NCP1392B, NCP1392D
High-Voltage Half-Bridge
Driver with Inbuilt
Oscillator
The NCP1392B/D is a self−oscillating high voltage MOSFET
driver primarily tailored for the applications using half bridge
topology. Due to its proprietary high−voltage technology, the driver
accepts bulk voltages up to 600 V. Operating frequency of the driver
can be adjusted from 25 kHz to 480 kHz using a single resistor.
Adjustable Brown−out protection assures correct bulk voltage
operating range. An internal 100 ms or 12.6 ms PFC delay timer
guarantee that the main downstream converter will be turned on in the
time the bulk voltage is fully stabilized. The device provides fixed
dead time which helps lowering the shoot−through current.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
www.onsemi.com
MARKING
DIAGRAMS
8
1392x
ALYWW
G
SOIC−8
CASE 751
1
1392x
Wide Operating Frequency Range − from 25 kHz to 480 kHz
Minimum frequency adjust accuracy $3%
Fixed Dead Time − 0.6 ms or 0.3 ms
Adjustable Brown−out Protection for a Simple PFC Association
100 ms or 12.6 ms PFC Delay Timer
Non−latched Enable Input
Internal 16 V VCC Clamp
Low Startup Current of 50 mA
1 A / 0.5 A Peak Current Sink / Source Drive Capability
Operation up to 600 V Bulk Voltage
Internal Temperature Shutdown
SOIC−8 Package
These are Pb−Free Devices
8
1
A
L
Y
WW
G
= Specific Device Code
x = B or D
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PINOUT DIAGRAM
Vboot
VCC
Rt
Mupper
BO
HB
GND
Mlower
Typical Applications
•
•
•
•
•
ORDERING INFORMATION
Flat Panel Display Power Converters
Low Cost Resonant SMPS
High Power AC/DC Adapters for Notebooks
Offline Battery Chargers
Lamp Ballasts
Device
Package
Shipping†
NCP1392BDR2G
SOIC−8
(Pb−Free)
2500 /
Tape & Reel
NCP1392DDR2G
SOIC−8
(Pb−Free)
2500 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 4
1
Publication Order Number:
NCP1392/D
NCP1392B, NCP1392D
Rbo1
M1
Dboot
Cboot
+
VCC
AC
OUTPUT
PFC FRONT STAGE
Vboot
+
Rt
Mupper
Cbulk
Bo
HB
GND
DC
OUTPUT
Mlower
M2
NCP1392
Rbo2
Rf
Rfmax
Rfstart
CSS
Figure 1. Typical Application Example
PIN FUNCTION DESCRIPTION
Pin #
Pin Name
Function
Pin Description
1
VCC
Supplies the Driver
2
Rt
Timing Resistor
3
BO
Brown−Out/Enable Input
4
GND
IC Ground
5
Mlower
Low−Side Driver Output
Drives the lower side MOSFET
6
HB
Half−Bridge Connection
Connects to the half−bridge output
7
Mupper
High−Side Driver Output
Drives the higher side MOSFET
8
Vboot
Bootstrap Pin
The driver accepts up to 16 V (given by internal zener clamp)
Connecting a resistor between this pin and GND, sets the operating frequency
Brown−Out function detects low input voltage conditions. Enable Input, when
brought above Vref_EN, stops the driver. Operation is then restored (without any
delay) when BO pin voltage drops by EN_Hyste below Vref_EN.
The floating supply terminal for the upper stage
www.onsemi.com
2
NCP1392B, NCP1392D
VDD
Vboot
S
Q
Pulse
Trigger
Level
Shifter
+
−
+
−
Ct
R
Q
CLK
R
Rt
Q
Mupper
D
Vref
S
Q
Vref
Bridge
UV
Detect
IDT
PFC Delay
(100ms)
VCC
VCC
Vref
VDD
PON
RESET
VCC
Mlower
DELAY
VCC
Management
VCC
Clamp
TSD
−
+
+
−
0.5ms
Filter
VrefEN
BO
+
−
+
−
20ms
Filter
VrefBO
Ihyster
SW
HIGH Level for 50ms After VCC On
GND
Figure 2. Internal Circuit Architecture (B Version)
www.onsemi.com
3
NCP1392B, NCP1392D
VDD
Vboot
S
Q
Pulse
Trigger
Level
Shifter
+
−
+
−
Ct
R
Q
CLK
R
Rt
Q
Mupper
D
Vref
S
Q
Vref
Bridge
UV
Detect
IDT
PFC Delay
(12.6 ms)
VCC
VCC
Vref
VDD
PON
RESET
VCC
Mlower
DELAY
VCC
Management
VCC
Clamp
TSD
BO
+
−
+
−
20ms
Filter
VrefBO
Ihyster
SW
HIGH Level for 6.3 ms After VCC On
GND
Figure 3. Internal Circuit Architecture (D Version)
www.onsemi.com
4
NCP1392B, NCP1392D
MAXIMUM RATINGS TABLE
Symbol
Rating
Vbridge
High Voltage Bridge Pin − Pin 6
Vboot −
Vbridge
Floating Supply Voltage
Value
Unit
−1 to +600
V
0 to 20
V
V
VDRV_HI
High−Side Output Voltage
Vbridge − 0.3 to
Vboot + 0.3
VDRV_LO
Low−Side Output Voltage
−0.3 to VCC +0.3
V
$50
V/ns
20
mA
−0.3 to 5
V
−0.3 to 10
V
178
°C/W
147
°C/W
dVbridge/dt Allowable Output Slew Rate
ICC
V_Rt
Maximum Current that Can Flow into VCC Pin (Pin 1), (Note 1)
Rt Pin Voltage
Maximum Voltage, All Pins (Except Pins 4 and 5)
RqJA
RqJA
Thermal Resistance Junction−to−Air, IC Soldered on 50
mm2
Thermal Resistance Junction−to−Air, IC Soldered on 200
Cooper 35 mm
mm2
Cooper 35 mm
−60 to +150
°C
ESD Capability, Human Body Model (All Pins Except HV Pins 6, 7 and 8)
2.0
kV
ESD Capability, Human Body Model (HV Pins 6, 7 and 8)
1.5
kV
ESD Capability, Machine Model
200
V
Storage Temperature Range
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device contains internal zener clamp connected between VCC and GND terminals. Current flowing into the VCC pin has to be limited
by an external resistor when device is supplied from supply which voltage is higher than VCCclamp (16 V typically). The ICC parameter is
specified for VBO = 0 V.
www.onsemi.com
5
NCP1392B, NCP1392D
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C,
VCC = 12 V, unless otherwise noted)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
Turn−On Threshold Level, VCC Going Up
1
VCCON
10
11
12
V
Minimum Operating Voltage after Turn−On
1
VCCmin
8
9
10
V
Startup Voltage on the Floating Section
1
VbootON
7.8
8.8
9.8
V
Cutoff Voltage on the Floating Section,
1
Vbootmin
7
8
9
V
VCC Level at which the Internal Logic gets Reset
1
VCCreset
−
6.5
−
V
Startup Current, VCC < VCCON, 0°C v Tamb v +125°C
1
ICC
−
−
50
mA
Startup Current, VCC < VCCON, −40°C v Tamb < 0°C
1
ICC
−
−
65
mA
Internal IC Consumption, No Output Load on Pins 8/7 − 5/4, Fsw = 100 kHz
1
ICC1
−
2.2
−
mA
Internal IC Consumption, 1 nF Output Load on Pins 8/7 − 5/4, Fsw = 100 kHz
1
ICC2
−
3.4
−
mA
Consumption in Fault Mode (Drivers Disabled, VCC > VCC(min), RT = 3.5 kW)
1
ICC3
−
2.56
−
mA
Consumption During PFC Delay Period, 0°C v Tamb v +125°C
ICC4
−
−
400
mA
Consumption During PFC Delay Period, −40°C v Tamb < 0°C
ICC4
−
−
470
mA
SUPPLY SECTION
Internal IC Consumption, No Output Load on Pin 8/7 FSW = 100 kHz
8
Iboot1
−
0.3
−
mA
Internal IC Consumption, 1 nF Load on Pin 8/7 FSW = 100 kHz
8
Iboot2
−
1.44
−
mA
Consumption in Fault Mode (Drivers Disabled, Vboot > Vbootmin)
8
Iboot3
−
0.1
−
mA
VCC Zener Clamp Voltage @ 20 mA
1
VCCclamp
15.4
16
17.5
V
Minimum Switching Frequency
(Rt = 35 kW on Pin 2 for DT = 600 ns, Rt = 70 kW on Pin 2 for DT = 300 ns)
2
FSW min
24.25
25
25.75
kHz
Maximum Switching Frequency (B Version), Rt = 3.5 kW on Pin 2, DT = 600 ns
2
FSW maxB
208
245
282
kHz
Maximum Switching Frequency (D Version), Rt = 3.5 kW on Pin 2, DT = 300 ns
2
FSW maxD
408
480
552
kHz
Reference Voltage for all Current Generations
2
Vref RT
3.33
3.5
3.67
V
Internal Resistance Discharging Csoft−start
2
Rtdischarge
−
500
−
W
5, 7
DC
48
50
52
%
Output Voltage Rise Time @ CL = 1 nF, 10−90% of Output Signal
5, 7
Tr
−
40
−
ns
Output Voltage Fall Time @ CL = 1 nF, 10−90% of Output Signal
5, 7
Tf
−
20
−
ns
Source Resistance
5, 7
ROH
−
12
−
W
Sink Resistance
5, 7
ROL
−
5
−
W
Deadtime (B Version)
5,7
TdeadB
540
610
720
ns
Deadtime (D Version)
5,7
TdeadD
260
305
360
ns
6,7,8
IHVLeak
−
−
5
mA
Brown−Out Input Bias Current
3
IBObias
−
0.01
−
mA
Brown−Out Level
3
VBO
0.95
1
1.05
V
Hysteresis Current, Vpin3 < VBO
3
IBO
15.6
18.2
20.7
mA
Reference Voltage for EN Input (B Version)
3
Vref EN
1.9
2
2.1
V
EN Comparator (not available in D Version)
−
Vref EN_D
−
−
−
V
Enable Comparator Hysteresis
3
EN_Hyste
−
100
−
mV
INTERNAL OSCILLATOR
Operating Duty Cycle Symmetry
NOTE:
Maximum capacitance directly connected to Pin 2 must be under 100 pF.
DRIVE OUTPUT
Leakage Current on High Voltage Pins to GND (600 Vdc)
PROTECTION
www.onsemi.com
6
NCP1392B, NCP1392D
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C,
VCC = 12 V, unless otherwise noted)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
Propagation Delay Before Drivers are Stopped
3
EN_Delay
−
0.5
−
ms
Delay Before Any Driver Restart (B Version)
−
PFC Delay
−
100
−
ms
PROTECTION
Delay Before Any Driver Restart (D Version)
−
PFC Delay
−
12.6
−
ms
Temperature Shutdown
−
TSD
140
−
−
°C
Hysteresis
−
TSDhyste
−
30
−
°C
Brown Out discharge time (B Version) (Note 2)
−
BOdisch
−
50
−
ms
Brown Out discharge time (D Version) (Note 2)
−
BOdisch
−
6.3
−
ms
2. Guaranteed by design.
www.onsemi.com
7
NCP1392B, NCP1392D
TYPICAL CHARACTERISTICS
11.01
8.98
11.00
8.97
8.96
10.98
VOLTAGE (V)
VOLTAGE (V)
10.99
10.97
10.96
10.95
10.94
8.95
8.94
8.93
8.92
10.93
8.91
10.92
−20
0
20
40
60
80
100
8.90
−40
120
0
20
40
60
TEMPERATURE (°C)
Figure 4. VCCon
Figure 5. VCCmin
8.85
8.10
8.80
8.05
8.75
8.70
8.65
80
100
120
8.00
7.95
7.90
7.85
8.60
8.55
−40
−20
TEMPERATURE (°C)
VOLTAGE (V)
VOLTAGE (V)
10.91
−40
7.80
−20
0
20
40
60
80
100
7.75
−40
120
−20
0
20
40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. VBOOTon
Figure 7. VBOOTmin
20
80
100
120
80
100
120
8
18
7
6
14
RESISTANCE (W)
RESISTANCE (W)
16
12
10
8
6
4
4
3
2
1
2
0
−40
5
−20
0
20
40
60
80
100
0
−40
120
−20
0
20
40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. ROH
Figure 9. ROL
www.onsemi.com
8
NCP1392B, NCP1392D
243.4
490
243.2
485
243.0
480
FREQUENCY (kHz)
FREQUENCY (kHz)
TYPICAL CHARACTERISTICS
242.8
242.6
242.4
242.2
475
470
465
460
242.0
241.8
−40
455
−20
0
20
40
60
80
100
450
−40
120
−20
0
TEMPERATURE (°C)
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 10. FSWmax (B Version)
Figure 11. FSWmax (D Version)
25.05
25.00
24.98
25.00
FREQUENCY (kHz)
FREQUENCY (kHz)
24.96
24.95
24.90
24.85
24.94
24.92
24.90
24.88
24.86
24.84
24.80
24.82
24.75
−40
−20
0
20
40
60
80
100
24.80
−40
120
−20
0
TEMPERATURE (°C)
45.0
450
40.0
400
35.0
350
30.0
300
25.0
20.0
15.0
50
40
60
100
120
150
5.0
20
80
200
100
0
60
250
10.0
−20
40
Figure 13. FSWmin (D Version)
CURRENT (mA)
CURRENT (mA)
Figure 12. FSWmin (B Version)
0.0
−40
20
TEMPERATURE (°C)
80
100
0
−40
120
TEMPERATURE (°C)
−20
0
20
40
60
TEMPERATURE (°C)
Figure 14. ICC_startup
Figure 15. ICC4
www.onsemi.com
9
80
100
120
NCP1392B, NCP1392D
TYPICAL CHARACTERISTICS
645
330
640
325
320
TIME (ns)
TIME (ns)
635
630
625
310
620
305
615
610
−40
315
−20
0
20
40
60
80
100
300
−40
120
−20
0
20
40
60
80
100
120
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Tdead (B Version)
Figure 17. Tdead (D Version)
14.0
109
108
13.5
107
13.0
TIME (ms)
TIME (ms)
106
105
104
103
12.5
12.0
102
101
11.5
100
90
−40
−20
0
20
40
60
80
100
11.0
−40
120
−20
0
2.008
1.015
2.006
1.014
2.004
1.013
2.002
2.000
1.998
1.996
1.010
1.992
1.008
20
40
60
80
1.011
1.009
0
60
1.012
1.994
−20
40
Figure 19. PFCdelay (D Version)
VOLTAGE (V)
VOLTAGE (V)
Figure 18. PFCdelay (B Version)
1.990
−40
20
TEMPERATURE (°C)
TEMPERATURE (°C)
80
100
1.007
−40
120
TEMPERATURE (°C)
−20
0
20
40
60
TEMPERATURE (°C)
Figure 21. VBO
Figure 20. Vref_EN
www.onsemi.com
10
80
100
120
NCP1392B, NCP1392D
580
110
560
108
540
106
VOLTAGE (mV)
RESISTANCE (W)
TYPICAL CHARACTERISTICS
520
500
480
460
104
102
100
98
96
440
94
420
92
400
−40
−20
0
20
40
60
80
100
90
−40
120
−20
0
20
40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 22. Rt_discharge
Figure 23. ENhyste
80
100
120
80
100
120
17.0
19.4
19.2
16.8
18.8
VOLTAGE (V)
CURRENT (mA)
19.0
18.6
18.4
18.2
18.0
17.8
16.6
16.4
16.2
16.0
17.6
17.4
−40
−20
0
20
40
60
80
100
15.8
−40
120
20
40
60
TEMPERATURE (°C)
Figure 24. IBO
Figure 25. VCC_clamp
600
500
FREQUENCY (kHz)
240
FREQUENCY (kHz)
0
TEMPERATURE (°C)
290
190
140
90
40
0.2
−20
400
300
200
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Irt (mA)
Irt (mA)
Figure 26. Irt and Appropriate Frequency
(B Version)
Figure 27. Irt and Appropriate Frequency
(D Version)
www.onsemi.com
11
NCP1392B, NCP1392D
APPLICATION INFORMATION
• Non−Latched Enable Input: The enable comparator
The NCP1392 is primarily intended to drive low cost half
bridge applications and especially resonant half bridge
applications. The IC includes several features that help the
designer to cope with resonant SPMS design. All features
are described thereafter:
• Wide Operating Frequency Range: The internal
current controlled oscillator is capable to operate over
wide frequency range. Minimum frequency accuracy is
$3%.
• Fixed Dead−Time: The internal dead−time helping to
fight with cross conduction between the upper and
lower power transistors. Three versions with different
dead time values are available to cover wide range of
applications.
• PFC Timer: Fixed delay is placed to IC operation
whenever the driver restarts (VCCON or BO_OK detect
events). This delay assures that the bulk voltage will be
stabilized in the time the driver provides pulses on the
outputs. Another benefit of this delay is that the soft
start capacitor will be full discharged before any restart.
• Brown−Out Detection: The BO input monitors bulk
voltage level via resistor divider and thus assures that
the application is working only for wanted bulk voltage
band. The BO input sinks current of 18.2 mA until the
VrefBO threshold is reached. Designer can thus adjust
the bulk voltage hysteresis according to the application
needs.
•
•
input is connected in parallel to the BO terminal to
allow the designer stop the output drivers when needed.
There is no PFC delay when enable input is released so
skip mode for resonant SMPS applications and
dimming for light ballast applications are possible.
Internal VCC Clamp: The internal zener clamp offers
a way to prepare passive voltage regulator to maintain
VCC voltage at 16 V in case the controller is supplied
from unregulated power supply or from bulk capacitor.
Low Startup Current: This device features maximum
startup current of 50 mA which allows the designer to
use high value startup resistor for applications when
driver is supplied from the auxiliary winding. Power
dissipation of startup resistor is thus significantly
reduced.
Current Controlled Oscillator
The current controlled oscillator features a high−speed
circuitry allowing operation from 50 kHz up to 960 kHz.
However, as a division by two internally creates the two Q
and Q outputs, the final effective signal on output Mlower
and Mupper switches in half frequency range. The VCO is
configured in such a way that if the current that flows out
from the Rt pin increases, the switching frequency also goes
up. Figure 28 shows the architecture of this oscillator.
V DD
S
Q
A
Q
B
D
+
−
+
−
Rsoft−start R
t
+
−
CLK
Vref
R
IDT
+
−
Dead
Time
Ct
Vref Rt
Csoft−start
Rt
Delay
From PFC Delay
PON
Reset
From EN
Cmp.
Figure 28. The Internal Current Controlled Oscillator Architecture
The internal timing capacitor Ct is charged by current
which is proportional to the current flowing out from the
Rt pin. The discharging current IDT is applied when voltage
on this capacitor reaches 2.5 V. The output drivers are
disabled during discharge period so the dead time length is
given by the discharge current sink capability. Discharge
sink is disabled when voltage on the timing capacitor
reaches zero and charging cycle starts again. The charging
current and thus also whole oscillator is disabled during the
PFC delay period to keep the IC consumption below 400 mA.
www.onsemi.com
12
NCP1392B, NCP1392D
This is valuable for applications that are supplied from
auxiliary winding and VCC capacitor is supposed to provide
energy during PFC delay period.
For the resonant applications and light ballast applications
it is necessary to adjust minimum operating frequency with
high accuracy. The designer also needs to limit maximum
operating and startup frequency. All these parameters can be
adjusted using few external components connected to the Rt
pin as depicted in Figure 29.
NCP1392
Rt
V CC
Rfmax
Rfmax−OCP
Rbias
Rfstart
D1
Rt
Rcomp
(to secondary
voltage regulator)
Ccomp
CSS
TLV431
Voltage Feedback
(to primary
current sensor)
Current Feedback
Figure 29. Typical Rt Pin Connection
The TLV431 shunt regulator is used in the example from
figure 4 to prepare current feedback loop. Diode D1 is used
to enable regulator biasing via resistor Rbias. Total
saturation voltage of this solution is 1.25 + 0.6 = 1.85 V for
room temperature. Shottky diode will further decrease
saturation voltage. Rfmax − OCP resistor value, limits the
maximum frequency that can be pushed by this regulation
loop. This parameter is not temperature stable because of the
D1 temperature drift.
The minimum switching frequency is given by the Rt
resistor value. This frequency is reached if there is no
optocoupler or current feedback action and soft start period
has been already finished. The maximum switching
frequency excursion is limited by the Rfmax selection. Note
that the Fmax value is influenced by the optocoupler
saturation voltage value. Resistor Rfstart together with
capacitor CSS prepares the soft start period after PFC timer
elapses. The Rt pin is grounded via an internal switch during
the PFC delay period to assure that the soft start capacitor
will be fully discharged via Rfstart resistor.
There is a possibility to connect other control loops (like
current control loop) to the Rt pin. The only one limitation
lies in the Rt pin reference voltage which is VrefRt = 3.5 V.
Used regulator has to be capable to work with voltage lower
than VrefRt.
Brown−Out Protection
The Brown−Out circuitry (BO) offers a way to protect the
application from low DC input voltages. Below a given
level, the controller blocks the output pulses, above it, it
authorizes them. The internal circuitry, depicted by
Figure 30, offers a way to observe the high−voltage (HV)
rail.
www.onsemi.com
13
NCP1392B, NCP1392D
Vbulk
Rupper
BO
+
−
+
−
20ms
Filter
BO_OK to and gates
VrefBO
Rlower
SW
To PFC Delay
IBO
High Level for BOdisch time after VCC ON
Figure 30. The internal Brown−Out Configuration with an Offset Current Sink
A resistive divider made of Rupper and Rlower, brings a
portion of the HV rail on Pin 3. Below the turn−on level,
the 18.2 mA current sink (IBO) is on. Therefore, the turn−on
level is higher than the level given by the division ratio
brought by the resistive divider. To the contrary, when the
internal BO_OK signal is high (PFC timer runs or Mlower
and Mupper pulse), the IBO sink is deactivated. As a result,
it becomes possible to select the turn−on and turn−off levels
via a few lines of algebra:
IBO is on
Vref BO + V bulk1 @
R lower
R lower ) R upper
* I BO @
ǒ
R lower @ R upper
Ǔ
R lower ) R upper
(eq. 1)
IBO is off
R lower
Vref BO + V bulk2 @
R lower ) R upper
(eq. 2)
We can extract Rlower from Equation 2 and plug it into Equation 1, then solve for Rupper:
R lower + Vref BO @
V bulk1 * V bulk2
I BO @ ǒV bulk2 * Vref BOǓ
R upper + R lower @
V bulk2 * Vref BO
(eq. 3)
(eq. 4)
Vref BO
If we decide to turn−on our converter for Vbulk1 equals 350 V and turn it off for Vbulk2 equals 250 V, then for IBO = 18.2 mA
and VrefBO = 1.0 V we obtain:
Rupper = 5.494 MW
Rlower = 22.066 kW
The bridge power dissipation is 4002 / 5.517 MW = 29 mW when front−end PFC stage delivers 400 V. Figure 31 simulation
result confirms our calculations.
www.onsemi.com
14
NCP1392B, NCP1392D
Figure 31. Simulation Results for 350/250 ON/OFF Brown−Out Levels
comparator is supposed to either hold the IBO sink turned
ON (if the bulk voltage level is not sufficient) or let it turned
OFF (if the bulk voltage is higher than Vbulk1).
See Figures 10 − 13 for better understanding on how the
BO input works.
The IBO current sink is turned ON for BOdisch time after
any controller restart to let the BO input voltage stabilize
(there can be connected big capacitor to the BO input and the
IBO is only 18.2 mA so it will take some time to discharge).
Once the BOdisch time one shoot pulse ends the BO
Vbulk_ON
Vbulk_OFF
Vbulk
1V
IBO is turned ON after Vcc_ON by
internal logic (for BOdisch time)
VBO
BO_OK
Vcc
< BOdisch
DRV_EN
Figure 32. BO Input Functionality − Vbulk2 < Vbulk < Vbulk1
www.onsemi.com
15
NCP1392B, NCP1392D
Vbulk_ON
Vbulk_OFF
Vbulk
1V
VBO
BO_OK
Vcc
PFCdelay
DRV_EN
Figure 33. BO Input Functionality −Vbulk2 < Vbulk < Vbulk1, PFC Start Follows
Vbulk_ON
Vbulk_OFF
Checking VBO by activating IBO
sink, released after BOdisch time
Vbulk
1V
BOdisch
VBO
The drivers are activated with delay specify by
PFCdelay after Vcc_ON, IBO sing has been
turned OFF by BOdisch time after Vcc_ON, BO
capacitor had enough time to charge
BO_OK
Vcc
PFCdelay
DRV_EN
Figure 34. BO Input Functionality − Vbulk > Vbulk1
www.onsemi.com
16
NCP1392B, NCP1392D
Vbulk_ON
Vbulk_OFF
Vbulk
1V
VBO
BO_OK
Vcc
PFCdelay
DRV_EN
Figure 35. BO Input Functionality − Vbulk < Vbulk2, PFC Start Follows
Non−Latched Enable Input (B Version only)
This input offers other features to the NCP1392 like
dimming function for lamp ballasts (Figure 36) or skip
mode capability for resonant converters (Figures 37
and 39).
The non−latched input stops output drivers immediately
the BO terminal voltage grows above 2 V threshold. The
enable comparator features 100 mV hysteresis so the BO
terminal has to go down below 1.9 V to recover IC operation.
Vbulk
VCC
R2
+
−
Q2
R3
to AND gates
−
+
Rupper
0.5ms
Filter
VrefEN
R4
BO
+
−
SW
Rlower
+
−
20ms
Filter
to AND gates
VrefBO
Ihyste
To PFC Delay
Rt
High Level for BOdisch time after VCC ON
D1
Rfstart
Rt
NCP1392
R1
Dimming
Input
Q1
CSS
GND
Figure 36. Dimming Feature Implementation Using Nonlatched Input on BO Terminal
www.onsemi.com
17
NCP1392B, NCP1392D
The dimming feature can be easily aid to the ballast
application by adding two bipolar transistors (Figure 14).
Transistor Q2 pullup BO input when dimming signal is high.
In the same time the Q1 discharges soft start capacitor via
diode D1. Ballast application is enabled (including
soft−start phase) when dimming signal becomes low again.
Vbulk
−
+
Rupper
+
−
D1
to AND gates
0.5ms
Filter
VrefEN
BO
+
−
SW
Rlower
+
−
to AND gates
20ms
Filter
VrefBO
Ihyste
To PFC Delay
R2
Rt
High Level for BOdisch time after VCC ON
Rfstart
Voltage
Feedback
Rt
NCP1392
CSS
R1
GND
Figure 37. Skip Mode Feature Implementation (Temperature Dependent, Cost Effective)
VCC
Vbulk
R6
R1
−
+
Q1
+
−
0.5ms
Filter
to AND gates
VrefEN
Rupper
R3
R2
BO
+
−
SW
Rlower
Soft−Start After Skip (If Needed)
+
−
20ms
Filter
to AND gates
VrefBO
Ihyste
D1
To PFC Delay
R5
Rt
High Level for BOdisch time after VCC ON
Rfstart
C1
Voltage
Feedback
Rt
NCP1392
Q2
R4
CSS
GND
Figure 38. Skip Mode with Transistor Feature Implementation (Temperature Dependent, Cost Effective)
www.onsemi.com
18
NCP1392B, NCP1392D
Vbulk
VCC
R6
R1
−
+
Rupper
Q1
+
−
0.5ms
Filter
to AND gates
VrefEN
R3
R2
BO
+
−
SW
Rlower
+
−
20ms
Filter
to AND gates
VrefBO
Ihyste
To PFC Delay
R5
Rt
High Level for BOdisch time after VCC ON
Rfstart
C1
Voltage
Feedback
Rt
NCP1392
IC1
TLV431
CSS
R4
GND
Figure 39. Skip Mode Feature Implementation (Better Accuracy)
Figures 37 and 39 shows skip mode feature
implementation using NCP1392 driver. Voltage across
resistor R1 (R4) increases when converter enters light load
conditions. The enable comparator is triggered when
voltage across R1 is higher than Vref EN + Vf(D1) for
connection from Figure 37 (voltage across R4 is higher than
1.24 V for connection from figure 16). IC then prevents
outputs from pulsing until BO terminal voltage decreases
below 1.92 V.
Note that enable comparator serves also as an automatic
overvoltage protection. When bulk voltage is too high, the
enable input is triggered via BO divider.
Following equations can be used for easy calculations of
devices connected to Rt pin:
Minimum frequency:
Rt +
3.5 @ k
Frequency * q
Maximum frequency where soft−start begins:
R fstart +
3.5 @ k @ R t
(eq. 6)
Frequency @ R t * R t @ q * 3.5 @ k
The soft−start duration is set by Css capacitor:
C SS +
SS duration
R fstart @ 5
(eq. 7)
A resistor to set maximum frequency, if the optocoupler is
fully conductive is calculated by the following equation:
R (R4)R5) + −
ǒ−3.5 ) V ce_satǓ @ k @ R t
Frequency @ R t − R t @ q − 3.5 @ k ) k @ V ce_sat
(eq. 8)
The constants in the equations are as follows:
Version B: k = 244.4106, q = 0.555103
Version D: k = 478.9106, q = 1.053103
(eq. 5)
www.onsemi.com
19
NCP1392B, NCP1392D
The High−Voltage Driver
the upper side MOSFET. The VCC for floating driver section
is provided by Cboot capacitor that is refilled by external
bootstrap diode.
Figure 40 shows the internal architecture of the
high−voltage section. The device incorporates an upper
UVLO circuitry that makes sure enough Vgs is available for
Boot
Pulse
Trigger
S
Level
Shifter
Cboot
Q
Hgd
R
Q
HB
UV
Detect
DEAD TIME
Vbulk
Dboot
from PFC
Delay
VCC
Vaux
+
B
B
A
Lgd
A
Delay
GND
from latch
high if OK
Figure 40. The Internal High−Voltage Section of the NCP1392
matching between these propagating signals. As stated in the
maximum rating section, the floating portion can go up to
600 Vdc and makes the IC perfectly suitable for offline
applications featuring a 400 V PFC front−end stage.
The A and B outputs are delivered by the internal logic, as
depicted in block diagram. This logic is constructed in such
a way that the Mlower driver starts to pulse firs after any
driver restart. The bootstrap capacitor is thus charged during
first pulse. A delay is inserted in the lower rail to ensure good
www.onsemi.com
20
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
onsemi Website: www.onsemi.com
◊
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
工商网监
湘ICP备2023018690号
