NCP1397A

NCP1397A, NCP1397B High Performance Resonant Mode Controller with Integrated High-Voltage Drivers The NCP1397 is a high performance controller that can be utilized in half bridge resonant topologies such as series resonant, parallel resonant and LLC resonant converters. It integrates 600 V gate drivers, simplifying layout and reducing external component count. With its unique architecture, including a 500 kHz Voltage Controlled Oscillator whose control mode permits flexibility when an ORing function is required, the NCP1397 delivers everything needed to build a reliable and rugged resonant mode power supply. The NCP1397 provides a suite of protection features with configurable settings to optimize any application. These include: auto−recovery or fault latch−off, brown−out, open optocoupler, soft−start and short−circuit protection. Deadtime is also adjustable to overcome shoot through current. Features http://onsemi.com MARKING DIAGRAMS 1 6 1 SO−16, LESS PIN 13 D SUFFIX CASE 751AM 16 NCP1397xG AWLYWW 1 • • • • • • • • • • • • • • • • • High−Frequency Operation from 50 kHz up to 500 kHz 600 V High−Voltage Floating Driver Adjustable Minimum Switching Frequency with $3% Accuracy Adjustable Deadtime from 100 ns to 2 ms. Startup Sequence Via an Externally Adjustable Soft−Start Brown−Out Protection for a Simpler PFC Association Latched Input for Severe Fault Conditions, e.g. Over Temperature or OVP Timer−Based Input with Auto−Recovery Operation for Delayed Event Reaction Latched Overcurrent Protection Disable Input for Immediate Event Reaction or Simple ON/OFF Control VCC Operation up to 20 V Low Startup Current of 300 mA 1 A / 0.5 A Peak Current Sink / Source Drive Capability Common Collector Optocoupler Connection for Easier ORing Optional Common Emitter Optocoupler Connection Internal Temperature Shutdown These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant x A WL Y WW G = A or B = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS CSS(dis) 1 Fmax 2 Ctimer 3 Rt 4 BO 5 FB 6 DT 7 Skip/Disable 8 (Top View) 12 VCC 11 Mlower 10 GND 9 Fault 16 Vboot 15 Mupper 14 HB ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 26 of this data sheet. Typical Applications • Flat Panel Display Power Converters • High Power ac−dc Adapters for Notebooks • Computing Power Supplies • Industrial and Medical Power Sources • Offline Battery Chargers © Semiconductor Components Industries, LLC, 2009 October, 2009 − Rev. 0 1 Publication Order Number: NCP1397/D NCP1397A, NCP1397B R18 Figure 1. Typical Application Example PIN FUNCTION DESCRIPTION Pin # 1 2 3 4 5 6 7 8 Pin Name CSS(dis) Fmax Ctimer Rt BO FB DT Skip/Disable Function Soft−Start Discharge Maximum frequency clamp Timer duration Minimum frequency clamp Brown−Out Feedback Deadtime Skip or Disable input Pin Description Soft−start capacitor discharge pin. Connect to the soft−start capacitor to reset it before startup or during overload conditions. A resistor sets the maximum frequency excursion Sets the timer duration in presence of a fault Connecting a resistor to this pin, sets the minimum oscillator frequency reached for VFB = 1 V. Detects low input voltage conditions. When brought above Vlatch (4 V typically), it fully latches off the controller. Injecting current into this pin increases the oscillation frequency up to Fmax. A simple resistor adjusts the dead−time width Upon release, a clean startup sequence occurs if VFB < 0.3 V. During the skip mode, when FB doesn’t drop below 0.3 V, the IC restarts without soft−start sequence. When asserted, the external timer starts to countdown and shuts down the controller at the end of its time duration. Simultaneously the Soft−Start discharge switch is activated so the converter operating frequency goes up to protect application power stage. This input features also second fault comparator with higher threshold (1.5 V typically) that: A) Speeds up the timer capacitor charging current 8 times – NCP1397A B) latches off the IC permanently – NCP1397B In both versions the second fault comparator helps to protect application in case of short circuit on the output or transformer secondary winding. − Drives the lower side MOSFET The controller accepts up to 20 V Increases the creepage distance Connects to the half−bridge output Drives the higher side MOSFET The floating VCC supply for the upper stage 9 Fault Fault detection input 10 11 12 13 14 15 16 GND Mlower VCC NC HB Mupper Vboot Analog ground Low side output Supplies the controller Not connected Half−bridge connection High side output Bootstrap pin http://onsemi.com 2 NCP1397A, NCP1397B VDD Temperature Shutdown S D + − Rt C I = Imax for Vfb = 5.3 V I = 0 for Vfb < Vfb(min) VDD Imax VFB = 5 VDD Vref Itimer1 Fmax Level Shifter Timeout Fault Itimer2 Vdd PON Reset Fault Timeout Fault Fast Fault IDT + DT Adj. Clk R 50% DC FF VCC Management Mupper Q Q Vref VBOOT Imin VFB ≤ VFB(off) Vref BO Reset UVLO HB Timer + − + Vref NC PON Reset Fault VCC Fault SS(dis) FB + − G=1 > 0 only VDD V = V(FB) − VFB(min) Mlower RFB + VFB(fault) + − + VFB(min) − Vref + Deadtime Adjustment Vref Skip/Disable + 20 ns Noise Filter GND Skip/ Disable DT VDD IDT IBO 20 ms Noise Filter Q Q R PON Reset BO + − + VBO + − + Vlatch + − 20 ms Noise Filter S Fault + Vref(fault) + − Vref(OCP) + 1 ms Noise Filter Figure 2. Internal Circuit Architecture (NCP1397A) http://onsemi.com 3 NCP1397A, NCP1397B VDD Temperature Shutdown S D + − Rt C I = Imax for Vfb = 5.3 V I = 0 for Vfb < Vfb_min VDD PON Reset Fault Timeout Fault Itimer1 Fmax If FAULT Itimer else 0 Timer Level Shifter Timeout Fault Fast Fault IDT + DT Adj. Clk R 50% DC FF VCC Management Mupper Q Q Vref VBOOT Imin VFB ≤ VFB(off) Vref BO Reset Imax Vfb = 5 VDD Vref UVLO HB + − + Vref NC PON Reset Fault VCC Fault SS(dis) FB + − G=1 > 0 only VDD V = V(FB) − VFB(min) Mlower RFB + VFB(fault) + − + VFB(min) − Vref + Deadtime Adjustment Vref Skip + GND Skip/ Disable 20 ns Noise Filter DT IDT VDD 20 ms Noise Filter IBO Q BO + − + VBO Fault + Vref(fault) Vref(OCP) + + − + − 1 ms Noise Filter + − + Vlatch 20 ms Noise Filter S Q R PON Reset Figure 3. Internal Circuit Architecture (NCP1397B) http://onsemi.com 4 NCP1397A, NCP1397B MAXIMUM RATINGS Rating High Voltage bridge pin, pin 14 Floating supply voltage, ground referenced High side output voltage Low side output voltage Allowable output slew rate Power Supply voltage, pin 12 Maximum voltage, all pins (except pin 11 and 10) Thermal Resistance Junction−to−Air, PDIP version Thermal Resistance Junction−to−Air, SOIC version Storage Temperature Range ESD Capability, Human Body Model (HBM) (All pins except HV pins) ESD Capability, Machine Model (MM) Symbol VBRIDGE VBOOT − VBRIDGE VDRV(HI) VDRV(LO) dVBRIDGE/dt VCC − RqJA RqJA − − − Value −1 to 600 0 to 20 VBRIDGE−0.3 to VBOOT+0.3 −0.3 to VCC+0.3 50 20 −0.3 to 10 100 130 −60 to +150 2 200 Unit V V V V V/ns V V °C/W °C/W °C kV V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device(s) contains ESD protection and exceeds the following tests: Human Body Model 2000 V per JEDEC Standard JESD22−A114E Machine Model 200 V per JEDEC Standard JESD22−A115−A 2. This device meets latchup tests defined by JEDEC Standard JESD78. http://onsemi.com 5 NCP1397A, NCP1397B ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Symbol SUPPLY SECTION VCC(on) VCC(min) Vboot(on) Vboot(min) Istartup VCC(reset) ICC1 ICC2 ICC3 Turn−on threshold level, VCC going up Minimum operating voltage after turn−on Startup voltage on the floating section Cutoff voltage on the floating section Startup current, VCC < VCC(on) VCC level at which the internal logic gets reset Internal IC consumption, no output load on pin 15/14 – 11/10, FSW = 300 kHz Internal IC consumption, 1 nF output load on pin 15/14 – 11/10, FSW = 300 kHz Consumption in fault or disable mode (All drivers disabled, Rt = 34 kW, RDT = 10 kW) 12 12 16−14 16−14 12 12 12 12 12 9.7 8.7 8 7.4 − − − − − 10.5 9.5 9 8.4 − 6.6 4 11 1.5 11.3 10.3 10 9.4 300 − − − − V V V V mA V mA mA mA Rating Pin Min Typ Max Unit VOLTAGE CONTROL OSCILLATOR (VCO) FSW(min) FSW(max) FBSW DC Tdel1 Tdel2 Vref(Rt) RFB VFB(min) VFB(off) VFBoff(hyste) Tr Tf ROH ROL Tdead Tdead(max) Tdead(min) IHV(LEAK) TIMERS Itimer1 Timer capacitor charge current during feedback fault or when Vref(fault) < Vpin9 < Vref(OCP) 3 150 175 190 mA Minimum switching frequency, Rt = 34 kW on pin 4, Vpin6 = 0.8 V, DT = 300 ns Maximum switching frequency, Rf(max) = 1.9 kW on pin 2, Vpin6 > 5.3 V, Rt = 34 kW, DT = 300 ns Feedback pin swing above which Df = 0 Operating duty−cycle symmetry Delay before driver restart from fault or disable mode Delay before driver restart after VCC(on) event (Note 4) Reference voltage for Rt pin 4 2 6 11−15 − − 4 58.2 440 − 48 − − 2.18 60 500 5.3 50 700 11 2.3 61.8 560 − 52 − − 2.42 kHz kHz V % ns ms V FEEDBACK SECTION Internal pulldown resistor Voltage on pin 6 below which the FB level has no VCO action Voltage on pin 6 below which the controller considers the FB fault Feedback fault comparator hysteresis 6 6 6 6 − − 240 − 20 1.1 280 45 − − 320 − kW V mV mV DRIVE OUTPUT Output voltage risetime @ CL = 1 nF, 10−90% of output signal Output voltage falltime @ CL = 1 nF, 10−90% of output signal Source resistance Sink resistance Deadtime with RDT = 10 kW from pin 7 to GND Maximum deadtime with RDT = 82 kW from pin 7 to GND Minimum deadtime, RDT = 3 kW from pin 7 to GND Leakage current on high voltage pins to GND 15−14/11−10 15−14/11−10 15−14/11−10 15−14/11−10 7 7 7 14, 15,16 − − − − 250 − − − 40 20 13 5.5 290 2 100 − − − − − 340 − − 5 ns ns W W ns ms ns mA 3. The IC does not activate soft−start (unless the feedback pin voltage is below 0.3 V) when the skip/disable input is released, this is for skip cycle implementation. 4. Guaranteed by design. http://onsemi.com 6 NCP1397A, NCP1397B ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Symbol TIMERS Itimer2 Ttimer TtimerR Vtimer(on) Vtimer(off) RSS(dis) Vref(Skip) Hyste(Skip) Vref(Fault) Hyste(Fault) Vref(OCP) Hyste(OCP) Tp(Disable) IBO(bias) VBO IBO Vlatch TSD TSD(hyste) Timer capacitor charge current when Vpin9 > Vref(OCP) (Icharge1 + Icharge2) – A version only Timer duration with a 1 mF capacitor and a 1 MW resistor, Itimer1 current applied Timer recurrence in permanent fault, same values as above Voltage at which pin 3 stops output pulses Voltage at which pin 3 restarts output pulses Soft−start discharge switch channel resistance 3 3 3 3 3 1 1.1 − − 3.8 0.95 − 1.3 24 1.4 4 1 100 1.5 − − 4.2 1.05 − mA ms s V V W Rating Pin Min Typ Max Unit PROTECTION Reference voltage for Skip/Disable input (Note 4) Hysteresis for Skip/Disable (Note 4) Reference voltage for Fault comparator Hysteresis for fault comparator input Reference voltage for OCP comparator Hysteresis for OCP comparator input Propagation delay from disable input to the drive shutdown Brown−Out input bias current Brown−Out level Hysteresis current, Vpin5 > VBO Latching voltage Temperature shutdown Hysteresis 8 8 9 9 9 9 8 5 5 5 5 − − 630 − 0.99 − 1.47 − − − 0.99 25 3.7 140 − 660 45 1.04 60 1.55 90 60 0.02 1.04 28 4 − 30 690 − 1.09 − 1.63 − 100 − 1.09 31 4.3 − − mV mV V mV V mV ns mA V mA V °C °C 3. The IC does not activate soft−start (unless the feedback pin voltage is below 0.3 V) when the skip/disable input is released, this is for skip cycle implementation. 4. Guaranteed by design. http://onsemi.com 7 NCP1397A, NCP1397B TYPICAL CHARACTERISTICS 10.55 9.52 9.50 10.50 VCC(min) (V) VCC(on) (V) 9.48 9.46 9.44 9.42 9.40 10.35 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 110 125 9.38 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 110 125 10.45 10.40 Figure 4. VCC(on) Threshold 60.05 60 FSW(max) (kHz) 59.95 59.9 59.85 59.8 59.75 510 509 508 507 506 505 504 −40 −20 0 20 40 60 TEMPERATURE (°C) 80 100 120 Figure 5. VCC(min) Threshold FSW(min) (kHz) 503 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 110 125 Figure 6. FSW(min) Frequency Clamp 23.0 22.5 22.0 21.5 21.0 20.5 20.0 19.5 19.0 18.5 −40 −25 −10 5 20 35 50 65 80 95 110 125 Vref(skip) (V) RFB (kW) 0.661 0.660 0.659 0.658 0.657 0.656 Figure 7. FSW(max) Frequency Clamp 0.655 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 8. Pulldown Resistor (RFB) Figure 9. Skip/Disable Threshold (Vref(skip)) http://onsemi.com 8 NCP1397A, NCP1397B TYPICAL CHARACTERISTICS 17.0 16.0 15.0 14.0 ROHA (W) 13.0 12.0 11.0 10.0 9.0 8.0 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 110 125 ROLA (W) 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 110 125 Figure 10. Source Resistance (ROH) Figure 11. Sink Resistance (ROL) 114 113 112 Tdead(nom) (ns) −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 110 125 Tdead(min) (ns) 111 110 109 108 107 106 105 104 297 296 295 294 293 292 291 290 289 288 287 286 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 110 125 Figure 12. Tdead(min) 2.065 2.060 Tdead(max) (ms) 2.055 2.050 2.045 2.040 2.035 −40 −25 −10 5 4.035 4.030 4.025 Vlatch (V) 4.020 4.015 4.010 Figure 13. Tdead(nom) 20 35 50 65 80 95 110 125 4.005 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 14. Tdead(max) Figure 15. Latch Level (Vlatch) http://onsemi.com 9 NCP1397A, NCP1397B TYPICAL CHARACTERISTICS 1.038 1.036 1.034 IBO (mA) 20 35 50 65 80 95 110 125 VBO (V) 1.032 1.030 1.028 1.026 1.024 1.022 −40 −25 −10 5 28.8 28.6 28.4 28.2 28.0 27.8 27.6 27.4 27.2 27.0 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. Brown−Out Reference (VBO) 1.050 1.048 1.046 1.044 Vref(fault) (V) 1.042 1.040 1.038 1.036 1.034 1.032 −40 −25 −10 5 20 35 50 65 80 95 110 125 Itimer1 (mA) 178 176 174 172 170 168 Figure 17. Brown−Out Hysteresis Current (IBO) 166 −40 −25 −10 5 20 35 50 65 80 95 110 12 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. Fault Input Reference (Vref(fault)) 1.565 1.560 1.555 Vref(OCP) (V) 1.550 1.545 1.540 1.535 1.530 −40 −25 −10 5 20 35 50 65 80 95 110 125 Itimer2 (mA) 1.34 1.33 1.32 1.31 1.30 1.29 1.28 1.27 1.26 Figure 19. Ctimer 1st Current (Itimer1) 1.25 −40 −25 −10 5 20 35 50 65 80 95 110 12 TEMPERATURE (°C) TEMPERATURE (°C) Figure 20. OCP reference (Vref(OCP)) Figure 21. Ctimer 2nd Current (Itimer2) http://onsemi.com 10 NCP1397A, NCP1397B TYPICAL CHARACTERISTICS 4.035 4.030 4.025 VFB(off) (V) 20 35 50 65 80 95 110 125 4.020 4.015 4.010 4.005 −40 −25 −10 5 0.288 0.286 0.284 0.282 0.280 0.278 0.276 0.274 −40 −25 −10 5 20 35 50 65 80 95 110 125 Vtimer(on) (V) TEMPERATURE (°C) TEMPERATURE (°C) Figure 22. Fault Timer Ending Voltage (Vtimer(on)) Figure 23. FB Fault Detection Threshold (VFB(fault)) 1.000 0.999 0.998 Vtimer(off) (V) 0.997 0.996 0.995 0.994 0.993 0.992 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 110 125 Figure 24. Fault Timer Reset Voltage (Vtimer(off)) http://onsemi.com 11 NCP1397A, NCP1397B APPLICATION INFORMATION The NCP1397A/B includes all necessary features to help building a rugged and safe switch−mode power supply featuring an extremely low standby power. The below bullets detail the benefits brought by implementing the NCP1397A/B controller: • Wide frequency range: A high−speed Voltage Control Oscillator allows an output frequency excursion from 50 kHz up to 500 kHz on Mlower and Mupper outputs. • Adjustable dead−time: Due to a single resistor wired to ground, the user has the ability to include some dead−time, helping to fight cross−conduction between the upper and the lower transistor. • Adjustable soft−start: Every time the controller starts to operate (power on), the switching frequency is pushed to the programmed starting value by external components (RFmin//RFstart) and slowly moves down toward the minimum frequency, until the feedback loop closes. The soft−start discharge input (SS(dis)) discharges the Soft−Start capacitor before any IC restart excluding the restart after Disable is released AND FB voltage is higher than 0.3 V. The Soft−Start discharge switch also activates in case the Fault input detects the overload conditions. • Adjustable minimum and maximum frequency excursion: In resonant applications, it is important to stay away from the resonating peak to keep operating the converter in the right region. Thanks to a single external resistor, the designer can program its lowest frequency point, obtained in lack of feedback voltage (during the startup sequence or in short−circuit conditions). Internally trimmed capacitors offer a $3% precision on the selection of the minimum switching frequency. The adjustable upper stop being less precise to $12%. • Low startup current: When directly powered from the high−voltage DC rail, the device only requires 300 mA to startup. • Brown−Out detection: To avoid operation from a low input voltage, it is interesting to prevent the controller from switching if the high−voltage rail is not within the right boundaries. Also, when teamed with a PFC front−end circuitry, the brown−out detection can ensure a clean startup sequence with soft−start, ensuring that the PFC is stabilized before energizing the resonant tank. The BO input features a 28 mA hysteresis current for the lowest consumption. • Adjustable fault timer duration: When a fault is detected on the Fault input or when the FB path is broken, timer pin starts to charge an external capacitor. If the fault is removed, the timer opens the charging path and nothing happens. When the timer reaches its selected duration (via a capacitor on Pin 3), all pulses are stopped. The controller now waits for the discharge via an external resistor on Pin 3 to issue a new clean startup sequence via soft−start. • Cumulative fault events: In the NCP1397A/B, the timer capacitor is not reset when the fault disappears. It actually integrates the information and cumulates the occurrences. A resistor placed in parallel with the capacitor will offer a simple way to adjust the discharge rate and thus the auto−recovery retry rate. • Overcurrent detection using Fault input: The fault input is specifically designed to protect LLC application in case of short circuit or overload. In case the voltage on this input grows above first threshold the Itimer current source is activated and Fault timer capacitor starts charging. Simultaneously the Soft−Start discharge switch is activated to increase operating frequency of the converter. The IC stops operation in case the Fault timer elapses. The Fault input includes also second fault comparator that: − Speeds up the fault timer capacitor charging by increasing the Itimer1 current to Itimer2 – NCP1397A − Latches off the device – NCP1397B The second fault comparator thus helps to protect the power stage in case of hard short circuit (like shorted transformer winding etc.) • Skip cycle possibility: The absence of the soft−start on the Skip/Disable input (in case the VFB > 0.3 V) offers an easy way to implement skip cycle when power saving features are necessary. A simple resistive divider from the feedback pin to the Skip/Disable input, and skip can be implemented. • Broken feedback loop detection: Upon startup or any time during operation, if the FB signal is missing, the timer starts to charge timer capacitor. If the loop is really broken, the FB level does not grow−up before the timer ends charging. The controller then stops all pulses and waits until the timer pin voltage collapses to 1 V typically before a new attempt to restart, via the soft−start. If the optocoupler is permanently broken, a hiccup takes place. • Common collector or common emitter optocoupler connection options: This IC allows the designer to select from two possible optocoupler configurations. Voltage−Controlled Oscillator The VCO section features a high−speed circuitry allowing operation from 100 kHz up to 1 MHz. However, as a division by two internally creates the two Q and /Q outputs, the final effective signal on output Mlower and Mupper switches between 50 kHz and 500 kHz. The VCO is configured in such a way that if the feedback pin voltage goes up, the switching frequency also goes up. Figure 25 shows the architecture of the VCO oscillator. http://onsemi.com 12 NCP1397A, NCP1397B VDD FBinternal max FSW max 0 to IFmax D Cint + + Imin Vref Rt Rt sets Fmin for V(FB) = 0 S Q Q + Clk R VDD IDT Vref DT RDT sets the deadtime VCC Fmax Fmax sets the maximum FSW FB RFB 20 k Imin A B VDD + Vb(off) + VFB < VFB(off) Start fault timer Figure 25. The Simplified VCO Architecture The designer needs to program the maximum switching frequency and the minimum switching frequency. In LLC configurations, for circuits working above the resonant frequency, a high precision is required on the minimum frequency, hence the $3% specification. This minimum switching frequency is actually reached when no feedback closes the loop. It can happen during the startup sequence, a strong output transient loading or in a short−circuit condition. By installing a resistor from Pin 4 to GND, the minimum frequency is set. Using the same philosophy, wiring a resistor from Pin 2 to GND will set the maximum frequency excursion. To improve the circuit protection features, we have purposely created a dead zone, where the feedback loop has no action. This is typically below 1.1 V. Figure 26 details the arrangement where the internal voltage (that drives the VCO) varies between 0 and 2.3 V. However, to create this swing, the feedback pin (to which the optocoupler emitter connects), will need to swing typically between 1.1 V and 5.3 V. VCC FB R1 11.3 k + R3 100 k R2 8.7 k D1 2.3 V + − Vref 0.5 V Fmax RFmax Figure 26. The OPAMP Arrangement Limits the VCO Modulation Signal between 0.5 and 2.3 V http://onsemi.com 13 NCP1397A, NCP1397B This techniques allows us to detect a fault on the converter in case the FB pin cannot rise above 0.3 V (to actually close the loop) in less than a duration imposed by the programmable timer. Please refer to the fault section for detailed operation of this mode. As shown on Figure 26, the internal dynamics of the VCO control voltage will be constrained between 0.5 V and 2.3 V, whereas the feedback loop will drive Pin 6 (FB) between 1.1 V and 5.3 V. If we take the default FB pin excursion numbers, 1.1 V = 50 kHz, 5.3 V = 500 kHz, then the VCO maximum slope will be: 500k * 50k + 107 kHz/V 4.2 Figures 27 and 28 portray the frequency evolution depending on the feedback pin voltage level in a different frequency clamp combination. Figure 28. Here a different minimum frequency was programmed as well as a maximum frequency excursion Please note that the previous small−signal VCO slope has now been reduced to 300k / 4.1 = 71 kHz / V on Mupper and Mlower outputs. This offers a mean to magnify the feedback excursion on systems where the load range does not generate a wide switching frequency excursion. Due to this option, we will see how it becomes possible to observe the feedback level and implement skip cycle at light loads. It is important to note that the frequency evolution does not have a real linear relationship with the feedback voltage. This is due to the deadtime presence which stays constant as the switching period changes. The selection of the three setting resistors (Fmax, Fmin and deadtime) requires the usage of the selection charts displayed below: Figure 27. Maximal Default Excursion, Rt = 34 kW on Pin 4 and RF(max) = 1.9 kW on Pin 2 550 450 Fmax (kHz) 350 250 150 50 1.9 Fmin = 200 kHz VCC = 15 V VFB = 6.5 V DT = 300 ns Fmax = 50 kHz 11.9 21.9 31.9 41.9 Figure 29. Maximum Switching Frequency Resistor Selection Depending on the Adopted Minimum Switching Frequency RFmax (kW) http://onsemi.com 14 NCP1397A, NCP1397B 500 450 400 Fmin (kHz) 350 300 250 200 150 100 2 4 6 8 10 12 RFmin (kW) 14 16 18 20 In1 In2 FB 20 k VCO VCC VCC = 15 V VFB = 1 V DT = 300 ns ORing capability and optocoupler connection configurations If for any particular reason, there is a need for a frequency variation linked to an event appearance (instead of abruptly stopping pulses), then the FB pin lends itself very well to the addition of other sweeping loops. Several diodes can easily be used perform the job in case of reaction to a fault event or to regulate on the output current (CC operation). Figure 33 shows how to do it. Figure 30. Minimum Switching Frequency Resistor Selection (Fmin = 100 kHz to 500 kHz) 100 90 80 Fmin (kHz) 70 60 50 40 30 20 20 30 40 50 60 70 RFmin (kW) 80 90 100 110 VCC = 15 V VFB = 1 V DT = 300 ns Figure 33. Thanks to the FB Configuration, Loop ORing is Easy to Implement Figure 31. Minimum Switching Frequency Resistor Selection (Fmin = 20 kHz to 100 kHz) 1900 1700 1500 1300 DT (ns) 1100 900 700 500 300 100 3.5 13.5 23.5 33.5 43.5 53.5 RDT (kW) 63.5 73.5 83.5 The VCO configuration used in this IC also offers an easy way to connect optocoupler (or pulldown bipolar) directly to the Rt pin instead of FB pin (refer to Figures 34 and 35). The optocoupler is then configured as “common emitter” and the operating frequency is controlled by the current that is taken out from the Rt pin – we have current controller oscillator (CCO). If one uses this configuration it is needed to maintain FB pin voltage between 0.3 V and 1 V otherwise the FB fault will be detected. The FB pin can be still used for open FB loop detection in some applications – to do so it is needed to keep optcoupler emitter voltage higher then 0.3 V for nominal load conditions. One needs to take RFB pulldown resistor into account when using this configuration. It is possible to implement skip mode using Skip/disable input and emitter resistors Rskip1 and Rskip2. Figure 32. Deadtime Resistor Selection http://onsemi.com 15 NCP1397A, NCP1397B Fstart(adj) − RFstart/RFmin Fmin(adj) − RFmin Fmax(adj) − Rc + Rskip1 + Rskip2 RFstart RFmin Rc SS Fmax Rt FB VCC GND Skip/Disable CSS OK1 Rskip1 NCP1397 Rskip2 Figure 34. Feedback Configuration Using Direct Connection to the Rt Pin Rbias Fstart(adj) − RFstart/RFmin Fmin(adj) − RFmin Fmax(adj) − Rc + Rskip1 + Rskip2 RFstart RFmin Rc SS Fmax Rt FB VCC GND Skip/Disable CSS OK1 Rskip1 NCP1397 Rskip2 1N4148 Figure 35. Feedback Configuration Using Direct Connection to the Rt Pin – No Open FB Loop Detection Dead−Time Control Deadtime control is an absolute necessity when the half−bridge configuration comes to play. The deadtime technique consists in inserting a period during which both high and low side switches are off. Of course, the deadtime amount differs depending on the switching frequency, hence the ability to adjust it on this controller. The option ranges between 100 ns and 2 ms. The deadtime is actually made by controlling the oscillator discharge current. Figure 36 portrays a simplified VCO circuit based on Figure 25. During the discharge time, the clock comparator is high and invalidates the AND gates: both outputs are low. When the comparator goes back to the low level, during the timing capacitor Ct recharge time, A and B outputs are validated. By connecting a resistor RDT to ground, it creates a current whose image serves to discharge the Ct capacitor: we control the dead−time. The typical range evolves between 100 ns (RDT = 3.5 kW) and 2 ms (RDT = 83.5 kW). Figure 39 shows the typical waveforms. http://onsemi.com 16 NCP1397A, NCP1397B VDD Icharge: FSW(min) + FSW(max) S + Idis Ct − D Clk R + 3 V−1 V Q Q Vref DT RDT A B Figure 36. Dead−time Generation Soft−Start Sequence In resonant controllers, a soft−start is needed to avoid suddenly applying the full current into the resonating circuit. With this controller the soft−start duration is fully adjustable using eternal components. The purpose of the Soft−Start pin is to discharge Soft−Start capacitor before IC restart and in case of fault conditions detected by Fault input. Once the controller starts operation, the Soft−Start capacitor (refer to Figure 37) is fully discharged and thus it starts charging from the Rt pin. The charging current increases operating frequency of the controller above Fmin. As the soft−start capacitor charges, the frequency smoothly decreases down to Fmin. Of course, practically, the feedback loop is supposed to take over the VCO lead as soon as the output voltage has reached the target. If not, then the minimum switching frequency is reached and a fault is detected on the feedback pin (typically below 300 mV). Figure 38 depicts a typical LLC startup using NCP1397A/B controller. SS Fmax Rt RFmin RFmax CSS Fstart(adj) − RFstart/RFmin Fmin(adj) − RFmin Fmax(adj) − RFmax GND NCP1397 SS Action Target is Reached Figure 38. A Typical Startup Sequence on a LLC Converter Using NCP1397 RF(start) Figure 37. Soft−Start Components Arrangement Please note that the soft−start capacitor is discharged in the following conditions: − A startup sequence − During auto−recovery burst mode − A brown−out recovery − A temperature shutdown recovery The skip/disable input undergoes a special treatment. Since we want to implement skip cycle using this input, we cannot activate the soft−start every time the feedback pin stops the operations in low power mode. Therefore, when the skip/enable pin is released, no soft−start occurs to offer the best skip cycle behavior. However, it is very possible to combine skip cycle and true disable, e.g. via ORing diodes driving Pin 8. In that case, if a signal maintains the skip/disable input high long enough to bring the feedback level down (below 0.3 V) since the output voltage starts to fall down, then the soft−start discharge switch is activated. http://onsemi.com 17 NCP1397A, NCP1397B 4.00 Plot1 Vct in Volts 3.00 2.00 1.00 0 Ct Voltage 16.0 Plot2 Clock in Volts 12.0 8.00 4.00 0 DT Clock Pulses DT 8.00 Plot3 Difference in Volts 4.00 0 −4.00 −8.00 A−B 56.2 m DT 65.9 m 75.7 m time in seconds 85.4 m 95.1 m Figure 39. Typical Oscillator Waveforms Brown−Out protection Vbulk Rupper IBO BO Rlower + VBO VDD ON/OFF The Brown−Out circuitry (BO) offers a way to protect the resonant converter from low DC input voltages. Below a given level, the controller blocks the output pulses, above it, it authorizes them. The internal circuitry, depicted by Figure 40, offers a way to observe the high−voltage (HV) rail. A resistive divider made of Rupper and Rlower, brings a portion of the HV rail on Pin 5. Below the turn−on level, the 28 mA current source IBO is off. Therefore, the turn−on level solely depends on the division ratio brought by the resistive divider. + − BO Figure 40. The Internal Brown−out Configuration with an Offset Current Source http://onsemi.com 18 NCP1397A, NCP1397B 450 16.0 351 V 350 Plot1 Vin in Volts 12.0 Vcmp in Volts Vin 250 V 250 8.0 150 4.0 50 0 20 m BO 60 m 100 m time in seconds 140 m 180 m Figure 41. Simulation Results for 350 / 250 ON / OFF Levels To the contrary, when the internal BO signal is high (Mlower and Mupper pulse), the IBO source is activated and creates a hysteresis. As a result, it becomes possible to select the turn−on and turn−off levels via a few lines of algebra: IBO is off V()) + V bulk1 R lower R lower ) R upper R lower R lower ) R upper R lower R upper R lower ) R upper (eq. 2) (eq. 1) R lowerer + VBO V bulk1 * V bulk2 IBO V bulk1 * VBO If we decide to turn−on our converter for Vbulk1 equals 350 V and turn it off for Vbulk2 equals 250 V, then we obtain: Rupper = 3.57 MW Rlower = 10.64 kW The bridge power dissipation is 4002 / 3.781 MW = 45 mW when front−end PFC stage delivers 400 V. Figure 41 simulation result confirms our calculations. Latchoff Protection IBO is on V()) + V bulk2 ) IBO We can now extract Rlower from Equation 1 and plug it into Equation 2, then solve for Rupper: R upper + R lower V bulk1 * VBO VBO There are some situations where the converter shall be fully turned−off and stay latched. This can happen in presence of an overvoltage (the feedback loop is drifting) or when an over temperature is detected. Thanks to the addition of a comparator on the BO pin, a simple external circuit can lift up this pin above Vlatch (4 V typical) and permanently disable pulses. The VCC needs to be cycled down below 6.5 V typically to reset the controller. http://onsemi.com 19 NCP1397A, NCP1397B VCC Vbulk + − 20 ms RC To permanent latch Q1 Vout Rupper + Vlatch IBO VDD BO NTC Rlower + VBO + − BO Figure 42. Adding a Comparator on the BO Pin Offers a way to Latch−off the Controller On Figure 42, Q1 is blocked and does not bother the BO measurement as long as the NTC and the optocoupler are not activated. As soon as the secondary optocoupler senses an OVP condition, or the NTC reacts to a high ambient temperature, Q1 base is brought to ground and the BO pin goes up, permanently latching off the controller. Protection Circuitry This resonant controller offers a dedicated input (Fault input) to detect primary overcurrent conditions and protect power stage from damage. Once the voltage on the Fault input exceeds 1.04 V threshold the external timer capacitor starts charging by Itimer1 current. Simultaneously the Soft−Start discharge switch is activated to shift operating frequency up to keep primary current at acceptable level. In case the overload disappears fast enough the Soft−Start discharge switch is open, Itimer1 current turned−off and timer capacitor discharges via an external parallel resistor. In case the overload lasts for more than timer duration (given by Itimer, Vtimer, Ctimer and Rtimer) the IC stops the operation and waits until the Ctimer will discharge to 1 V. The application then restarts via Soft−Start. In case of heavy overload, like transformer short circuit, the primary current grows very fast and thus could reach danger level prior the fault timer elapses. The NCP1397B therefore features additional comparator (1.55 V) on the Fault input to permanently latch the application and protect against destruction. Figure 44 depicts the architecture of the fault circuitry for NCP1397B controller. The NCP1397A features second fault comparator as well but in this case it doesn’t latches off the IC but speeds up the Fault timer capacitor charging by turning on additional current source Itimer2 – refer to Figure 43. The NCP1397A can thus be used in applications that have to recover automatically from any fault conditions. http://onsemi.com 20 NCP1397A, NCP1397B VDD VDD Itimer2 Itimer1 Ctimer UVLO Ctimer discharge at VCC(on)/ restart if VFB < 0.3 V SS(dis) Css Reset + +Vref(fault) + Rtimer Fault Average Input Current To Primary Current Sensing Circuitry + VtimerON VtimerOFF 1 = ok 0 = fault + Vref(skip) + + Vref(OCP) + VCC FB FB 1 = ok 0 = fault Skip/Disable Reset DRIVING LOGIC SS Skip A B A B Figure 43. Fault Input Logic for NCP1397A http://onsemi.com 21 NCP1397A, NCP1397B discharge at VCC(on)/ restart if VFB < 0.3 V VDD SS(dis) Css Itimer1 Ctimer UVLO Reset + +Vref(fault) to latch VtimerON VtimerOFF 1 = ok 0 = fault + + Vref(skip) FB + Rtimer Fault Ctimer Average Input Current To Primary Current Sensing Circuitry + + + Vref(OCP) VCC FB 1 = ok 0 = fault Skip/Disable Reset DRIVING LOGIC SS Skip A B A B Figure 44. Fault Input Logic for NCP1397B On Figures 43 and 44 examples, a voltage proportional to primary current, once averaged, gives an image of the input power in case Vin is kept constant via a PFC circuit. If the output loading increases above a certain level, the voltage on this pin will pass the 1 V threshold and start the timer. If the overload stays there, after a few tens of milli −seconds, switching pulses will disappear and a protective auto−recovery cycle will take place. Adjusting the resistor R in parallel with the timer capacitor will give the flexibility to adjust the fault burst mode (refer to Figure 45). http://onsemi.com 22 NCP1397A, NCP1397B SMPS Stops 4V Fault is Gone SMPS Re−starts 1V Reset at Re−start Figure 45. A Resistor Can Easily Program the Capacitor Discharge Time VCC FB Skip/Disable lose regulation in light load conditions, forcing the FB level to increase. When it reaches the programmed level, it triggers the skip input and stops pulses. Then Vout slowly drops, the loop reacts by decreasing the feedback level which, in turn, unlocks the pulses, Vout goes up again and so on: we are in skip cycle mode. As the feedback voltage does not drop below 0.3 V the Soft−Start discharge switch is not activated in this case. Please refer also to Figure 35 for skip mode function implementation when optocoupler is connected directly to Rt pin. Startup Behavior Figure 46. Skip Cycle Can Be Implemented Via Two Resistors on the FB Pin to the Fast Fault Input Skip/Disable The Skip/Disable input is not affected by a delayed action. As soon as its voltage exceeds 0.66 V typical, all pulses are off and maintained off as long as the fault is present. When the pin is released, pulses come back and the soft−start is activated (in case the VFB < 0.3 V). Thanks to the low activation level, this pin can observe the feedback pin via a resistive divided and thus implement skip cycle operation. The resonant converter can be designed to When the VCC voltage increases, the internal current consumption is kept below Istrup. When VCC reaches the VCC(on) level, output Mlower goes high first and then output Mupper. This sequence will always be the same whatever triggers the pulse delivery: fault, OFF to ON etc… Pulsing the output Mlower high first gives an immediate charge of the bootstrap capacitor. Then, the rest of pulses follow, delivered at the highest switching value, set by the RFstart resistor in parallel with RFmin resistor on Pin 4. The soft−start capacitor ensures a smooth frequency decrease to either the programmed minimum value (in case of fault) or to a value corresponding to the operating point if the feedback loop closes first. Figure 47 shows typical signals evolution at power on. http://onsemi.com 23 NCP1397A, NCP1397B Figure 47. At Power On, Output A is First Activated and the Frequency Slowly Decreases Based on the Soft−Start Capacitor Voltage Figure 47 depicts an auto−recovery situation, where the timer has triggered the end of output pulses. In that case, the VCC level was given by an auxiliary power supply, hence its stability during the hiccup. A similar situation can arise if the user selects a more traditional startup method, with an auxiliary winding. In that case, the VCC(min) comparator stops the output pulses whenever it is activated, that is to say, when VCC falls below 9.5 V typical. At this time, the VCC pin still receives its bias current from the startup resistor and increases toward VCC(on). When the voltage reaches VCC(on), a standard sequence takes place, involving a soft−start. Figure 48 portrays this behavior. http://onsemi.com 24 NCP1397A, NCP1397B Figure 48. When the VCC is to Low, All Pulses are Stopped Until VCC Goes Back to the Startup Voltage The High−Voltage Driver The driver features a traditional bootstrap circuitry, requiring an external high−voltage diode for the capacitor refueling path. Figure 49 shows the internal architecture of the high−voltage section. HV B Pulse Trigger Level Shifter Vboot S Q Q R HB Cboot Mupper UVLO VCC Fault A Delay Dboot aux VCC Mlower + GND Figure 49. The Internal High−voltage Section of the NCP1397 http://onsemi.com 25 NCP1397A, NCP1397B The device incorporates an upper UVLO circuitry that makes sure enough Vgs is available for the upper side MOSFET. The B and A outputs are delivered by the internal logic, as Figure 43 testifies. A delay is inserted in the lower rail to ensure good matching between these propagating signals. As stated in the maximum rating section, the floating portion can go up to 600 VDC and makes the IC perfectly suitable for offline applications featuring a 400 V PFC front−end stage. ORDERING INFORMATION Device NCP1397ADR2G NCP1397DR2G Package SOIC−16, Less Pin 13 (Pb−Free) SOIC−16, Less Pin 13 (Pb−Free) Shipping† 2500 / Tape & Reel 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. http://onsemi.com 26 NCP1397A, NCP1397B PACKAGE DIMENSIONS SOIC−16 NB, LESS PIN 13 CASE 751AM−01 ISSUE O D 16 9 AB H E C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. DIM A A1 b C D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ 0.25 M B M 1 15X e 8 b 15X L M 0.25 A1 TA S B S C SEATING PLANE h x 45 _ A M SOLDERING FOOTPRINT* 6.40 15X 1.12 16 1 15X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The product described herein (NCP1397A/B), is covered by U.S. patent: 6,097, 075; 7176723; 6,362, 067. There may be some other patent pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 27 NCP1397/D