NCP1397GANGEVB

NCP1397A/B, NCV1397A/B High Performance Resonant Mode Controller with Integrated High-Voltage Drivers www.onsemi.com The NCP1397 is a high performance controller that can be utilized in half bridge resonant topologies such as series resonant, parallel resonant and LLC resonant converters. It integrates 600 V gate drivers, simplifying layout and reducing external component count. With its unique architecture, including a 500 kHz Voltage Controlled Oscillator whose control mode permits flexibility when an ORing function is required, the NCP1397 delivers everything needed to build a reliable and rugged resonant mode power supply. The NCP1397 provides a suite of protection features with configurable settings to optimize any application. These include: auto−recovery or fault latch−off, brown−out, open optocoupler, soft−start and short−circuit protection. Deadtime is also adjustable to overcome shoot through current. 16 1 SO−16, LESS PIN 13 D SUFFIX CASE 751AM MARKING DIAGRAMS 16 NCx1397yG AWLYWW Features • • • • • • • • • • • • • • • • • • 1 High−Frequency Operation from 50 kHz up to 500 kHz 600 V High−Voltage Floating Driver Adjustable Minimum Switching Frequency with ±3% Accuracy Adjustable Deadtime from 100 ns to 2 ms. Startup Sequence Via an Externally Adjustable Soft−Start Brown−Out Protection for a Simpler PFC Association Latched Input for Severe Fault Conditions, e.g. Over Temperature or OVP Timer−Based Input with Auto−Recovery Operation for Delayed Event Reaction Latched Overcurrent Protection Disable Input for Immediate Event Reaction or Simple ON/OFF Control VCC Operation up to 20 V Low Startup Current of 300 mA 1 A/0.5 A Peak Current Sink/Source Drive Capability Common Collector Optocoupler Connection for Easier ORing Optional Common Emitter Optocoupler Connection Internal Temperature Shutdown NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications • Flat Panel Display Power Converters • High Power ac−dc Adapters for Notebooks • Computing Power Supplies © Semiconductor Components Industries, LLC, 2015 October, 2015 − Rev. 6 x y A WL Y WW G = P (standard) or V (automotive) = A or B = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS 16 Vboot CSS(dis) 1 15 Mupper Fmax 2 Ctimer 3 14 HB Rt 4 BO 5 12 VCC FB 6 11 Mlower DT 7 10 GND Skip/Disable 8 9 Fault (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 26 of this data sheet. • Industrial and Medical Power Sources • Offline Battery Chargers 1 Publication Order Number: NCP1397/D NCP1397A/B, NCV1397A/B R18 Figure 1. Typical Application Example PIN FUNCTION DESCRIPTION Pin # Pin Name Function Pin Description 1 CSS(dis) Soft−Start Discharge 2 Fmax Maximum frequency clamp 3 Ctimer Timer duration 4 Rt Minimum frequency clamp Connecting a resistor to this pin, sets the minimum oscillator frequency reached for VFB = 1 V. 5 BO Brown−Out Detects low input voltage conditions. When brought above Vlatch (4 V typically), it fully latches off the controller. 6 FB Feedback Injecting current into this pin increases the oscillation frequency up to Fmax. A simple resistor adjusts the dead−time width Soft−start capacitor discharge pin. Connect to the soft−start capacitor to reset it before startup or during overload conditions. A resistor sets the maximum frequency excursion Sets the timer duration in presence of a fault 7 DT Deadtime 8 Skip/Disable Skip or Disable input Upon release, a clean startup sequence occurs if VFB < 0.3 V. During the skip mode, when FB doesn’t drop below 0.3 V, the IC restarts without soft−start sequence. 9 Fault Fault detection input When asserted, the external timer starts to countdown and shuts down the controller at the end of its time duration. Simultaneously the Soft−Start discharge switch is activated so the converter operating frequency goes up to protect application power stage. This input features also second fault comparator with higher threshold (1.5 V typically) that: A) Speeds up the timer capacitor charging current 8 times – NCP1397A B) latches off the IC permanently – NCP1397B In both versions the second fault comparator helps to protect application in case of short circuit on the output or transformer secondary winding. 10 GND Analog ground 11 Mlower Low side output − 12 VCC Supplies the controller The controller accepts up to 20 V 13 NC Not connected Increases the creepage distance 14 HB Half−bridge connection 15 Mupper High side output 16 Vboot Bootstrap pin Drives the lower side MOSFET Connects to the half−bridge output Drives the higher side MOSFET The floating VCC supply for the upper stage www.onsemi.com 2 NCP1397A/B, NCV1397A/B VDD Temperature Shutdown S Imin VFB  VFB(o ) VBOOT D + Vref Q Clk Rt R + VCC Management IDT C Vref Q −− 50% DC DT Adj. I = Imax for Vfb = 5.3 V I = 0 for Vfb < Vfb(min) FF Mupper BO Reset VDD PON Reset Imax VFB = 5 Vdd VDD Fast Fault Timeout Fault Vref Itimer1 UVLO Fault HB Itimer2 Fmax Timer Level Shifter + −− NC Timeout Fault + Vref PON Reset Vtimer OFF Reset VCC PON Reset Fault Fault SS(dis) Enable (if Vfb 0 only VDD V=V (FB) −− VFB(min) + −− + VFB(fault) GND + VFB(min) Skip/ Disable −− Vref Deadtime Adjustment IDT DT 20 ns Noise Filter + Vref Skip/Disable + VDD 20 ms Noise Filter IBO Q BO + −− + VBO Fault Q + −− + Vlatch S R 20 ms Noise Filter + −− + Vref(fault) + −− Vref(OCP) + 1 ms Noise Filter Figure 2. Internal Circuit Architecture (NCP1397A) www.onsemi.com 3 PON Reset NCP1397A/B, NCV1397A/B VDD Temperature Shutdown S Imin VFB  VFB(o ) VBOOT Q D Vref + Clk Vref Q −− Rt R + IDT VCC Management C 50% DC DT Adj. I = Imax for Vfb = 5.3 V I = 0 for Vfb < Vfb_min VDD FF Mupper BO Reset PON Reset Imax Vfb = 5 UVLO Fault VDD Fast Fault Timeout Fault Vref HB Itimer1 Fmax If FAULT Itimer else 0 Level Shifter + −− Timer NC Timeout Fault + Vref PON Reset Vtimer OFF Reset VCC PON Reset Fault Fault SS(dis) Enable (if Vfb 0 only VDD V=V (FB) −− VFB(min) −− RFB + −− + VFB(fault) GND + VFB(min) Skip/ Disable 20 ns Noise Filter −− + Vref Deadtime Adjustment IDT DT Vref Skip + VDD 20 ms Noise Filter IBO Q BO + + −− + VBO −− + Vlatch Fault S 20 ms Noise Filter Q R + −− + Vref(fault) + −− Vref(OCP) + 1 ms Noise Filter Figure 3. Internal Circuit Architecture (NCP1397B) www.onsemi.com 4 PON Reset NCP1397A/B, NCV1397A/B MAXIMUM RATINGS Rating Symbol Value Unit VBRIDGE −1 to 600 V VBOOT − VBRIDGE 0 to 20 V High side output voltage VDRV(HI) VBRIDGE−0.3 to VBOOT+0.3 V Low side output voltage VDRV(LO) −0.3 to VCC+0.3 V dVBRIDGE/dt 50 V/ns VCC 20 V − −0.3 to 10 V RqJA 130 °C/W Storage Temperature Range − −60 to +150 °C ESD Capability, Human Body Model (HBM) (All pins except HV pins) − 2 kV ESD Capability, Machine Model (MM) − 200 V High Voltage bridge pin, pin 14 Floating supply voltage, ground referenced Allowable output slew rate Power Supply voltage, pin 12 Maximum voltage, all pins (except pin 11 and 10) Thermal Resistance Junction−to−Air, SOIC version Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device(s) contains ESD protection and exceeds the following tests: Human Body Model 2000 V per JEDEC Standard JESD22−A114E Machine Model 200 V per JEDEC Standard JESD22−A115−A 2. This device meets latchup tests defined by JEDEC Standard JESD78. www.onsemi.com 5 NCP1397A/B, NCV1397A/B ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit SUPPLY SECTION VCC(on) Turn−on threshold level, VCC going up 12 9.7 10.5 11.3 V VCC(min) Minimum operating voltage after turn−on 12 8.7 9.5 10.3 V Vboot(on) Startup voltage on the floating section 16−14 8 9 10 V Vboot(min) Cutoff voltage on the floating section 16−14 7.4 8.4 9.4 V Startup current, VCC < VCC(on) 12 − − 300 mA VCC level at which the internal logic gets reset 12 − 6.6 − V ICC1 Internal IC consumption, no output load on pin 15/14 – 11/10, FSW = 300 kHz 12 − 4 − mA ICC2 Internal IC consumption, 1 nF output load on pin 15/14 – 11/10, FSW = 300 kHz 12 − 11 − mA ICC3 Consumption in fault or disable mode (All drivers disabled, Rt = 34 kW, RDT = 10 kW) 12 − 1.5 − mA Istartup VCC(reset) VOLTAGE CONTROL OSCILLATOR (VCO) FSW(min) Minimum switching frequency, Rt = 34 kW on pin 4, Vpin6 = 0.8 V, DT = 300 ns 4 58.2 60 61.8 kHz FSW(max) Maximum switching frequency, Rf(max) = 1.9 kW on pin 2, Vpin6 > 5.3 V, Rt = 34 kW, DT = 300 ns 2 440 500 560 kHz Feedback pin swing above which Df = 0 6 − 5.3 − V 11−15 48 50 52 % − 700 − ns FBSW DC Operating duty−cycle symmetry Tdel1 Delay before driver restart from fault or disable mode − Tdel2 Delay before driver restart after VCC(on) event (Note 4) − − 11 − ms Reference voltage for Rt pin 4 2.18 2.3 2.42 V Internal pulldown resistor 6 − 20 − kW VFB(min) Voltage on pin 6 below which the FB level has no VCO action 6 − 1.1 − V VFB(off) Voltage on pin 6 below which the controller considers the FB fault 6 240 280 320 mV Feedback fault comparator hysteresis 6 − 45 − mV Vref(Rt) FEEDBACK SECTION RFB VFBoff(hyste) DRIVE OUTPUT Tr Output voltage risetime @ CL = 1 nF, 10−90% of output signal 15−14/11−10 − 40 − ns Tf Output voltage falltime @ CL = 1 nF, 10−90% of output signal 15−14/11−10 − 20 − ns ROH Source resistance 15−14/11−10 − 13 − W ROL Sink resistance 15−14/11−10 − 5.5 − W Deadtime with RDT = 10 kW from pin 7 to GND 7 250 290 340 ns Tdead(max) Tdead Maximum deadtime with RDT = 82 kW from pin 7 to GND 7 − 2 − ms Tdead(min) Minimum deadtime, RDT = 3 kW from pin 7 to GND 7 − 100 − ns IHV(LEAK) Leakage current on high voltage pins to GND 14, 15,16 − − 5 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. The IC does not activate soft−start (unless the feedback pin voltage is below 0.3 V) when the skip/disable input is released, this is for skip cycle implementation. 4. Guaranteed by design. www.onsemi.com 6 NCP1397A/B, NCV1397A/B ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V unless otherwise noted) Symbol Rating Pin Min Typ Max Unit TIMERS Itimer1 Timer capacitor charge current during feedback fault or when Vref(fault) < Vpin9 < Vref(OCP) 3 150 175 190 mA Itimer2 Timer capacitor charge current when Vpin9 > Vref(OCP) (Icharge1 + Icharge2) – A version only 3 1.1 1.3 1.5 mA Ttimer Timer duration with a 1 mF capacitor and a 1 MW resistor, Itimer1 current applied 3 − 24 − ms TtimerR Timer recurrence in permanent fault, same values as above 3 − 1.4 − s Vtimer(on) Voltage at which pin 3 stops output pulses 3 3.8 4 4.2 V Vtimer(off) Voltage at which pin 3 restarts output pulses 3 0.95 1 1.05 V RSS(dis) Soft−start discharge switch channel resistance 1 − 100 − W Reference voltage for Skip/Disable input (Note 4) 8 630 660 690 mV Hysteresis for Skip/Disable (Note 4) 8 − 45 − mV Reference voltage for Fault comparator 9 0.99 1.04 1.09 V Hysteresis for fault comparator input 9 − 60 − mV Reference voltage for OCP comparator 9 1.47 1.55 1.63 V Hyste(OCP) Hysteresis for OCP comparator input 9 − 90 − mV Tp(Disable) Propagation delay from disable input to the drive shutdown 8 − 60 100 ns IBO(bias) PROTECTION Vref(Skip) Hyste(Skip) Vref(Fault) Hyste(Fault) Vref(OCP) Brown−Out input bias current 5 − 0.02 − mA VBO Brown−Out level 5 0.99 1.04 1.09 V IBO Hysteresis current, Vpin5 > VBO 5 25 28 31 mA Latching voltage 5 3.7 4 4.3 V Temperature shutdown − 140 − − °C Hysteresis − − 30 − °C Vlatch TSD TSD(hyste) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. The IC does not activate soft−start (unless the feedback pin voltage is below 0.3 V) when the skip/disable input is released, this is for skip cycle implementation. 4. Guaranteed by design. www.onsemi.com 7 NCP1397A/B, NCV1397A/B TYPICAL CHARACTERISTICS 10.55 9.52 9.50 9.48 VCC(min) (V) VCC(on) (V) 10.50 10.45 9.46 9.44 9.42 10.40 9.40 10.35 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 9.38 −40 −25 −10 5 110 125 95 110 125 Figure 5. VCC(min) Threshold 60.05 510 60 509 508 59.95 FSW(max) (kHz) FSW(min) (kHz) Figure 4. VCC(on) Threshold 20 35 50 65 80 TEMPERATURE (°C) 59.9 59.85 59.8 507 506 505 504 59.75 −40 −20 0 20 40 60 TEMPERATURE (°C) 80 100 120 503 −40 −25 −10 5 Figure 6. FSW(min) Frequency Clamp 20 35 50 65 80 TEMPERATURE (°C) 95 110 125 Figure 7. FSW(max) Frequency Clamp 0.661 23.0 22.5 0.660 22.0 0.659 Vref(skip) (V) RFB (kW) 21.5 21.0 20.5 20.0 0.658 0.657 19.5 0.656 19.0 18.5 −40 −25 −10 5 20 35 50 65 80 95 110 125 0.655 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 8. Pulldown Resistor (RFB) Figure 9. Skip/Disable Threshold (Vref(skip)) www.onsemi.com 8 NCP1397A/B, NCV1397A/B TYPICAL CHARACTERISTICS 17.0 9.0 16.0 8.5 15.0 8.0 7.5 ROLA (W) ROHA (W) 14.0 13.0 12.0 11.0 7.0 6.5 6.0 5.5 10.0 5.0 9.0 4.5 8.0 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 4.0 −40 −25 −10 5 110 125 114 297 113 296 112 295 111 294 110 109 108 107 110 125 293 292 291 290 289 106 288 105 287 104 95 Figure 11. Sink Resistance (ROL) Tdead(nom) (ns) Tdead(min) (ns) Figure 10. Source Resistance (ROH) 20 35 50 65 80 TEMPERATURE (°C) −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 286 −40 −25 −10 5 110 125 95 110 125 95 110 125 Figure 13. Tdead(nom) Figure 12. Tdead(min) 4.035 2.060 4.030 2.055 4.025 Vlatch (V) Tdead(max) (ms) 2.065 4.020 2.050 2.045 4.015 2.040 4.010 2.035 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 20 35 50 65 80 95 110 125 4.005 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) TEMPERATURE (°C) Figure 14. Tdead(max) Figure 15. Latch Level (Vlatch) www.onsemi.com 9 NCP1397A/B, NCV1397A/B 1.038 28.8 1.036 28.6 1.034 28.4 28.2 1.032 IBO (mA) VBO (V) TYPICAL CHARACTERISTICS 1.030 1.028 28.0 27.8 27.6 1.026 27.4 1.024 27.2 1.022 −40 −25 −10 5 20 35 50 65 80 95 27.0 −40 −25 −10 5 110 125 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. Brown−Out Reference (VBO) Figure 17. Brown−Out Hysteresis Current (IBO) 1.050 178 1.048 176 1.046 174 Itimer1 (mA) Vref(fault) (V) 1.044 1.042 1.040 172 170 1.038 1.036 168 1.034 1.032 −40 −25 −10 5 20 35 50 65 80 95 166 −40 −25 −10 5 110 125 20 35 50 65 80 95 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. Fault Input Reference (Vref(fault)) Figure 19. Ctimer 1st Current (Itimer1) 1.565 110 125 1.34 1.33 1.560 1.32 Itimer2 (mA) Vref(OCP) (V) 1.555 1.550 1.545 1.31 1.30 1.29 1.28 1.540 1.27 1.535 1.26 1.530 −40 −25 −10 5 20 35 50 65 80 95 110 125 1.25 −40 −25 −10 5 20 35 50 65 80 95 TEMPERATURE (°C) TEMPERATURE (°C) Figure 20. OCP reference (Vref(OCP)) Figure 21. Ctimer 2nd Current (Itimer2) www.onsemi.com 10 110 125 NCP1397A/B, NCV1397A/B 4.035 0.288 4.030 0.286 0.284 VFB(off) (V) 4.025 4.020 4.015 0.282 0.280 0.278 4.010 0.276 4.005 −40 −25 −10 5 20 35 50 65 80 95 110 125 0.274 −40 −25 −10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) Figure 22. Fault Timer Ending Voltage (Vtimer(on)) Figure 23. FB Fault Detection Threshold (VFB(fault)) 1.000 0.999 0.998 Vtimer(off) (V) Vtimer(on) (V) TYPICAL CHARACTERISTICS 0.997 0.996 0.995 0.994 0.993 0.992 −40 −25 −10 5 20 35 50 65 80 TEMPERATURE (°C) 95 110 125 Figure 24. Fault Timer Reset Voltage (Vtimer(off)) www.onsemi.com 11 NCP1397A/B, NCV1397A/B APPLICATION INFORMATION The NCP1397A/B includes all necessary features to help building a rugged and safe switch−mode power supply featuring an extremely low standby power. The below bullets detail the benefits brought by implementing the NCP1397A/B controller: • Wide frequency range: A high−speed Voltage Control Oscillator allows an output frequency excursion from 50 kHz up to 500 kHz on Mlower and Mupper outputs. • Adjustable dead−time: Due to a single resistor wired to ground, the user has the ability to include some dead−time, helping to fight cross−conduction between the upper and the lower transistor. • Adjustable soft−start: Every time the controller starts to operate (power on), the switching frequency is pushed to the programmed starting value by external components (RFmin//RFstart) and slowly moves down toward the minimum frequency, until the feedback loop closes. The soft−start discharge input (SS(dis)) discharges the Soft−Start capacitor before any IC restart excluding the restart after Disable is released AND FB voltage is higher than 0.3 V. The Soft−Start discharge switch also activates in case the Fault input detects the overload conditions. • Adjustable minimum and maximum frequency excursion: In resonant applications, it is important to stay away from the resonating peak to keep operating the converter in the right region. Thanks to a single external resistor, the designer can program its lowest frequency point, obtained in lack of feedback voltage (during the startup sequence or in short−circuit conditions). Internally trimmed capacitors offer a $3% precision on the selection of the minimum switching frequency. The adjustable upper stop being less precise to $12%. • Low startup current: When directly powered from the high−voltage DC rail, the device only requires 300 mA to startup. • Brown−Out detection: To avoid operation from a low input voltage, it is interesting to prevent the controller from switching if the high−voltage rail is not within the right boundaries. Also, when teamed with a PFC front−end circuitry, the brown−out detection can ensure a clean startup sequence with soft−start, ensuring that the PFC is stabilized before energizing the resonant tank. The BO input features a 28 mA hysteresis current for the lowest consumption. • Adjustable fault timer duration: When a fault is detected on the Fault input or when the FB path is broken, timer pin starts to charge an external capacitor. If the fault is removed, the timer opens the charging path and nothing happens. When the timer reaches its selected duration (via a capacitor on Pin 3), all pulses are stopped. The controller now waits for the discharge via an external resistor on Pin 3 to issue a new clean startup sequence via soft−start. • Cumulative fault events: In the NCP1397A/B, the timer capacitor is not reset when the fault disappears. It actually integrates the information and cumulates the occurrences. A resistor placed in parallel with the capacitor will offer a simple way to adjust the discharge rate and thus the auto−recovery retry rate. • Overcurrent detection using Fault input: The fault input is specifically designed to protect LLC application in case of short circuit or overload. In case the voltage on this input grows above first threshold the Itimer current source is activated and Fault timer capacitor starts charging. Simultaneously the Soft−Start discharge switch is activated to increase operating frequency of the converter. The IC stops operation in case the Fault timer elapses. The Fault input includes also second fault comparator that: − Speeds up the fault timer capacitor charging by increasing the Itimer1 current to Itimer2 – NCP1397A − Latches off the device – NCP1397B The second fault comparator thus helps to protect the power stage in case of hard short circuit (like shorted transformer winding etc.) • Skip cycle possibility: The absence of the soft−start on the Skip/Disable input (in case the VFB > 0.3 V) offers an easy way to implement skip cycle when power saving features are necessary. A simple resistive divider from the feedback pin to the Skip/Disable input, and skip can be implemented. • Broken feedback loop detection: Upon startup or any time during operation, if the FB signal is missing, the timer starts to charge timer capacitor. If the loop is really broken, the FB level does not grow−up before the timer ends charging. The controller then stops all pulses and waits until the timer pin voltage collapses to 1 V typically before a new attempt to restart, via the soft−start. If the optocoupler is permanently broken, a hiccup takes place. • Common collector or common emitter optocoupler connection options: This IC allows the designer to select from two possible optocoupler configurations. Voltage−Controlled Oscillator The VCO section features a high−speed circuitry allowing operation from 100 kHz up to 1 MHz. However, as a division by two internally creates the two Q and /Q outputs, the final effective signal on output Mlower and Mupper switches between 50 kHz and 500 kHz. The VCO is configured in such a way that if the feedback pin voltage goes up, the switching frequency also goes up. Figure 25 shows the architecture of the VCO oscillator. www.onsemi.com 12 NCP1397A/B, NCV1397A/B FBinternal VDD max FSW + - max Imin 0 to IFmax Vref + - Rt Rt sets Fmin for V(FB) = 0 S D Cint Q Clk Q R + VDD IDT Vref Imin A B DT RDT sets the deadtime VCC VDD Fmax Fmax sets the maximum FSW FB + RFB 20 k VFB < VFB(off) Start fault timer Vb(off) + Figure 25. The Simplified VCO Architecture VCC The designer needs to program the maximum switching frequency and the minimum switching frequency. In LLC configurations, for circuits working above the resonant frequency, a high precision is required on the minimum frequency, hence the $3% specification. This minimum switching frequency is actually reached when no feedback closes the loop. It can happen during the startup sequence, a strong output transient loading or in a short−circuit condition. By installing a resistor from Pin 4 to GND, the minimum frequency is set. Using the same philosophy, wiring a resistor from Pin 2 to GND will set the maximum frequency excursion. To improve the circuit protection features, we have purposely created a dead zone, where the feedback loop has no action. This is typically below 1.1 V. Figure 26 details the arrangement where the internal voltage (that drives the VCO) varies between 0 and 2.3 V. However, to create this swing, the feedback pin (to which the optocoupler emitter connects), will need to swing typically between 1.1 V and 5.3 V. FB + − R1 11.3 k + R3 100 k R2 8.7 k D1 2.3 V Vref 0.5 V Fmax RFmax Figure 26. The OPAMP Arrangement Limits the VCO Modulation Signal between 0.5 and 2.3 V www.onsemi.com 13 NCP1397A/B, NCV1397A/B This techniques allows us to detect a fault on the converter in case the FB pin cannot rise above 0.3 V (to actually close the loop) in less than a duration imposed by the programmable timer. Please refer to the fault section for detailed operation of this mode. As shown on Figure 26, the internal dynamics of the VCO control voltage will be constrained between 0.5 V and 2.3 V, whereas the feedback loop will drive Pin 6 (FB) between 1.1 V and 5.3 V. If we take the default FB pin excursion numbers, 1.1 V = 50 kHz, 5.3 V = 500 kHz, then the VCO maximum slope will be: 500 k * 50 k 4.2 + 107 kHz/V Figures 27 and 28 portray the frequency evolution depending on the feedback pin voltage level in a different frequency clamp combination. Figure 28. Here a Different Minimum Frequency was Programmed as well as a Maximum Frequency Excursion Please note that the previous small−signal VCO slope has now been reduced to 300k / 4.1 = 71 kHz / V on Mupper and Mlower outputs. This offers a mean to magnify the feedback excursion on systems where the load range does not generate a wide switching frequency excursion. Due to this option, we will see how it becomes possible to observe the feedback level and implement skip cycle at light loads. It is important to note that the frequency evolution does not have a real linear relationship with the feedback voltage. This is due to the deadtime presence which stays constant as the switching period changes. The selection of the three setting resistors (Fmax, Fmin and deadtime) requires the usage of the selection charts displayed below: Figure 27. Maximal Default Excursion, Rt = 41 kW on Pin 4 and RF(max) = 1.9 kW on Pin 2 www.onsemi.com 14 NCP1397A/B, NCV1397A/B 1900 VCC = 15 V VFB = 6.5 V DT = 300 ns 550 1700 1500 1300 DT (ns) Fmax (kHz) 450 350 Fmin = 200 kHz 250 1100 900 700 500 150 Fmin = 50 kHz 50 1.9 11.9 21.9 31.9 300 100 3.5 41.9 13.5 RFmax (kW) Figure 29. Maximum Switching Frequency Resistor Selection Depending on the Adopted Minimum Switching Frequency 23.5 33.5 43.5 53.5 RDT (kW) 63.5 73.5 83.5 Figure 32. Deadtime Resistor Selection ORing capability and optocoupler connection configurations 500 If for any particular reason, there is a need for a frequency variation linked to an event appearance (instead of abruptly stopping pulses), then the FB pin lends itself very well to the addition of other sweeping loops. Several diodes can easily be used perform the job in case of reaction to a fault event or to regulate on the output current (CC operation). Figure 33 shows how to do it. VCC = 15 V VFB = 1 V DT = 300 ns 450 Fmin (kHz) 400 350 300 250 VCC 200 150 100 2 4 6 8 10 12 RFmin (kW) 14 16 18 20 In1 In2 Figure 30. Minimum Switching Frequency Resistor Selection (Fmin = 100 kHz to 500 kHz) 100 Fmin (kHz) 80 60 50 40 30 20 30 40 50 60 70 RFmin (kW) 80 90 20 k The VCO configuration used in this IC also offers an easy way to connect optocoupler (or pulldown bipolar) directly to the Rt pin instead of FB pin (refer to Figures 34 and 35). The optocoupler is then configured as “common emitter” and the operating frequency is controlled by the current that is taken out from the Rt pin – we have current controller oscillator (CCO). If one uses this configuration it is needed to maintain FB pin voltage between 0.3 V and 1 V otherwise the FB fault will be detected. The FB pin can be still used for open FB loop detection in some applications – to do so it is needed to keep optcoupler emitter voltage higher then 0.3 V for nominal load conditions. One needs to take RFB pulldown resistor into account when using this configuration. It is possible to implement skip mode using Skip/disable input and emitter resistors Rskip1 and Rskip2. 70 20 VCO Figure 33. Thanks to the FB Configuration, Loop ORing is Easy to Implement VCC = 15 V VFB = 1 V DT = 300 ns 90 FB 100 110 Figure 31. Minimum Switching Frequency Resistor Selection (Fmin = 20 kHz to 100 kHz) www.onsemi.com 15 NCP1397A/B, NCV1397A/B Fstart(adj) − RFstart/RFmin Fmin(adj) − RFmin Fmax(adj) − Rc + Rskip1 + Rskip2 SS Fmax RFstart Rt Rc RFmin VCC FB GND Skip/Disable NCP1397 CSS OK1 Rskip1 Rskip2 Figure 34. Feedback Configuration Using Direct Connection to the Rt Pin Rbias Fstart(adj) − RFstart/RFmin Fmin(adj) − RFmin Fmax(adj) − Rc + Rskip1 + Rskip2 SS Fmax RFstart Rt Rc RFmin FB VCC GND Skip/Disable NCP1397 CSS OK1 Rskip1 Rskip2 1N4148 Figure 35. Feedback Configuration Using Direct Connection to the Rt Pin – No Open FB Loop Detection Dead−Time Control Deadtime control is an absolute necessity when the half−bridge configuration comes to play. The deadtime technique consists in inserting a period during which both high and low side switches are off. Of course, the deadtime amount differs depending on the switching frequency, hence the ability to adjust it on this controller. The option ranges between 100 ns and 2 ms. The deadtime is actually made by controlling the oscillator discharge current. Figure 36 portrays a simplified VCO circuit based on Figure 25. During the discharge time, the clock comparator is high and invalidates the AND gates: both outputs are low. When the comparator goes back to the low level, during the timing capacitor Ct recharge time, A and B outputs are validated. By connecting a resistor RDT to ground, it creates a current whose image serves to discharge the Ct capacitor: we control the dead−time. The typical range evolves between 100 ns (RDT = 3.5 kW) and 2 ms (RDT = 83.5 kW). Figure 39 shows the typical waveforms. www.onsemi.com 16 NCP1397A/B, NCV1397A/B VDD Icharge: FSW(min) + FSW(max) S D + Q Clk − Idis Q R Ct + 3 V−1 V Vref DT RDT A B Figure 36. Dead−time Generation Soft−Start Sequence In resonant controllers, a soft−start is needed to avoid suddenly applying the full current into the resonating circuit. With this controller the soft−start duration is fully adjustable using eternal components. The purpose of the Soft−Start pin is to discharge Soft−Start capacitor before IC restart and in case of fault conditions detected by Fault input. Once the controller starts operation, the Soft−Start capacitor (refer to Figure 37) is fully discharged and thus it starts charging from the Rt pin. The charging current increases operating frequency of the controller above Fmin. As the soft−start capacitor charges, the frequency smoothly decreases down to Fmin. Of course, practically, the feedback loop is supposed to take over the VCO lead as soon as the output voltage has reached the target. If not, then the minimum switching frequency is reached and a fault is detected on the feedback pin (typically below 300 mV). Figure 38 depicts a typical LLC startup using NCP1397A/B controller. SS Action Target is Reached Figure 38. A Typical Startup Sequence on a LLC Converter Using NCP1397 Please note that the soft−start capacitor is discharged in the following conditions: − A startup sequence − During auto−recovery burst mode − A brown−out recovery − A temperature shutdown recovery The skip/disable input undergoes a special treatment. Since we want to implement skip cycle using this input, we cannot activate the soft−start every time the feedback pin stops the operations in low power mode. Therefore, when the skip/enable pin is released, no soft−start occurs to offer the best skip cycle behavior. However, it is very possible to combine skip cycle and true disable, e.g. via ORing diodes driving Pin 8. In that case, if a signal maintains the skip/disable input high long enough to bring the feedback level down (below 0.3 V) since the output voltage starts to fall down, then the soft−start discharge switch is activated. SS Fmax RF(start) Rt RFmin RFmax CSS GND NCP1397 Fstart(adj) − RFstart/RFmin Fmin(adj) − RFmin Fmax(adj) − RFmax Figure 37. Soft−Start Components Arrangement www.onsemi.com 17 NCP1397A/B, NCV1397A/B Plot1 Vct in Volts 4.00 3.00 2.00 1.00 Ct Voltage 0 Plot2 Clock in Volts 16.0 Clock Pulses DT 12.0 8.00 4.00 0 DT Plot3 Difference in Volts 8.00 DT 4.00 0 −4.00 A−B −8.00 56.2 m 65.9 m 75.7 m time in seconds 85.4 m 95.1 m Figure 39. Typical Oscillator Waveforms Brown−Out protection Vbulk The Brown−Out circuitry (BO) offers a way to protect the resonant converter from low DC input voltages. Below a given level, the controller blocks the output pulses, above it, it authorizes them. The internal circuitry, depicted by Figure 40, offers a way to observe the high−voltage (HV) rail. A resistive divider made of Rupper and Rlower, brings a portion of the HV rail on Pin 5. Below the turn−on level, the 28 mA current source IBO is off. Therefore, the turn−on level solely depends on the division ratio brought by the resistive divider. Rupper VDD ON/OFF IBO BO + − BO Rlower + VBO Figure 40. The Internal Brown−out Configuration with an Offset Current Source www.onsemi.com 18 450 16.0 350 12.0 250 Vcmp in Volts Plot1 Vin in Volts NCP1397A/B, NCV1397A/B 351 V 250 V Vin 8.0 150 4.0 50 0 BO 20 m 60 m 100 m time in seconds 140 m 180 m Figure 41. Simulation Results for 350 / 250 ON / OFF Levels To the contrary, when the internal BO signal is high (Mlower and Mupper pulse), the IBO source is activated and creates a hysteresis. As a result, it becomes possible to select the turn−on and turn−off levels via a few lines of algebra: IBO is off V()) + V bulk1 R lower R lower ) R upper R lowerer + VBO ) IBO ǒ R lower R upper R lower ) R upper Latchoff Protection Ǔ (eq. 2) There are some situations where the converter shall be fully turned−off and stay latched. This can happen in presence of an overvoltage (the feedback loop is drifting) or when an over temperature is detected. Thanks to the addition of a comparator on the BO pin, a simple external circuit can lift up this pin above Vlatch (4 V typical) and permanently disable pulses. The VCC needs to be cycled down below 6.5 V typically to reset the controller. We can now extract Rlower from Equation 1 and plug it into Equation 2, then solve for Rupper: R upper + R lower ǒV bulk1 * VBOǓ Rupper = 3.57 MW Rlower = 10.64 kW The bridge power dissipation is 4002 / 3.781 MW = 45 mW when front−end PFC stage delivers 400 V. Figure 41 simulation result confirms our calculations. (eq. 1) R lower R lower ) R upper IBO If we decide to turn−on our converter for Vbulk1 equals 350 V and turn it off for Vbulk2 equals 250 V, then we obtain: IBO is on V()) + V bulk2 V bulk1 * V bulk2 V bulk1 * VBO VBO www.onsemi.com 19 NCP1397A/B, NCV1397A/B VCC Vbulk 20 ms RC + − Q1 Vout To permanent latch + Vlatch Rupper IBO VDD BO NTC Rlower + − BO + VBO Figure 42. Adding a Comparator on the BO Pin Offers a way to Latch−off the Controller discharges via an external parallel resistor. In case the overload lasts for more than timer duration (given by Itimer, Vtimer, Ctimer and Rtimer) the IC stops the operation and waits until the Ctimer will discharge to 1 V. The application then restarts via Soft−Start. In case of heavy overload, like transformer short circuit, the primary current grows very fast and thus could reach danger level prior the fault timer elapses. The NCP1397B therefore features additional comparator (1.55 V) on the Fault input to permanently latch the application and protect against destruction. Figure 44 depicts the architecture of the fault circuitry for NCP1397B controller. The NCP1397A features second fault comparator as well but in this case it doesn’t latches off the IC but speeds up the Fault timer capacitor charging by turning on additional current source Itimer2 – refer to Figure 43. The NCP1397A can thus be used in applications that have to recover automatically from any fault conditions. On Figure 42, Q1 is blocked and does not bother the BO measurement as long as the NTC and the optocoupler are not activated. As soon as the secondary optocoupler senses an OVP condition, or the NTC reacts to a high ambient temperature, Q1 base is brought to ground and the BO pin goes up, permanently latching off the controller. Protection Circuitry This resonant controller offers a dedicated input (Fault input) to detect primary overcurrent conditions and protect power stage from damage. Once the voltage on the Fault input exceeds 1.04 V threshold the external timer capacitor starts charging by Itimer1 current. Simultaneously the Soft−Start discharge switch is activated to shift operating frequency up to keep primary current at acceptable level. In case the overload disappears fast enough the Soft−Start discharge switch is open, Itimer1 current turned−off and timer capacitor www.onsemi.com 20 NCP1397A/B, NCV1397A/B discharge at VCC(on)/ restart if VFB < 0.3 V VDD SS(dis) VDD Css Itimer2 Itimer1 Ctimer Ctimer UVLO Reset Average Input Current Rtimer + - + Fault To Primary Current Sensing Circuitry + Vref(fault) + - VtimerON VtimerOFF + - 1 = ok 0 = fault VCC + Vref(OCP) + Vref(skip) + FB FB 1 = ok 0 = fault Reset DRIVING LOGIC Skip/Disable Skip SS Figure 43. Fault Input Logic for NCP1397A www.onsemi.com 21 A A B B NCP1397A/B, NCV1397A/B discharge at VCC(on)/ restart if VFB < 0.3 V SS(dis) VDD Css Itimer1 Ctimer Ctimer UVLO Reset Average Input Current Rtimer + - + Fault To Primary Current Sensing Circuitry + Vref(fault) + - to latch VtimerON VtimerOFF 1 = ok 0 = fault + VCC + Vref(OCP) + + FB Vref(skip) FB 1 = ok 0 = fault Reset DRIVING LOGIC Skip/Disable Skip SS A A B B Figure 44. Fault Input Logic for NCP1397B overload stays there, after a few tens of milli −seconds, switching pulses will disappear and a protective auto−recovery cycle will take place. Adjusting the resistor R in parallel with the timer capacitor will give the flexibility to adjust the fault burst mode (refer to Figure 45). On Figures 43 and 44 examples, a voltage proportional to primary current, once averaged, gives an image of the input power in case Vin is kept constant via a PFC circuit. If the output loading increases above a certain level, the voltage on this pin will pass the 1 V threshold and start the timer. If the www.onsemi.com 22 NCP1397A/B, NCV1397A/B SMPS Stops 4V Fault is Gone SMPS Re−starts 1V Reset at Re−start Figure 45. A Resistor Can Easily Program the Capacitor Discharge Time VCC lose regulation in light load conditions, forcing the FB level to increase. When it reaches the programmed level, it triggers the skip input and stops pulses. Then Vout slowly drops, the loop reacts by decreasing the feedback level which, in turn, unlocks the pulses, Vout goes up again and so on: we are in skip cycle mode. As the feedback voltage does not drop below 0.3 V the Soft−Start discharge switch is not activated in this case. Please refer also to Figure 35 for skip mode function implementation when optocoupler is connected directly to Rt pin. FB Skip/Disable Startup Behavior When the VCC voltage increases, the internal current consumption is kept below Istrup. When VCC reaches the VCC(on) level, output Mlower goes high first and then output Mupper. This sequence will always be the same whatever triggers the pulse delivery: fault, OFF to ON etc… Pulsing the output Mlower high first gives an immediate charge of the bootstrap capacitor. Then, the rest of pulses follow, delivered at the highest switching value, set by the RFstart resistor in parallel with RFmin resistor on Pin 4. The soft−start capacitor ensures a smooth frequency decrease to either the programmed minimum value (in case of fault) or to a value corresponding to the operating point if the feedback loop closes first. Figure 47 shows typical signals evolution at power on. Figure 46. Skip Cycle Can Be Implemented Via Two Resistors on the FB Pin to the Fast Fault Input Skip/Disable The Skip/Disable input is not affected by a delayed action. As soon as its voltage exceeds 0.66 V typical, all pulses are off and maintained off as long as the fault is present. When the pin is released, pulses come back and the soft−start is activated (in case the VFB < 0.3 V). Thanks to the low activation level, this pin can observe the feedback pin via a resistive divided and thus implement skip cycle operation. The resonant converter can be designed to www.onsemi.com 23 NCP1397A/B, NCV1397A/B Figure 47. At Power On, Output A is First Activated and the Frequency Slowly Decreases Based on the Soft−Start Capacitor Voltage Figure 47 depicts an auto−recovery situation, where the timer has triggered the end of output pulses. In that case, the VCC level was given by an auxiliary power supply, hence its stability during the hiccup. A similar situation can arise if the user selects a more traditional startup method, with an auxiliary winding. In that case, the VCC(min) comparator stops the output pulses whenever it is activated, that is to say, when VCC falls below 9.5 V typical. At this time, the VCC pin still receives its bias current from the startup resistor and increases toward VCC(on). When the voltage reaches VCC(on), a standard sequence takes place, involving a soft−start. Figure 48 portrays this behavior. www.onsemi.com 24 NCP1397A/B, NCV1397A/B Figure 48. When the VCC is to Low, All Pulses are Stopped Until VCC Goes Back to the Startup Voltage The High−Voltage Driver The driver features a traditional bootstrap circuitry, requiring an external high−voltage diode for the capacitor refueling path. Figure 49 shows the internal architecture of the high−voltage section. HV B Pulse Trigger Vboot Level Shifter S Cboot Mupper Q Q R HB UVLO Dboot VCC Fault A aux VCC Mlower Delay + GND Figure 49. The Internal High−voltage Section of the NCP1397 www.onsemi.com 25 NCP1397A/B, NCV1397A/B The device incorporates an upper UVLO circuitry that makes sure enough Vgs is available for the upper side MOSFET. The B and A outputs are delivered by the internal logic, as Figure 43 testifies. A delay is inserted in the lower rail to ensure good matching between these propagating signals. As stated in the maximum rating section, the floating portion can go up to 600 VDC and makes the IC perfectly suitable for offline applications featuring a 400 V PFC front−end stage. ORDERING INFORMATION Device Package Shipping† SOIC−16, Less Pin 13 (Pb−Free) 2500 / Tape & Reel NCP1397ADR2G NCV1397ADR2G* NCP1397BDR2G NCV1397BDR2G* †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. www.onsemi.com 26 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 NB, LESS PIN 13 CASE 751AM−01 ISSUE O DATE 20 AUG 2007 SCALE 1:1 D 16 A B 9 E H 0.25 M B M 1 8 e 15X C b C L 15X 0.25 M T A S B DIM A A1 b C D E e H h L M S A1 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. h x 45 _ A M GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 16 6.40 15X XXXXXXXXXG AWLYWW 1.12 1 16 1 15X 0.58 1.27 PITCH 8 MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ 9 XXXXX A WL Y WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G”, may or not be present. DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98AON25333D SOIC−16 NB, LESS PIN 13 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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