NCP145AMX120TCG

NCP145 500 mA, Very Low Dropout Bias Rail CMOS Voltage Regulator The NCP145 is a 500 mA VLDO equipped with NMOS pass transistor and a separate bias supply voltage (VBIAS). The device provides very stable, accurate output voltage with low noise suitable for space constrained, noise sensitive applications. In order to optimize performance for battery operated portable applications, the NCP145 features low IQ consumption. The XDFN4 1.2 mm x 1.2 mm package is optimized for use in space constrained applications. Features • • • • • • • • • • • • • Input Voltage Range: 1.0 V to 5.5 V Bias Voltage Range: 2.4 V to 5.5 V Fixed Voltage Versions Available Output Voltage Range: 1.0 V to 1.8 V (Fixed) ±1.5% Accuracy over Temperature, 0.5% VOUT @ 25°C Ultra−Low Dropout: Typ. 140 mV at 500 mA Very Low Bias Input Current of Typ. 80 mA Very Low Bias Input Current in Disable Mode: Typ. 0.5 mA Logic Level Enable Input for ON/OFF Control Output Active Discharge Option Available Stable with a 2.2 mF Ceramic Capacitor Available in XDFN4 − 1.2 mm x 1.2 mm x 0.4 mm Package These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant www.onsemi.com T MARKING DIAGRAM 1 XXM XDFN4 CASE 711BC 1 XX = Specific Device Code M = Date Code PIN CONNECTIONS 4 IN 3 EN 2 BIAS GND 5 OUT 1 (Top View) Typical Applications • Battery−powered Equipment • Smartphones, Tablets • Cameras, DVRs, STB and Camcorders ORDERING INFORMATION See detailed ordering, marking and shipping information on page 9 of this data sheet. VBIAS >2.7 V NCP145 100 nF BIAS VIN 1.5 V 1 mF EN VOUT 1 V up to 500 mA OUT IN 2.2 mF GND VEN Figure 1. Typical Application Schematics © Semiconductor Components Industries, LLC, 2017 March, 2018 − Rev. 1 1 Publication Order Number: NCP145/D NCP145 CURRENT LIMIT IN EN BIAS OUT ENABLE BLOCK UVLO 150 W VOLTAGE REFERENCE + − THERMAL LIMIT *Active DISCHARGE GND *Active output discharge function is present only in NCP145AMXyyyTCG devices. yyy denotes the particular output voltage option. Figure 2. Simplified Schematic Block Diagram www.onsemi.com 2 NCP145 PIN FUNCTION DESCRIPTION Pin No. XDFN4 Pin Name 1 OUT Regulated Output Voltage pin 2 BIAS Bias voltage supply for internal control circuits. This pin is monitored by internal Under-Voltage Lockout Circuit. 3 EN Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. 4 IN Input Voltage Supply pin 5 GND Description Ground ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit VIN −0.3 to 6 V VOUT −0.3 to (VIN+0.3) ≤ 6 V VEN, VBIAS −0.3 to 6 V Output Short Circuit Duration tSC unlimited s Maximum Junction Temperature TJ 150 °C TSTG −55 to 150 °C ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V ESD Capability, Machine Model (Note 2) ESDMM 200 V Input Voltage (Note 1) Output Voltage Chip Enable, Bias Input Storage Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection (except OUT pin) and is tested by the following methods: ESD Human Body Model tested per EIA/JESD22−A114 ESD Machine Model tested per EIA/JESD22−A115 Latchup Current Maximum Rating tested per JEDEC standard: JESD78. THERMAL CHARACTERISTICS Rating Thermal Characteristics, XDFN4 1.2 mm x 1.2 mm Thermal Resistance, Junction−to−Air (Note 3) Symbol Value Unit RqJA 170 °C/W 3. This data was derived by thermal simulations for a single device mounted on the 40 mm x 40 mm x 1.6 mm FR4 PCB with 2−ounce 800 sq mm copper area on top and bottom. www.onsemi.com 3 NCP145 ELECTRICAL CHARACTERISTICS −40°C ≤ TJ ≤ 85°C; VBIAS = 2.7 V or (VOUT + 1.6 V), whichever is greater, VIN = VOUT(NOM) + 0.3 V, IOUT = 1 mA, VEN = 1 V, unless otherwise noted. CIN = 1 mF, COUT = 2.2 mF. Typical values are at TJ = +25°C. Min/Max values are for −40°C ≤ TJ ≤ 85°C unless otherwise noted. (Note 4) Test Conditions Symbol Min Operating Input Voltage Range VIN Operating Bias Voltage Range VBIAS Parameter Undervoltage Lock−out VBIAS Rising Hysteresis Output Voltage Accuracy Typ Max Unit VOUT + VDO 5.5 V (VOUT + 1.40) ≥ 2.4 5.5 V UVLO 1.6 0.2 V VOUT ±0.5 % Output Voltage Accuracy −40°C ≤ TJ ≤ 85°C, VOUT(NOM) + 0.3 V ≤ VIN ≤ VOUT(NOM) + 1.0 V, 2.7 V or (VOUT(NOM) + 1.6 V), whichever is greater < VBIAS < 5.5 V, 1 mA < IOUT < 500 mA VOUT VIN Line Regulation VOUT(NOM) + 0.3 V ≤ VIN ≤ 5.0 V LineReg 0.01 %/V VBIAS Line Regulation 2.7 V or (VOUT(NOM) + 1.6 V), whichever is greater < VBIAS < 5.5 V LineReg 0.01 %/V Load Regulation IOUT = 1 mA to 500 mA LoadReg 1.5 mV VIN Dropout Voltage IOUT = 150 mA (Note 5) VDO 37 75 IOUT = 500 mA (Note 5) VDO 140 250 VBIAS Dropout Voltage IOUT = 500 mA, VIN = VBIAS (Note 5) VDO 1.1 1.5 V Output Current Limit VOUT = 90% VOUT(NOM) Bias Pin Operating Current VBIAS = 2.7 V Bias Pin Disable Current ICL −1.5 550 +1.5 % mV 800 1000 mA IBIAS 80 110 mA VEN ≤ 0.4 V IBIAS(DIS) 0.5 1 mA Vinput Pin Disable Current VEN ≤ 0.4 V IVIN(DIS) 0.5 1 mA EN Pin Threshold Voltage EN Input Voltage “H” VEN(H) EN Input Voltage “L” VEN(L) V 0.9 0.4 EN Pull Down Current VEN = 5.5 V IEN 0.3 Turn−On Time From assertion of VEN to VOUT = 98% VOUT(NOM). VOUT(NOM) = 1.2 V tON 215 ms Turn−On Slew Rate VEN 0 V to 1.0 V, VOUT(NOM) = 1.2 V, VOUT from 10 mV to 610 mV SR 15 mV/ms Power Supply Rejection Ratio VIN to VOUT, f = 1 kHz, IOUT = 150 mA, VIN ≥ VOUT +0.5 V PSRR(VIN) 70 dB PSRR(VBIAS) 80 dB VN 40 mVRMS °C VBIAS to VOUT, f = 1 kHz, IOUT = 150 mA, VIN ≥ VOUT +0.5 V Output Noise Voltage VIN = VOUT +0.5 V, VOUT(NOM) = 1.0 V, f = 10 Hz to 100 kHz Thermal Shutdown Threshold Temperature increasing 160 Temperature decreasing 140 Output Discharge Pull−Down VEN ≤ 0.4 V, VOUT = 0.5 V, NCP145A options only RDISCH 150 1 mA W Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at TA = 25°C. Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible. 5. Dropout voltage is characterized when VOUT falls 3% below VOUT(NOM). www.onsemi.com 4 NCP145 TYPICAL CHARACTERISTICS VDO (VIN − VOUT) DROPOUT VOLTAGE (mV) At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 2.7 V, VEN = VBIAS, VOUT(NOM) = 1.0 V, IOUT = 500 mA, CIN = 1 mF, CBIAS = 0.1 mF, and COUT = 2.2 mF (effective capacitance), unless otherwise noted. VDO (VIN − VOUT) DROPOUT VOLTAGE (mV) 200 180 160 +125°C +85°C 140 120 100 −40°C 80 60 40 +25°C 20 0 100 200 400 300 150 +125°C +85°C 100 +25°C −40°C 50 VDO (VBIAS − VOUT) DROPOUT VOLTAGE (mV) 100 80 +125°C 60 +85°C 40 20 0 0.5 1.0 1.5 2.0 +25°C −40°C 2.5 3.0 3.5 4.0 Figure 4. VIN Dropout Voltage vs. (VBIAS − VOUT) and Temperature TJ 200 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4.5 500 450 IOUT = 500 mA 400 350 300 +125°C 250 +85°C 200 +25°C 150 −40°C 100 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VBIAS − VOUT (V) VBIAS − VOUT (V) Figure 5. VIN Dropout Voltage vs. (VBIAS − VOUT) and Temperature TJ Figure 6. VIN Dropout Voltage vs. (VBIAS − VOUT) and Temperature TJ 4.5 140 1500 1400 120 +125°C 1300 +85°C +125°C 100 IBIAS (mA) −40°C 1200 +25°C 1100 80 60 −40°C +25°C 40 +85°C 1000 900 120 Figure 3. VIN Dropout Voltage vs. IOUT and Temperature TJ IOUT = 300 mA 0.5 160 140 VBIAS − VOUT (V) 250 0 IOUT = 100 mA 180 IOUT, OUTPUT CURRENT (mA) 300 VDO (VIN − VOUT) DROPOUT VOLTAGE (mV) 500 VDO (VIN − VOUT) DROPOUT VOLTAGE (mV) 0 200 20 0 50 100 150 200 250 300 0 0 50 100 150 200 250 300 350 400 450 500 IOUT, OUTPUT CURRENT (mA) IOUT, OUTPUT CURRENT (mA) Figure 7. VBIAS Dropout Voltage vs. IOUT and Temperature TJ Figure 8. BIAS Pin Current vs. IOUT and Temperature TJ www.onsemi.com 5 NCP145 TYPICAL CHARACTERISTICS At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 2.7 V, VEN = VBIAS, VOUT(NOM) = 1.0 V, IOUT = 500 mA, CIN = 1 mF, CBIAS = 0.1 mF, and COUT = 2.2 mF (effective capacitance), unless otherwise noted. 200 1000 180 900 ICL, CURRENT LIMIT (mA) 160 IBIAS (mA) 140 120 +125°C +85°C 100 80 60 40 20 0 2.0 +25°C −40°C +125°C 800 700 +85°C +25°C 600 −40°C 500 400 300 200 100 2.5 3.0 3.5 4.0 4.5 5.0 0 5.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VBIAS (V) VBIAS − VOUT (V) Figure 9. BIAS Pin Current vs. VBIAS and Temperature TJ Figure 10. Current Limit vs. (VBIAS − VOUT) www.onsemi.com 6 NCP145 TYPICAL CHARACTERISTICS 50 mV/div VOUT tR = tF = 1 ms 200 mA/div tR = tF = 1 ms VOUT IOUT IOUT 50 ms/div Figure 12. Load Transient Response, IOUT = 50 mA to 500 mA, COUT = 2.2 mF 50 mV/div 50 ms/div Figure 11. Load Transient Response, IOUT = 50 mA to 500 mA, COUT = 10 mF VOUT VOUT tR = tF = 1 ms 200 mA/div 200 mA/div 50 mV/div 200 mA/div 50 mV/div At TJ = +25°C, VIN = VOUT(TYP) + 0.3 V, VBIAS = 2.7 V, VEN = VBIAS, VOUT(NOM) = 1.0 V, IOUT = 500 mA, CIN = 1 mF, CBIAS = 0.1 mF, and COUT = 2.2 mF (effective capacitance), unless otherwise noted. tR = tF = 1 ms IOUT IOUT 500 ms/div 500 ms/div Figure 14. Load Transient Response, IOUT = 1 mA to 500 mA, COUT = 2.2 mF 10 mV/div 10 mV/div Figure 13. Load Transient Response, IOUT = 1 mA to 500 mA, COUT = 10 mF VOUT VOUT tR = tF = 5 ms VIN VIN 1 V/div 1 V/div tR = tF = 5 ms 20 ms/div 20 ms/div Figure 15. VIN Line Transient Response, VIN = 1.3 V to 2.3 V, IOUT = 100 mA, COUT = 10 mF Figure 16. VIN Line Transient Response, VIN = 1.3 V to 2.3 V, IOUT = 100 mA, COUT = 2.2 mF www.onsemi.com 7 NCP145 APPLICATIONS INFORMATION NCP145 VBAT EN Switch−mode DC/DC VOUT = 1.5 V IN LX EN FB Processor BIAS 1.5 V OUT 1.0 V IN LOAD GND GND I/O I/O To other circuits Figure 17. Typical Application: Low−Voltage DC/DC Post−Regulator with ON/OFF Functionality or greater. Ceramic capacitors are recommended. For the best performance all the capacitors should be connected to the NCP145 respective pins directly in the device PCB copper layer, not through vias having not negligible impedance. When using small ceramic capacitor, their capacitance is not constant but varies with applied DC biasing voltage, temperature and tolerance. The effective capacitance can be much lower than their nominal capacitance value, most importantly in negative temperatures and higher LDO output voltages. That is why the recommended Output capacitor capacitance value is specified as Effective value in the specific application conditions. The NCP145 dual−rail very low dropout voltage regulator is using NMOS pass transistor for output voltage regulation from VIN voltage. All the low current internal control circuitry is powered from the VBIAS voltage. The use of an NMOS pass transistor offers several advantages in applications. Unlike PMOS topology devices, the output capacitor has reduced impact on loop stability. Vin to Vout operating voltage difference can be very low compared with standard PMOS regulators in very low Vin applications. The NCP145 offers smooth monotonic start-up. The controlled voltage rising limits the inrush current. The Enable (EN) input is equipped with internal hysteresis. NCP145 Voltage linear regulator Fixed version is available. Enable Operation The enable pin will turn the regulator on or off. The threshold limits are covered in the electrical characteristics table in this data sheet. If the enable function is not to be used then the pin should be connected to VIN or VBIAS. Dropout Voltage Because of two power supply inputs VIN and VBIAS and one VOUT regulator output, there are two Dropout voltages specified. The first, the VIN Dropout voltage is the voltage difference (VIN – VOUT) when VOUT starts to decrease by percent specified in the Electrical Characteristics table. VBIAS is high enough; specific value is published in the Electrical Characteristics table. The second, VBIAS dropout voltage is the voltage difference (VBIAS – VOUT) when VIN and VBIAS pins are joined together and VOUT starts to decrease. Current Limitation The internal Current Limitation circuitry allows the device to supply the full nominal current and surges but protects the device against Current Overload or Short. Thermal Protection Internal thermal shutdown (TSD) circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When TSD activated , the regulator output turns off. When cooling down under the low temperature threshold, device output is activated again. This TSD feature is provided to prevent failures from accidental overheating. Activation of the thermal protection circuit indicates excessive power dissipation or inadequate heatsinking. For reliable operation, junction temperature should be limited to +125°C maximum. Input and Output Capacitors The device is designed to be stable for ceramic output capacitors with Effective capacitance in the range from 2.2 mF to 10 mF. The device is also stable with multiple capacitors in parallel, having the total effective capacitance in the specified range. In applications where no low input supplies impedance available (PCB inductance in VIN and/or VBIAS inputs as example), the recommended CIN = 1 mF and CBIAS = 0.1 mF www.onsemi.com 8 NCP145 ORDERING INFORMATION Device Nominal Output Voltage Marking NCP145AMX100TCG 1.00 V HE NCP145AMX105TCG 1.05 V HG NCP145AMX120TCG 1.20 V HD Option Package Shipping† Output Active Discharge XDFN4 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. To order other package and voltage variants, please contact your ON Semiconductor sales representative www.onsemi.com 9 NCP145 PACKAGE DIMENSIONS XDFN4 1.2x1.2, 0.8P CASE 711BC ISSUE O A B D PIN ONE REFERENCE ÉÉÉ ÉÉÉ NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 mm FROM THE TERMINAL TIPS. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DETAIL B E DETAIL B TOP VIEW A3 SIDE VIEW A 0.05 C A1 4X (0.12) SIDE VIEW SEATING PLANE C 4X D2 1 e/2 2 0.05 e M b C A B NOTE 3 4X L1 RECOMMENDED MOUNTING FOOTPRINT* PACKAGE OUTLINE 4 MILLIMETERS MIN MAX 0.35 0.45 0.00 0.05 0.13 REF 0.25 0.35 0.15 0.25 1.15 1.25 0.58 0.68 1.15 1.25 0.58 0.68 0.80 BSC 0.25 0.35 0.13 0.23 L DETAIL A E2 DETAIL A (0.12) 4X 0.05 C NOTE 4 DIM A A1 A3 b b1 D D2 E E2 e L L1 ALTERNATE CONSTRUCTION 4X 1.50 0.25 C 0.195 0.22 3 b1 BOTTOM VIEW 4X 0.80 PITCH 0.35 2X 0.63 1 4X 0.48 45 5 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ◊ N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 www.onsemi.com 10 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP145/D