NCP1562-100WGEVB

NCP1562-100WGEVB NCP1562 100 W 48 V DC-DC Converter Evaluation Board User'sManual http://onsemi.com EVAL BOARD USER’S MANUAL Introduction • Line Feedforward: The NCP1562 PWM controller contains all the features and flexibility needed to implement an active clamp forward dc−dc converter. This IC operates from an input supply up to 150 V, thus covering the input voltages usually found in telecom, datacom and 42 V automotive systems. One can also note that the NCP1562 can be used in mains related applications (e.g. desktop, server, flat TVs) as it can be supplied by an auxiliary power supply. The NCP1562 is the ideal choice for new generation isolated fixed switching frequency dc−dc converters using the active clamp topology with synchronous rectification to achieve extremely high conversion efficiency. This controller will help designers cope with their daily challenge, “small form factor highly protected module” through the following features: • Dual Outputs with Adjustable Overlap Delay: provide design flexibility. Output 1 (OUT1) drives the main switch in a forward or flyback converter topology. Output 2 (OUT2) can be used to drive an active clamp/reset switch, a synchronous rectifier switch, or both. OUT2 has an adjustable overlap delay to prevent simultaneous conduction of the switching elements. • Soft−Stop: discharges the active clamp capacitor prior to turn off to eliminate unwanted oscillations. • An Internal Startup Regulator: provides power to the NCP1562 during startup. Once the system powers up, the regulator is disabled, thus reducing power consumption. The regulator can be powered directly from the input line. • Soft−Start: allows the system to turn on in a controlled manner and reduce stress on system components. • Adjustable Maximum Duty Ratio: allows the design to be optimized without a penalty on drain voltage. Duty ratio is controlled within ±5%. • Adjustable Volt-second Limit: prevents transformer saturation and improve transient response. © Semiconductor Components Industries, LLC, 2012 October, 2012 − Rev. 2 • • adjusts the duty ratio inversely proportional to line voltage, allowing the controller to respond in the same cycle to line voltage changes. It provides the controller some advantages of current-mode control, while eliminating noise susceptibility, low power jitter and the need for ramp compensation. Dual Mode Overcurrent Protection Circuit: handles momentary and continuous overcurrent conditions differently to provide the best tradeoff in system performance and safety. Line Under/Overvoltage Detector: circuits enable the device when the line voltage is within the pre-selected voltage range. A resistor divider from the input line biases the under and overvoltage detectors. The accurate UV limit allows the converter to operate at high duty ratio without creating additional component stresses. Figure 1. NCP1562 Evaluation Board 1 Publication Order Number: EVBUM2148/D NCP1562−100WGEVB DESIGN SPECIFICATIONS Active Clamp Forward Topology The flexibility of the NCP1562 is demonstrated by examining a detailed design of a dc−dc converter for the telecom system. The converter delivers up to 100 W at 3.3 V. The converter specifications are listed in Table 1. A forward active clamp topology is selected for the converter, as it provides very high efficiency. The active clamp forward (ACF) topology has multiple advantages compared to a traditional forward converter. The benefits of the active clamp topology can be easily maximized once the unique characteristics of this topology are fully understood. Figure 2 shows a simplified schematic of an active clamp forward topology. The transformer model (TX1) consists of an ideal transformer, magnetizing (LMAG) and leakage (LLKG) inductances. The active clamp network consists of the P-channel clamp switch (Qclamp) and clamp capacitor (Cclamp). This configuration is known as low side active clamp. A high side clamp could have been implemented using an N-channel MOSFET and clamp capacitor in parallel with the transformer primary. However, it requires a floating gate drive signal increasing system cost and complexity. Table 1. DESIGN SPECIFICATIONS Parameter Input Voltage Frequency Symbol Min Max Vin (V) 33 76 fSW(kHz) Full Load Efficiency h (%) − D − 65% Duty Ratio Output Voltage 350 (typ) 90 Vout (V) 3.267 3.333 Vout(rip) (mV) − 50 Output Current Iout (A) 3 30 Output Power Pout (W) − 100 TA (C) − Output Voltage Ripple Ambient Temperature Derating Factor − TX1 + Vin − 50 90% NP:NS = 1:N ISEC/N IMAG Lout Synchronous Rectifier Control LMAG LLKG QFW Cout IP QREC NCP1562 OUT1 OUT2 ISEC Qmain Cdrain Cclamp Qclamp CC Figure 2. Active Clamp Forward Converter The differences between traditional and active clamp forward converters are during the main switch off time. In the active clamp topology, the transformer is reset at a lower voltage during the complete off time instead of a higher voltage during a shorter period of time. Figure 3 shows a comparison between the drain waveforms of both topologies. The traditional forward waveform was taken with a primary:reset winding ratio of 5:3 instead of 1:1. The 5:3 ratio allowed operation above 50% duty cycle. Reset Winding Active Clamp Figure 3. Drain Voltage Waveforms for Traditional and Active Clamp Forward Topologies http://onsemi.com 2 NCP1562−100WGEVB transformer and the main switch. This current is the sum of the transformer magnetizing (IMAG) and reflected secondary currents. No current flows through Qclamp and current flows in the secondary side through the forward rectifier, QREC. The primary current continues to build while Qmain is on. Time interval t1 − t2: The main switch turns off at t1. The forward rectifier turns off at t1 eliminating the reflected secondary current component from IP if the leakage inductance effect is neglected. The primary current is now the magnetizing current. It continues to flow in the same direction charging the drain capacitance, Cdrain. Time interval t2 – t3: At time t2 the drain voltage reaches the clamp capacitor voltage. The primary current charges both the drain capacitance and Cclamp. The primary current flows through the body diode of Qclamp. The clamp capacitor is several orders of magnitude larger Cdrain, causing the voltage slope to drop. The drain ripple voltage is determined by the resonance between LMAG and Cclamp. Time interval t3−t4: The active clamp switch can turn on at any time between t2 and t4 under ZVS conditions. Once Qclamp turns on, current flows through its channel. The magnitude of IP is decreasing and reaches zero at t4. It is imperative for Qclamp to be on at t4. Otherwise, IP will not have a path to reverse its direction. Time interval t4−t5: The primary current has reversed direction and is now discharging Cclamp. The drain voltage begins to decrease. The magnetizing current continues to build up in the reverse direction. Time interval t5−t6: The active clamp switch turns off at t5. It is critical to achieve a fast turn off Qclamp to force the magnetizing current to discharge the drain capacitance. Otherwise, current will continue flowing through Qclamp. The drain voltage decays as the drain capacitance is discharged. The minimum drain voltage is determined by the inductive energy (EL) stored in the magnetizing and leakage inductances. If the inductive energy is greater than the capacitive energy stored in the drain capacitance, ZVS is achieved. If the magnetizing energy is not enough, an external inductor can be added to facilitate ZVS. The inductive energy is increased by reducing LMAG. This might be counter intuitive. But let me explain; Let’s start with the magnetizing energy equation given by Equation 1. The differences go beyond the replacement of the reset winding and catch diode with a clamp capacitor and a clamp switch. There are many system considerations and benefits provided by the active clamp topology as described below: 1. Facilitates zero volt switching (ZVS) or low-voltage/soft switching of the main and active clamp switches. 2. The ability to operate above 50% duty ratio with a high turns ratio without a penalty on drain voltage. 3. A high turns ratio reduces: a) The reflected output current component on the primary side allowing the use of a smaller Qmain. b) The secondary voltage allowing the use of lower voltage rectification elements. 4. Lower output inductance is required due to the higher duty ratio. 5. Signals for driving a synchronous rectifier are readily available. The operation of the active clamp forward is discussed in detail with the use of Figure 4. This figure shows the power stage waveforms of an active clamp forward converter in steady state. One switch cycle is divided in several time intervals to facilitate the analysis. OUT1 OUT2 VDS IQ(main) IP t2 t0 t1 t3 t4 t5 t6 EL(MAG) + 1 @ LMAG @ IMAG 2 2 Figure 4. Active Clamp Forward Waveforms (eq. 1) For a given voltage and on time, the LMAG and IMAG product is constant. That is, if LMAG decreases by 1/2, IMAG increases by 2. As IMAG is squared, the net effect is an increase in energy. Time interval t0 − t1: The main switch turns on at t0. The active clamp switch remains off. The primary current (IP) flows through the http://onsemi.com 3 NCP1562−100WGEVB Design Procedure 150 The converter design is divided in several steps to ease the design process. The process begins with the power stage as it determines most of the system components. The design continues with the feedback loop followed by the setup of the controller, the NCP1562. Finally, the system performance is evaluated and compared to the design target. Throughout this application note, operation at the minimum and maximum input voltages are referred as low and high line, respectively. VDS, DRAIN VOLTAGE (V) 125 Transformer A power transformer (TX1) is used to step down the voltage and provide voltage isolation between the input supply and the load. The transformer in this design has three windings; primary, secondary and auxiliary. Contrary to a traditional forward transformer, an active clamp transformer is designed with low magnetizing inductance. The stored magnetizing energy is used to discharge the drain capacitance and facilitate ZVS as explained earlier. In addition, LMAG affects the loop response as it affects a pair of complex zeros introduced by the active clamp stage. It is discussed later in the feedback loop section. The input to output voltage relationship is described by Equation 2. Vout + ǒVin * VNDS(on) * Vf (QREC) Ǔ @ D Vin 1*D N=5 75 50 25 0 30 40 50 60 70 80 Vin, INPUT VOLTAGE (V) Figure 5. Clamp Voltage vs. Input Voltage for Several Turns Ratios Using the design tool a turns ratio of 6 is selected for a maximum duty ratio of 63%. The ideal turns ratio is 6.5, but it would have increased the complexity of the transformer. In high current output converters, it is desired to keep the secondary turns at the lowest level (e.g. 1 turn) to reduce conduction losses. The primary turns (NP) are set at 6 and the secondary turns (NS) are set at 1. A 12:2 (NP:NS) ratio could have been used to reduce core losses. Low core losses are beneficial when conduction losses are low, as can be the case when operation at high line. The magnetizing inductance is set at 120 mH to reduce conduction losses. A planar transformer is selected due to its low profile and repeatable characteristics. The custom transformer is manufactured by Payton Planar Magnetics and can be easily ordered under part number 51665. (eq. 2) where, N is the primary to secondary turns ratio, VDS(on) is the voltage drop across Qmain, Vf(QREC) is the voltage drop across QREC, D is the duty ratio and Vin is the input voltage. Equation 2) is used to select N given a target maximum duty ratio. An additional factor to consider in the selection of N is the drain voltage of the main switch (VDS) during the off time as it depends on the duty ratio. Equation 3 shows the relationship between VDS and D. VDS + N=6 100 Active Clamp Stage The active clamp topology recycles the transformer magnetizing energy using a resonant circuit. This resonant circuit is composed of the magnetizing inductance and clamp capacitor. The parasitic drain capacitance and leakage inductance are ignored as they are very small. The resonant frequency of LMAG and Cclamp is selected low enough to maintain a constant voltage during the main switch off time. That is, the resonant period is significantly larger than the switching period of the controller. The clamp capacitor determines the drain ripple voltage (VDS(ripple)) during the main switch off time. The ripple voltage is inversely proportional to Cclamp. The active clamp capacitor also affects the loop response as it contributes to a pair of complex zeros introduced by the active clamp stage. It is discussed later in the Feedback Loop Section. If duty (eq. 3) The NCP1562 Excel-based design tool (downloadable from http://www.onsemi.com). provides an easy way to evaluate the interaction between the turns ratio, duty ratio and maximum drain voltage as shown in Figure 5. The drain voltage is almost constant over the complete operating range. A high turns ratio is desired to reduce the primary current and the secondary voltage. However, it causes the drain voltage to increase very rapidly at low line. The ideal turns ratio is the one that achieves equal drain voltages at low and high line. http://onsemi.com 4 NCP1562−100WGEVB ratio changes rapidly, the voltage across Cclamp has to change accordingly. Otherwise, the transformer may saturate. Therefore, a tradeoff between ripple voltage and transient response has to be considered in the selection of Cclamp. The design tool facilitates the selection of Cclamp by plotting VDS(ripple) and the normalized peak flux excursion vs Cclamp as shown in Figure 6. VDS(ripple), DRAIN VOLTAGE RIPPLE (V) 60 where: D(min) is the minimum duty ratio. Solving Equation 6: Lout + 3.0 2.5 NORMALIZED PEAK FLUX 40 2.0 Flux at Low Line 30 1.5 20 1.0 Iout(rip) + 0 2 4 6 8 10 12 14 16 18 Iout(rip) + IL, INDUCTOR CURRENT (A) (eq. 4) It is absolutely critical to consider the ripple current rating in the selection of Cclamp. Otherwise, the capacitor may overheat. The minimum ripple current rating of Cclamp is determined by the magnetizing rms current. Assuming the magnetizing current reverses direction halfway during the off time, the clamp capacitor rms current is approximated by Equation 5. Vin @ D SW @ LMAG Ǹ1 *2 D SW Ǔ + 4.58 A Low Line 31 30 29 28 0 0.5 1.0 1.5 2.0 2.5 3.0 The minimum output capacitance required to maintain the output voltage ripple below our target of 50 mV is calculated using Equation 8. Cout + Iout(rip) 8 @ f SW @ Vout(rip) (eq. 8) A minimum capacitance of 33 mF is required. The capacitor ESR also affects the output voltage ripple as shown in Equation 9. Vout(rip) + Iout(rip) @ RESR (eq. 9) In order to maintain Vout(rip) below our target, RESR has to be below 10.9 mW. Please consider that Equation 8 provides a minimum value to maintain Vout(rip) within target. In most cases, a higher Cout is required to meet voltage holdup requirements and shape the frequency response of the converter as it is 1*D(min) f 1.5 Figure 7. Calculated Output Inductor Current at Low and High Conditions (eq. 5) The output L−C (Lout−Cout) filter averages the square wave signal at the transformer output. The output inductor, Lout, is sized such that it operates in continuous conduction mode at the minimum output current, Iout(min) using Equation 6. Lout + Ǔ 3.3 @ ǒ1*0.271 350 Time (ms) Output L−C Filter ǒ (eq. 7) 32 27 The worst case condition is at high line. Using the Design Tool, an rms magnetizing current of 0.294 A is calculated. A ceramic capacitor is preferred due its low equivalent series resistance (ESR). TDK’s C3216X7R2J103M is used. Although maximum drain voltage of this design is 150 V, a 630 V capacitor is used as it is readily available. Vout @ SW High Line The magnetizing current charges and discharges the active clamp capacitor every cycle and is given by Equation 4. ICclamp(rms) [ f f Lout 33 Figure 6. VDS(ripple) and Normalized Peak Flux vs. Cclamp Vin @ D SW @ LMAG Vout @ 1*ton(min) a maximum ripple current of 4.58 A is obtained. Figure 7 shows the inductor current at low and high line as provided by the Design Tool. 0 CLAMP CAPACITANCE (nF) IMAG [ f + 1.15 mH Solving Equation 7: 0.5 10 0 2@3 using the D(min) provided by the Design Tool, a minimum inductance of 1.15 mH is required. A custom 1.5 mH inductor from Payton Planar Magnetics is used. It can be easily ordered under part number 51666. The inductor ripple current, Iout(rip), reaches its maximum value at high line and it is given by Equation 7. Ripple Voltage at High Line 50 Ǔ 3.3 @ ǒ1*0.271 350 (eq. 6) 2 @ Iout(min) http://onsemi.com 5 NCP1562−100WGEVB described later in the Feedback Loop Section. For this design, Cout is set at 544 mF using a parallel combination of tantalum capacitors for bulk capacitance and ceramic capacitors for RESR reduction. where, VDS is the drain voltage at which the main switch turns on, tsw(on) is the switch turn on time. The main switch turn off switching losses are very small and are ignored. In an active clamp converter, the main switch achieves Zero-Volt Switching (ZVS) under specific operating conditions. ZVS is affected by input voltage and output load. Even if ZVS is not achieved, reduced voltage switching is obtained. As a first approximation, the input voltage is used as the switch voltage at turn-on for our calculations. The capacitance at the drain voltage should be minimized to facilitate ZVS. That includes the main and active clamp switches output capacitance (Coss) and transformer capacitance. Therefore, Coss should also be considered in addition to the typical RDS(on) and gate charge parameters for the selection of the main switch. Fairchild’s FDD2582 is selected for this design as it provides the best tradeoff between RDS(on) and Coss. It is a 150 V N-channel MOSFET with an RDS(on) of 58 mW. Using the Design Tool the power dissipation of the main switch at high and low line assuming a 50 ns turn on time is calculated to be 1.49 W and 1.56 W, respectively. Power dissipation of the main switch is dominated at low line by conduction losses and at high line by switching losses. The maximum power dissipation of the main switch is calculated using Equation 14. Main Switch A MOSFET is used as the main switch. Several factors, including current, voltage stress and power dissipation are considered for the MOSFET selection. The shape of the primary current is shown in Figure 8. It consists of the primary magnetizing and reflected output currents. The valley of the primary current, IP(VL) is approximated to the inductor current divided by the turns ratio. In practice, IP(VL) is slightly less as the magnetizing current starts negative due to the resonant transition. But it is a good approximation as the magnetizing current is significantly smaller than the reflected output inductor current. IMAG IP(PK) Iout/N P+ IP(VL) T Figure 8. Primary Current Waveform The primary peak current, IP(PK), is given by Equation 10. The maximum IP(PK) occurs at high line when the output inductor ripple current is at its highest. Iout ) Iout(rip) Vin @ D 2 ) N LMAG @ f SW (eq. 10) The main switch experiences conduction and switching losses. The conduction losses are given by Equation 11. Pcon + IP(rms) 2 @ RDS(on) (eq. 11) where, RDS(on) is the switch on resistance and IP(rms) is the primary rms current. The primary rms current is given by Equation 12. Ǹǒ IP(RMS) + IP(PK) 2 * IP(PK) @ IP(VL) ) IP(VL) 2 3 Ǔ Active Clamp Switch The active clamp switch experiences low conduction losses because only the magnetizing current flows through it. Switching losses are negligible because the active clamp switch is turned on after the body diode is conducting. IR’s IRF6217PBF is used for the active clamp switch. It is a 150 V P-channel MOSFET with an on resistance of 2.4ĂW. Only conduction losses are considered for the power dissipation of the active clamp switch. Solving Equation 11, @ D (eq. 12) The turn on switching loss of the main switch is approximated by Equation 13. PSW(Qmain) + VDS @ IP(VL) @ tSW(on) @ f SW 6 (eq. 14) where, RθJA is the junction to ambient thermal resistance and TJ(max) and TA(max) are the maximum junction and ambient temperatures, respectively. Please keep in mind that Equation 14 assumes there are no other heat sources in the system. However, this is not the case in a real system. As specified in Table 1, TA(max) is 50°C. Solving Equation 14 for TJ(max) at high line, a maximum TJ of 131°C is calculated. The maximum allowed TJ is 158°C assuming an 90% derating for TJ(max) of the FDD2582. Power dissipation of the main switch is high and should be verified during design validation to make sure it is still within acceptable limits. However, keep in mind that this is a worst case scenario as the provided RqJA does not include airflow. Also, it is for a lower copper weight than the one used on this board. The thermal resistance of the main switch can be reduced by maximizing the copper area around the package. A heatsink can also be added on top of the package. ton IP(PK) + TJ(max) * TA(max) RqJA (eq. 13) http://onsemi.com 6 NCP1562−100WGEVB a power dissipation of 0.58 W is calculated for a TJ(max) of 79_C. The designer may be tempted to use a lower on resistance switch to reduce conduction losses. However, this may counterproductive. The active clamp switch has to turn off quickly to divert the magnetizing current and discharge the drain capacitance to achieve ZVS. If not, the magnetizing current will keep flowing through the switch preventing the drain capacitance to be discharged and achieve ZVS. A larger active clamp switch will have lower conduction losses but may increase switching losses on the main switch if ZVS is affected. The low side active clamp circuit is easier to implement as it is compatible with a ground referenced gate drive signal. However, it requires a negative voltage to turn on the P-channel MOSFET. It is generated using a level shift circuit as the one shown in Figure 2. Active clamp forward converter. It consists of a diode and an ac coupling capacitor (CC). The ac coupling capacitor is selected using Equation 15. CC + VDRV @ (1 * D) @ D QG ) DVC @ RGS @ f SW DVC The number of auxiliary turns (NAUX) is calculated using Equation 16. NAUX [ IAUX + IAUX3 ) f @ (QT(main) ) QT(clamp)) (eq. 15) The NCP1562 has an internal startup circuit. It charges the supply capacitor (CAUX) on the VAUX pin until the startup threshold is reached. The startup circuit is then disabled and the controller is biased by CAUX. The auxiliary capacitor is sized to store enough energy to maintain VAUX above its turnoff threshold, VAUX(off2). An auxiliary supply biases VAUX under normal operating conditions to prevent the converter from turning off. The auxiliary supply can be generated from a winding on the transformer or on the output inductor. The main difference is the speed at which the supply voltage builds up. The supply from the transformer builds up quickly where as the output inductor supply builds up with Vout. However, the output inductor supply is inherently regulated. In this design, the auxiliary supply is implemented from the transformer to reduce the value of CAUX. An L−C filter (LAUX−CAUX) is used to average the voltage from the auxiliary winding as shown in Figure 9. To VAUX Pin VAUX + − CAUX Vf (eq. 17) where, IAUX3 is the controller bias current (refer to the NCP1562 datasheet) and QT(main) and QT(clamp) are the total gate charge of the main and active clamp switches, respectively. Solving Equation 17, an IAUX of 23.2 mA is obtained. The required inductor for an IAUX(min) of 15% of IAUX is 694 mH. Coilcraft’s DO1606T series is selected for the auxiliary inductor. This series is very rugged and has a very low profile. The next size up in the DO1606T series is used. It is 1000 mH. As previously discussed, CAUX must be sized to maintain VAUX above VAUX(off2) during startup. The NCP1562 reduces the CAUX requirement by turning on the startup circuit if an intermediate threshold (VAUX(off1)) is reached. This, in addition to the other factors that affect the auxiliary supply (load current, soft start period, etc.) make the selection of VAUX non trivial. Empirically it was found that 88 mF works well under all operating conditions. However, 116ĂmF was used as the components were readily available from distribution. The VAUX capacitance consists of one 22ĂmF ceramic capacitor across the NCP1562 to reduce noise, and two 47 mF tantalum capacitors for bulk storage. Auxiliary Supply Regulator − (eq. 16) SW Solving Equation 16, 3.6 turns are required for a VAUX of 12 V and a Vf of 0.7 V. The turns are rounded up to 4 for a VAUX of 13.35 V. The LC filter averages the voltage as long as the inductor operates in continuous conduction mode. The auxiliary inductor value is selected in the same manner as the output inductor using Equation 6 by replacing the “out” subscript with “AUX”. The auxiliary current (IAUX) is calculated using Equation 17. where, QG is the total gate charge of the switch, VDRV is the gate drive voltage, DVC is the gate voltage ripple (should be ~10% VDRV), and RGS is the gate to source resistor. A 0.01ĂmF is used for a 12 V gate voltage with an RGS of 10 kW. LAUX AUX ) Vf Ǔ @ Np ǒVDC Vin Input Filter An input L−C (Lin−Cin) filter is used to reduce EMI and provide a solid input voltage to the converter. The input filter design is constrained by stability and power rating criteria. Oscillation will occur if the converter input impedance, Zin, is lower than the filter output impedance, Zout. The converter closed loop input impedance is ultimately determined by the converter feedback loop. However, the converter input impedance can be approximated as a negative resistor using 18. outǓ ǒVIout + Zin(dBW) [ −20 log NAUX The L−C filter output impedance is given by 19. ǒ R Zout(dBW) [ Lin ø n @ Cin ) ESR n NS (eq. 18) Ǔ (eq. 19) where, n is the number of capacitors in parallel. The input inductor is selected to handle the converter average input current. Coilcraft’s DS3316P−152 is used as the input inductor. NP TX1 Figure 9. Auxiliary Supply Architecture http://onsemi.com 7 NCP1562−100WGEVB The input capacitors are selected based on the input ripple current given by 20. Ceramic capacitors are preferred due their low ESR and high ripple current capability. TDK’s C4532X7R2A225MT are used as the input capacitors. Ǹǒ Iin(rms) + IMAG 2(1−D) D 2)I 2 I P(PK)IP(VL) ) IP(PK) Ǔ ) 3 P(VL) 2 In general, if the system oscillates, the input filter output impedance can be decreased as in most cases the converter input impedance is dictated by the system specifications. This can be accomplished adding a damping network. Synchronous Rectification (eq. 20) Low output voltage converters require synchronous rectification to achieve high efficiency. If a diode is used for rectification, the forward voltage drop becomes a significant portion of the output voltage thus severely affecting the efficiency. The active clamp topology lends itself for synchronous rectification as it has signals readily available that may be used for driving a synchronous rectifier. The synchronous rectifiers are driven from the main transformer output winding as shown in Figure 11. This configuration is known as self-driven synchronous rectification (SD−SR). The voltage of the transformer output when the main switch is on (VFW) and off (VREC) are given by Equations 21 and 22. Equation 20 is an approximation and assumes the magnetizing current reverse directions halfway during the off time. It can be observed that equations 12 and 20 are very similar. The main difference is the ripple component added by the active clamp during the reset of the transformer. Equation 20 sets the minimum capacitance to comply with the capacitor input ripple current rating. Additional capacitance may be needed to insure the system is stable over the complete operating range. The input filter is implemented using a 1.5 mH inductor with four 2.2 mF capacitors in parallel. Figure 10 shows the L−C filter output impedance and the approximated converter input impedance over frequency obtained with the Design Tool. As the capacitor ESR changes over frequency, the ESR at the filter corner frequency is used for the analysis. V VFW + in N 50 VREC + 40 IMPEDANCE (dBW) 30 10 0 −10 N Input Filter −20 −30 −40 −50 0.1 1 10 FREQUENCY (kHz) 100 1000 Figure 10. Input Filter Output Impedance and Approximated Converter Input Impedance Lout TX1 + Vin (eq. 22) Before SD−SR can be used, the voltage at the transformer output needs to be calculated to ensure it is high enough to turn on the rectification MOSFETs but it does not exceed its maximum gate voltage. Using the NCP1562 Design Tool the range for VFW and VREC is calculated between 4.7 V and 12.7 V as shown in Figure 12. A MOSFET characterized with a 4.5 V gate voltage should be used to ensure the rectification MOSFET turn on. Converter 20 Vclamp (eq. 21) − + − VFW VREC − NCP1562 OUT1 QFW + Qmain QREC Cclamp OUT2 Qclamp CC Figure 11. Synchronous Rectification Circuit http://onsemi.com 8 Cout NCP1562−100WGEVB QREC and QFW are given by Equations 23 and 24, respectively. 14 STRESS VOLTAGE (V) 12 Pcond(REC) + Iout(rms) 2 @ D @ RDS(on) VFW 10 Pcond(FW) + Iout(rms) 2 @ (1 * D) @ RDS(on) (eq. 24) 8 The gate charge losses of the driver and body diode conduction losses are given by 25 and 26, respectively. VREC 6 4 2 0 (eq. 23) 30 40 50 60 70 Pdriver + f SW @ QG(TOT) @ Vgate (eq. 25) Pbd + Vbd @ Iout @ f SW @ tdead (eq. 26) Figure 13 shows the synchronous rectification losses calculated by the NCP1562 Design Tool. 80 4.0 Vin, INPUT VOLTAGE (V) 3.5 If the secondary voltage is not compatible with the MOSFET gate voltage, a few alternatives are available as listed below: 1. Use a lower transformer turns ratio. 2. Add an extra winding or use a stacked winding on the transformer secondary. 3. Drive the MOSFETs from the primary side (OUT1 and OUT2) using a gate drive transformer. 3.0 POWER (W) Figure 12. Synchronous Rectifier Gate Voltage Freewheeling MOSFET 2.5 2.0 Rectification MOSFET 1.5 1.0 0.5 The selection of the rectification MOSFETs in an SD−SR configuration is not trivial. Both conduction and switching losses should be optimized for the best overall efficiency. Contrary to traditional belief, the lowest RDS(on) MOSFET will not always provide the best overall efficiency. The incremental reduction in conduction losses of a low RDS(on) MOSFET may be overcome by an increase in switching losses. ON Semiconductor’s NTMFS4835N is selected for both QREC and QFW MOSFETs. It is a 30 V MOSFET with a maximum RDS(on) of 5.0 mW and a maximum gate charge of 39 nC at 4.5 V. The NTMFS4835N is housed in a SO−8 Flat Lead (FL) package. The SO−8 FL is a leadless package with an exposed tab to reduce thermal resistance and parasitic inductance and capacitance. The maximum power dissipation of the SD−SR MOSFETs is calculated using Equation 14. The NTMFS4835 datasheet provides an RqJA of 55.1°C/W and a TJ(max) of 150°C. Telecom products are usually designed for a TA(max) of 50°C. Solving Equation 14, with 90% derating on TJ(max) each MOSFET can dissipate 1.54 W. If higher power dissipation is required, a heatsink can be added to the MOSFET to reduce its RqJA. The converter high output current requires multiple MOSFETs to be used in parallel due to the high conduction losses. The number of MOSFETs for QFW and QREC is determined by calculating the losses of each one and dividing it by the maximum power dissipation given by Equation 14. The maximum power dissipation of QREC occurs at low line and for QFW at high line. The conduction losses for 0.0 30 40 50 60 70 80 Vin, INPUT VOLTAGE (V) Figure 13. Synchronous Rectification Losses The full load losses for QFW and QREC are 3.6 W and 3.4 W, respectively. Two MOSFETs are used in parallel for each of QFW and QREC. However it is apparent that external cooling or a heatsink is required to deliver full power. Alternatively, a larger number of MOSFETs in parallel could have been used. Almost no ringing is observed on the drain of the synchronous rectifiers. This is due to the minimum parasitic inductance and capacitance of the SO−8 FL package and the tight layout of the output power stage. No R−C snubbers are required across the synchronous rectifiers. Optocoupler and VEA Circuit The output voltage is regulated by comparing the error signal in the VEA pin to the feedforward (FF) ramp. An optocoupler transmits the error signal across the isolation boundary. Typically, optocouplers introduce a pole around 10 kHz. This pole limits the system bandwidth and complicates the frequency compensation of the converter as it occurs at the desired crossover frequency range. The pole is due to the impedance and capacitance at the collector terminal. Fortunately, there are a few tricks to move the optocoupler pole to a higher frequency and increase the system bandwidth. First, a cascode stage using a bipolar transistor (Q1) is placed between the optocoupler pull up resistor (REA) and the collector of the optocoupler as shown in Figure 14. The http://onsemi.com 9 NCP1562−100WGEVB collector impedance is now the impedance looking into the emitter of the bipolar transistor which is very small. The optocoupler pole is effectively moved to a higher frequency (>50 kHz). stable and has adequate transient response, the closed loop response should have a minimum phase margin of 45° under all line and load conditions. This is accomplished by shaping the open loop response using an error amplifier. The first step is to determine the open loop frequency response of the converter. An active clamp forward converter operating in voltage mode has two poles, p1,2(LC), due to the output LC filter and one zero, zESR, due to the output capacitor series resistance. In addition it has two complex zeros introduced by the active clamp network. The complex zeros are not shown due to their great complexity. The complex zeros happen before the system poles P1,2(AC). The system crossover frequency should be selected below P1,2(AC) to avoid the complex poles. Equations 28 through 30 show the system poles and zeros. VREF VEA REA Q1 R11 − + R6 Vref(EA) R13 Feedback Figure 14. High Bandwidth Optocoupler Biasing Configuration Second, the optocoupler diode is driven with an ideal current source. This arrangement works very well during transients and power up. As the diode is driven with a current instead of a voltage source, the error amplifier output does not have to swing too far during a transient. This arrangement is also immune to supply voltage variations. The optocoupler gain changes with its bias current, Iopto. It is not uncommon for an optocoupler to have a gain variation of 10 or more over the operating current range. As the optocoupler bias current changes from low to high line, it presents a design challenge. In addition, optocoupler performance changes with age and temperature. A low gain optocoupler is preferred to minimize its impact in the overall system gain. NEC’s PS2703−1−M optocoupler is used in this design. The optocoupler manufacturer recommends biasing the optocoupler at 1 mA. Our optocoupler is designed to operate at 1 mA at nominal input voltage (48 V). However, the bias current at low or high line will be slightly different. Equation 27 relates the duty ratio to optocoupler bias current, REA + VREF * (3 @ D ) 0.9) Iopto 1 Ǹ 2p Lout @ Cout (eq. 28) 1 2p @ RESR @ Cout (eq. 29) P1, 2(LC) + ZESR + P1, 2(AC) + (1 * D) (eq. 30) 2p ǸLMAG @ Cclamp The ESR of the output capacitors is very low ( 200 − p1,2(AC) 41.1 − GMOD − 1.86 GOPTO − 18.7 http://onsemi.com 10 0 40 −20 30 −40 20 −60 10 −80 0 −100 −10 −120 −20 −140 −30 −160 −40 −50 −180 0.01 0.1 1 10 100 GEA + 20 @ log ǒRR20 Ǔ 21 (eq. 36) The system open loop gain in Figure 15 Simulated Open Loop Frequency Response at the desired crossover frequency of 15 kHz is 5 dB. Therefore, the EA gain is set at −8.77 dB to achieve a gain of 0 dB at approximately 15 kHz. Resistors R20 and R21 are set at 5.9 kW and 16.2 kW, respectively. One compensation zero is placed before and one after p1,2(LC) at 482 Hz and 9.8 kHz, respectively. Capacitors C25 and C29 are set at 0.056 mF and 1,000 pF, respectively. The second pole is set at a 457 kHz setting R30 at 348 W. The simulated frequency response is shown in Figure 17. The simulated crossover frequency is around 15 kHz with a 60° phase margin. −200 FREQUENCY (kHz) Figure 15. Simulated Open Loop Frequency Response 180 40 Measured Phase 30 MAGNITUDE (dB) The maximum achievable bandwidth is limited by p1,2(AC) at low line. Therefore, the system crossover frequency, fCO, should be set lower than p1,2(AC). In this design, fCO is set at 20 kHz. Several EA configurations are available. A type II error amplifier, as the one shown in Figure 16, is used in this design as it provides adequate phase margin. A type II error amplifier has 2 poles and 2 zeros. The first pole is at the origin. The frequency of the remaining pole and zeros are calculated using Equations 33 through 35. 20 90 10 Measured Gain 45 0 0 −10 −45 −20 −90 −30 −135 −40 Vout 135 PHASE (°) 50 PHASE (°) MAGNITUDE (dB) NCP1562−100WGEVB 0.1 1 10 100 −180 FREQUENCY (kHz) Figure 17. Simulated System Frequency Response R19 R20 C25 Error Amplifier Voltage Reference R30 The error amplifier reference voltage (Vref(EA)) is generated using ON Semiconductor’s TLV431 as shown in Figure 18. D5 R21 C29 EA + EA Vref(EA) B (eq. 33) 1 fz1 + 2p @ C29 @ R21 (eq. 34) 1 fz2 + 2p @ C25 @ R20 (eq. 35) C9 R7 C6 IK TLV431 Ibias R27 C5 1.25 V R28 − + D6 R12 + 1 2p @ C29 @ (R21 ø R30) D3 A Figure 16. Type II Error Amplifier fp2 + − + − Vref(EA) − Figure 18. Error Amplifier Reference Voltage The error amplifier reference voltage is set at 3.3 V using R27 and R28. This eliminates the need of a bias resistor between the EA inverting input and ground. The voltage across R28 is regulated at 1.25 V by the TLV431. Assuming a bias current (Ibias) of 500 mA, R28 is set at 2.49 kW. Resistor R27 is set by calculating the difference between Vref(EA) and 1.25 V and dividing it by Resistor R19 is added to provide an injection point to measure the frequency response. A small resistor value (10 to 20 W) is used for R19 so it does not affect the dc operating point. Diode D5 clamps the output of the error amplifier during startup to improve the transient response. The selection of the compensation network components begins by determining the error amplifier gain, GEA, using Equation 36. http://onsemi.com 11 NCP1562−100WGEVB avoid distortion of the current sense signal. The value of R10 is set at 100 W and C11 is set at 100 pF. The complete current sense circuit is shown in Figure 19. Ibias. It is set at 4.22 kW. Capacitor C5 provides noise immunity for Vref(EA). It is set at 1,000 pF. The maximum voltage of either A or B provides the voltage supply for the EA and the TLV431. Signals A and B are taken from the dot (A) and non-dot (B) ends of the secondary winding of the main transformer. The NCP1562 Design Tool shows a minimum voltage of approximately 7 V. The maximum value of R7 is calculated using Equation 37. IK ) Ibias VCS (eq. 37) Rsense Figure 19. Current Sense Circuit The converter enters the cycle skip current mode if a continuous over current condition is exists. Once a current limit event is detected, a 90 mA current source begins charging the capacitor on the CSKIP pin. If the capacitor charges to 3 V, the converter enters a soft stop mode. A cycle skip period of 330 ms is set with a 0.01 mF capacitor. Under and Over Voltage Detector The NCP1562 facilitates design by incorporating tightly controlled undervoltage (UV) detector. In addition, it incorporates an independent overvoltage (OV) detector in the same pin. The pin is biased using a resistor divider as shown in Figure 20. Current Limit Circuit This converter is designed to deliver 100 W under normal operating conditions. However, under a fault condition the current may increase significantly and permanently damage the system. The NCP1562 incorporates an extremely accurate current limit circuit to protect the system while a current limit condition is present. A low propagation delay combined with an extremely accurate current limit threshold limit the maximum power delivered under a current limit condition. This allows the designer to have a robust and safe system without excessive over design. The NCP1562 has two overcurrent protection methods, cycle by cycle and cycle skip. In cycle by cycle, the conduction period ends once the current limit threshold is reached. Cycle skip is enabled if the converter is in a continuous current limit for a user programmed time. While in cycle skip mode, the converter power downs and restart after a user determined time. The NCP1562A is used in this design. It has a current limit voltage threshold, VILIM, of 0.2 V. A current sense resistor is used to reduce system cost and complexity. It is calculated using 38. VILIM IP(PK) C11 − where, Vf is the diode drop of D3 or D6 and IK is the TLV431 minimum cathode current. Solving 37 with an IK of 80 mA sets the maximum value of R7 at 10.9 kW. The value of R7 is set at 4.22 kW. The switching noise at nodes A and B is attenuated by placing a small resistor (R12) in series with D3 and D6. The value of R12 is set at 49.9 W. The components of the peak detector (D3, D6, R12 and C9) are placed close to each other but away from the EA to keep noise low. A bypass capacitor (C6) is placed across the supply terminals of the EA. Both C9 and C6 are set at 0.1 mF. Rsense + R10 To CS Pin + R7 + V(A or B) * 0.7 V Main Switch Vin R1 To UVOV Pin C16 R4 Figure 20. UVOV Bias Circuit The minimum operating voltage of the system is controlled by comparing the voltage on the UVOV pin to a 2 V reference, VOV. The system turn on threshold, Vin(UV), is determined by the ratio of the resistor divider on the UV pin as shown in Equation 39. Vin(UV) + VUV @ (R1 ) R4) R4 (eq. 39) The maximum operating voltage, Vin(OV), is controlled by comparing the voltage on the UVOV pin to an internal 3 V reference, VOV. An internal current source (Ioffset(UVOV)) sinks 50 mA into the UVOV pin once the UVOV voltage exceeds 2.5 V. The voltage offset introduced by this current source allows independent adjustment of Vin(UV) and Vin(OV) (patent pending). The OV threshold depends on the ratio of the resistor divider as well as the absolute value of R1 as shown in Equation 40. (eq. 38) Using IP(PK) calculated earlier, Rsense is calculated at 34 mW. The value of the sense resistor is set at 33 mW. The NCP1562 incorporates a 75 ns leading edge blanking circuit to mask the leading edge spike of the current signal. The evaluation board also provides external blanking time using a simple RC low pass filter comprised of R10 and C11. The cutoff frequency of the low pass filter is selected several orders of magnitude greater than the operating frequency to Vin(OV) + VOV @ http://onsemi.com 12 (R1 ) R4) R4 ) ( Ioffset(UVOV) @ R1 ) (eq. 40) NCP1562−100WGEVB A small capacitor of at least 1,000 pF is required on the UVOV to provide noise immunity and filter turn ON and turn OFF transitions on the input line. The Design Tool suggests using an R1 of 504 kW and an R2 of 32.4 kW. Used values are 523 W and 32.4 kW for R1 and R4, respectively. The calculated operating voltage range is between 35.31 V and 80.15 V with Vin increasing and between 32.52 V and 75 V with Vin decreasing. CFF + IFF @ V * sec(max) 3V (eq. 41) Our transformer has a V-sec(max) of 62.4 V-msec. Selecting an arbitrarily IFF of 1.75 mA, the Design Tool suggest values of 43.4 kW and 479 pF for RFF and CFF, respectively. Final values are 45.3 kW for RFF and 470 pF for CFF. As duty ratio control is very important, the tolerances for RFF and CFF are set at 1% and 5%, respectively. Maximum Duty Ratio As shown in Figure 5, the drain voltage of the main switch of an active clamp converter increases rapidly at low input voltages. Accurate duty ratio control allows the designer to fully optimize the system without risking exceeding the voltage rating of the main switch. The NCP1562 incorporates an extremely accurate duty ratio control. It is trimmed during manufacturing to achieve better that ±5% accuracy over the complete temperature and process range. Duty ratio and frequency are controlled using a timing resistor, RT, and capacitor, CT, on the RTCT pin. The resistor is connected between the VREF and RTCT pins and the capacitor is connected between the RTCT and GND pins. The converter is designed to operate at 350 kHz with a maximum duty ratio of 63%. Taking into account the overlap time delay, the required oscillator duty ratio is 66%. The Design Tool suggests initial values for RT and CT of 14.5 and 320 pF, respectively. Final values of RT and CT are set at 15 kW and 300 pF. Soft−Start Soft−start slowly starts the converter and reduces stress during power up. The NCP1562 implements soft−start by comparing the voltage in the SS pin to the FF Ramp. Soft−start is adjusted by placing an external capacitor, CSS, between the SS pin and ground. The capacitor is charged with a constant 10 mA current source. The peak voltage of the FF Ramp is 3 V. Therefore, soft−start ends once the SS voltage exceeds the FF Ramp or it exceeds 3 V. Under steady state conditions the SS capacitor is charged to 3.8 V. Soft−Stop The clamp capacitor in a forward topology needs to be discharged while powering down the converter. If the capacitor remains charged after power down it may damage the converter. First, the resonant tank between Cclamp and LMAG used for ZVS during normal operation will continue to resonate after power down as long as energy is stored in the capacitor. Second, a long reset time is applied to the transformer during power up as duty ratio slowly increases from 0%. If the capacitor is charged during power up, the maximum V-sec of the transformer may be exceeded. This will push the transformer far into the third quadrant of the B−H curve, possibly saturating the transformer. The NCP1562 solves these problems by using a novel approach called soft−stop. Soft−stop reduces the duty ratio until it reaches 0% prior to turn off. Duty ratio is reduced by discharging the capacitor on the SS pin using a 90 mA current source. The voltage of the clamp capacitor is given by Equation 42. It can be observed that the clamp capacitor voltage will approach zero as duty ratio approaches zero. Volt Second Limit and Feedforward A forward converter regulates the output voltage by maintain a constant Volt-second (V-sec) product. If the maximum V-sec product is exceeded, the transformer will saturate and possibly damage to the system. Therefore, it is critical to accurately control the V-sec product in a forward converter. The NCP1562 implements V-sec limit by generating a Feedforward (FF) Ramp proportional to Vin and comparing it to a 3 V reference. The ramp is generated by charging an external capacitor (CFF) with a resistor (RFF) from Vin. Feedforward is achieved by changing the slope of the FF Ramp while maintaining a constant error voltage. Feedforward reduces line voltage variations and provides a frequency gain independent of Vin making the system easier to compensate. The peak voltage of the ramp is set below 3 V under normal operating conditions. The margin allows the converter to quickly respond during a transient. The FF components are calculated starting with the desired maximum FF charge current, IFF. Given IFF, RFF is calculated by dividing the maximum input voltage by IFF. The FF capacitor is calculated using Equation 41. V @D Vclamp + in 1*D (eq. 42) Empirically it is determined that a 0.1 mF is sufficient to discharge the clamp capacitor under all operating conditions. The worst case condition for soft−stop is light load at high line. During this condition, VEA is at its lowest making the achievable soft−stop time a minimum for a given capacitance. Figure 21 shows the drain of the main switch during power down at high line and no load. As expected, soft−stop provides a controlled turn off without any unwanted oscillations on the drain voltage. http://onsemi.com 13 NCP1562−100WGEVB Figure 21. Converter Power Down using Soft−Stop The same capacitor is used for soft−start and soft−stop. The minimum soft−start time is determined by the required soft−stop period. A soft−start to soft−stop ratio of 1/10 is set with the internal charge and discharge currents. If a different ratio is required, a resistor can be placed between the VREF and SS pins to increase the SS charge current. Figure 22. Layer 1 (Top) Board Layout The converter is built to validate the design using a 4 layer FR4, double sided board. The converter meets the industry standard half brick (2.3 in. × 2.4 in.) footprint and pinout. Power components are placed on the top layer (primary) and control components on the bottom (secondary) layer. The board is constructed using 2 oz copper. The top and bottom layers are plated to 3 oz. to improve power dissipation. The two inner layers are used for ground and signal routing. During the layout process care was taken to: 1. Minimize trace length, especially for high current loops. 2. Use wide traces for high current connections. 3. Use a single ground connection. 4. Keep sensitive nodes away from noisy nodes such as drain of power switches. 5. Place decoupling capacitors close to ICs. 6. Sense output voltage at the output terminal to improve load regulation. Figure 23. Inner Layer 2 The layers are numbered 1 through 4 from top to bottom and are shown in Figure 22 through Figure 25. The top and bottom layers show the component location. http://onsemi.com 14 NCP1562−100WGEVB Design Validation The top and bottom view of the board are shown in Figure 26 and Figure 27, respectively. Figure 24. Inner Layer 3 Figure 26. NCP1562 Evaluation Board Top View Figure 27. NCP1562 Evaluation Board Bottom View The circuit schematic is shown in Figure 28 and the bill of material is listed in Table 3. Figure 25. Layer 4 (Bottom) The layout files may be available. Please contact your sales representative for availability. http://onsemi.com 15 J5 J2 J1 Pi n4 Pi n1 Pi n2 1 1 1 L1 1.5uH 2.2 2.2 C30 open 32. 4k R4 R1 523k C2 C1 C12 300p R9 15k 0.01 C16 2.2 C3 Vref 2.2 C4 470p C24 R3 44.2k R8 32.4k Vref CS 0.1 C8 8 7 6 5 4 3 2 1 22 C7 47 Vea SS tD CSKIP OUT2 PGND OUT1 Vaux VAUX NCP1562A VREF SYNC RTCT GND CS FF UVOV Vin U1 0.1 C23 47 C22 9 10 11 12 13 14 15 16 4.75 D1 1 2 R15 C28 0.1 C13 0.01 R5 44.2k OUT2 0. 01 R6 10k 1 R16 10k R11 4.22k D4 7 4 2 MMS D 9 1 4 R2 R10 100 X1 1 D2 C11 100p C1 4 M M SD 914 2 1 CS MBRM120E 1 C1 0 2 4 3 3 1 MMS D9 14 1 2 Q1 R17 10k 4 X2 0.01 C26 6T 4T TX1 51665 35m SU D 25N 15-52 C31 D7 2 4 1T 9 8 1 Vref U2 R18 2.49k 220 0p C2 7 X4 X3 U4B 7 5 6 7 8 5 6 7 8 1 2 3 5 6 LM258 + − SEC_PWR2 R29 2.0 Q2 BC807 R14 750 R25 10k X5 4 SE C _ PW R 1 1p25 R2 4 10k NTMFS4709N 1 2 3 NTMFS4709N R23 2.0 4 4 1 3 2 PS2703 4 2. 2 C1 5 1 SEC_PWR2 SEC _PW R 1 2 D3 1 R12 D6 1 24.9k R26 MSD914 2 MSD914 0.1 C9 49.9 U4A 1 R20 7.5k LM258 1.5u 1 348 X6 4 4 L2 R13 N T M F S4709N L3 68 0uH 5 6 7 8 1 2 3 3 4 8 I R F 6217 BC 817-25 1 2 1 2 3 5 6 7 8 N T M F S4709N 5 6 7 8 1 2 3 2 3 D5 1 0.1 C6 + − MSD914 2 TL V 431 U3 R7 4.02k 3 2 47 47 C25 0.056 C18 C17 150 C19 3 16 4 http://onsemi.com 8 Figure 28. Circuit Schematic 5 VA U X 4 150 C21 R28 2.49k R27 4.22k 1000p C29 150 C20 J3 1 J4 Pi n9 1 1p2 5 Pi n5 C5 10 00p R22 open R2 1 16 . 2k 348 R30 10 R19 3p3Vout NCP1562−100WGEVB NCP1562−100WGEVB Table 3. BILL OF MATERIAL FOR THE NCP1562 EVALUATION BOARD Designator Qty. Description Value Tolerance Footprint Manufacturer Manufacturer Part Number Substitution Allowed Lead Free R1 1 Resistor 523 kW 1% 0805 Vishay CRCW08055523KFKEA Yes Yes R2 1 Resistor 0.035 W 1% Custom IRC Electronics LRC−LRF3WLF−01−R033−F No Yes R3 1 Resistor 45.3 kW 1% 1206 Vishay CRCW120645K3FKEA Yes Yes R4, R8 2 Resistor 32.4 kW 1% 0805 Vishay CRCW080532K4FKEA Yes Yes R5 1 Resistor 44.2 kW 1% 0805 Vishay CRCW080544K2FKEA Yes Yes R9 1 Resistor 15 kW 1% 0805 Vishay CRCW080515K0FKEA Yes Yes R10 1 Resistor 100 W 1% 0805 Vishay CRCW0805100RFKEA Yes Yes R7, R11, R27 3 Resistor 4.22 kW 1% 0805 Vishay CRCW08054K22FKEA Yes Yes R12 1 Resistor 49.9 W 1% 0805 Vishay CRCW080549R9FKEA Yes Yes R13, R30 2 Resistor 348 W 1% 0805 Vishay CRCW0805348RFKEA Yes Yes R14 1 Resistor 953 W 1% 0805 Vishay CRCW0805953RFKEA Yes Yes R15 1 Resistor 4.75 W 1% 1206 Vishay CRCW12064R75RKEA Yes Yes R6, R16, R17, R24, R25 5 Resistor 10 kW 1% 0805 Vishay CRCW080510K0FKEA Yes Yes R18 1 Resistor 3.01 kW 1% 0805 Vishay CRCW08053K01FKEA Yes Yes R19 1 Resistor 10 W 1% 1206 Vishay CRCW120610R0FKEA Yes Yes R20 1 Resistor 5.9 kW 1% 0805 Vishay CRCW08055K90FKEA Yes Yes R21 1 Resistor 16.2 kW 1% 0805 Vishay CRCW080516K2FKEA Yes Yes R22 1 Resistor Open 1% 0805 Vishay CRCW0805… Yes Yes R23, R29 2 Resistor 2.00 W 1% 1206 Vishay CRCW12062R00FKEA Yes Yes R26 1 Resistor 24.9 kW 1% 0805 Vishay CRCW080524K9FKEA Yes Yes R28 1 Resistor 2.49 kW 1% 0805 Vishay CRCW08052K49FKEA Yes Yes L1 1 Inductor 1.5 mH N/A Custom Coilcraft DS3316P−152MLB Yes Yes L2 1 Inductor 1.5 mH N/A Custom Payton 51666 No Yes L3 1 Inductor 1,000 mH N/A Custom Coilcraft DO1606T−105MLB Yes Yes C1−C4 4 Capacitor 2.2 mF, 100 V 20% 4532 TDK C4532X7R2A225MT No Yes C5, C29 2 Capacitor 1,000 pF, 50 V 5% 0805 Vishay VJ0805A102JXAAT Yes Yes C6, C8, C9, C28 4 Capacitor 100 nF, 50 V 10% 0805 Vishay VJ0805Y104KXAAT Yes Yes C7 1 Capacitor 22 mF, 16 V 20% 4532 TDK C4532X5R1C226M Yes Yes C10 1 Capacitor 1 mF, 25 V 20% 3216 TDK C3216X7R1E105M Yes Yes C11 1 Capacitor 100 pF, 50 V 10% 0805 Vishay VJ0805A101KXAAT Yes Yes C12 1 Capacitor 300 pF, 50 V 5% 0805 Vishay VJ0805A301JXAAT Yes Yes C13, C16 2 Capacitor 10 nF, 50 V 10% 0805 Vishay VJ0805Y103KXAAT Yes Yes C14 1 Capacitor 18 nF, 50 V 10% 0805 Vishay VJ0805Y183KXAAT Yes Yes C15 1 Capacitor 2.2 mF, 10 V 10% 2012 TDK C2012X5R1A225K Yes Yes C17, C18 2 Capacitor 47 mF, 6.3 V 20% 3225 TDK C3225X5R0J476M Yes Yes C19−C21 3 Capacitor 150 mF, 6.3 V 20% Custom Kemet T520B157M006ATE045 No Yes C22, C31 2 Capacitor 47 mF, 16 V 10% Custom Vishay 595D476X9016C4T No Yes C23 1 Capacitor 0.1 mF, 100 V 10% 3216 TDK C3216X7R2A104K Yes Yes C24 1 Capacitor 470 pF, 50 V 5% 0805 Vishay VJ0805A471JXAAT Yes Yes C25 1 Capacitor 56 nF, 25 V 10% 0805 Vishay VJ0805Y563KXXAT Yes Yes C26 1 Capacitor 10 nF, 630 V 20% 3216 TDK C3216X7R2J103M Yes Yes C27 1 Capacitor 2,200 pF, 2 kV 10% 4532 TDK C4532X7R3D222K Yes Yes C30 1 Capacitor 27 pF, 50 V 5% 0805 Vishay VJ0805A270JXAAT Yes Yes D1 1 Schottky Diode 20 V, 1 A N/A POWERMI TE ON Semiconductor MBRM120ET1G No Yes D2−D7 6 Diode 100 V N/A SOD123 ON Semiconductor MMSD914T1G No Yes J1, J2, J5 3 Pins N/A N/A 40 mils Mill−Max 3103−2−00−21−00−00−08−0 Yes Yes http://onsemi.com 17 NCP1562−100WGEVB Table 3. BILL OF MATERIAL FOR THE NCP1562 EVALUATION BOARD (continued) Description Value Tolerance Footprint Manufacturer Manufacturer Part Number Substitution Allowed Lead Free 2 Pins N/A N/A 80 mils Mill−Max 3231−2−00−34−00−00−08−0 Yes Yes 1 Transformer N/A N/A N/A Payton 51665 No Yes U1 1 PWM Controller N/A N/A TSSOP−16 ON Semiconductor NCP1562ADBR2G No Yes U2 1 Optocoupler N/A N/A 4−SOP NEC PS2703−1−M−A No Yes U3 1 Shunt Reference N/A N/A SOT−23 ON Semiconductor TLV431ASNT1G No Yes U4 1 Op Amp N/A N/A SOIC−8 ON Semiconductor LM258DG Yes Yes X1 1 MOSFET 150 V, 21 A N/A DPAK Vishay SUD25N15−52 Yes Yes Designator Qty. J3, J4 TX1 X2 1 MOSFET 150 V, 700 mA N/A SO8 IR IRF6217PBF Yes Yes X3−X6 4 MOSFET 30 V, 104 A N/A SO8−FL ON Semiconductor NTMFS4835NT1G No Yes Q1 1 NPN Transistor BC817−25 N/A SOT−23−3 ON Semiconductor BC817−25LT1G No Yes Q2 1 PNP Bipolar Transistor BC807−25 N/A SOT−23−3 ON Semiconductor BC807−25LT1G No Yes 40 180 30 135 MAGNITUDE (dB) The open loop response is measured injecting an AC signal across R19 using a network analyzer and an isolation transformer as shown in Figure 29. The open loop response is the ratio of B to A. 10 −45 −10 + Vout − Simulated Gain −90 −135 0.1 1 10 100 −180 FREQUENCY (kHz) Figure 30. Measured and Calculated Open Loop Frequency Responses 1:1 Z1 Measured Phase −30 R19 To Error Amplifier Inverting Input 0 0 −40 out 45 Measured Gain −20 Lout To Converter C Simulated Phase 90 20 PHASE (°) The converter performance is evaluated and compared to our original goals. The evaluation criteria includes: 1. Open loop frequency response. 2. Efficiency. 3. Line and load regulation. 4. Step load response. 5. Output voltage ripple. The full load efficiency of the converter is measured above 91% across the complete input voltage range. Figure 31 shows the efficiency vs output current at 36 V, 48 V and 72 V. The peak efficiency is measured at 92.8%. REF A Network Analyzer B Rbias 95 94 Vin = 48 V 93 EFFICIENCY (%) Figure 29. Open Loop Frequency Response Measurement Setup The measured and calculated open loop responses are shown in Figure 30. The measured phase margin is 57_ and the crossover frequency is 16.7 kHz. A good correlation is observed between the simulated and calculated responses up to around 30 kHz. The simulated tool does not show the complex zeros and P1,2(AC) of the active clamp. 92 Vin = 76 V 91 90 Vin = 36 V 89 88 87 86 85 0 5 10 15 20 25 Iout, OUTPUT CURRENT (A) Figure 31. Efficiency vs. Output Current http://onsemi.com 18 30 NCP1562−100WGEVB Thermal Performance Line and load regulation are calculated using 43 and 44, respectively. DVout Reg(line) + DVin Reg(load) + Vout(no load) * Vout(full load) Vout(no load) This evaluation board is designed to operate with airflow as in a telecom system. Airflow is required if the converter operates above 50% of its rated power. Optimum cooling is achieved when air flows from the output side to the input side. The thermal performance of the board is evaluated using an infrared camera. Figure 34 through Figure 37 show several images of the board at full load. Images include top and bottom layers at low and high line. All images were taken with airflow from the output side to the input side. (eq. 43) (eq. 44) Line regulation is measured below 0.01% and load regulation is measured below 0.23%. The dynamic response of the converter at 48 V is evaluated stepping the load current from 50% to 75% and from 75% to 50% of Iout(max). The step load response is shown in Figure 32. Air Flow Figure 34. Thermal Image of the Top of the Board at Low Line and Full Load Condition Figure 32. Output Voltage Response to a Step Load from 22.5 A to 15 A. The output voltage ripple is measured at 16 mV at high line and full load. It is significantly below the 50 mV target. The output voltage ripple waveform at high line and full load is shown in Figure 33. Air Flow Figure 35. Thermal Image of the Bottom of the Board at Low Line and Full Load Condition Figure 33. Output Voltage Ripple at High Line and Full Load Air Flow Figure 36. Thermal Image of the Top of the Board at High Line and Full Load Condition http://onsemi.com 19 NCP1562−100WGEVB The NCP1562 evaluation board thermal performance can be optimized by using heatsinks, integrating magnetic components on the board, using additional layers and placing the synchronous rectifiers farther away from each other. Please keep in mind that this is a evaluation board to showcase the flexibility of the NCP1562. A commercially available dc−dc converter will use advanced packaging and manufacturing techniques to maximize power dissipation of critical components. Summary Air Flow A 100 W converter is designed and built using the active clamp forward topology. The converter is implemented using the NCP1562. The full load efficiency is measured above 91% over the complete operating range. The converter provides excellent transient response. Output voltage ripple is measured at 16 mV. Phase margin and crossover frequency are measured at 57_ and 16.7 kHz, respectively. This evaluation board is designed to demonstrate the features and flexibility of the NCP1562. This design should not be used for production or manufacturing purposes. Figure 37. Thermal Image of the Bottom of the Board at High Line and Full Load Condition Most of the losses on the board are on the main switch and synchronous rectifiers. The synchronous rectifier losses are dominated by conduction losses. At low line, QFW has the higher duty ratio and thus the higher power dissipation as shown in Figure 34. At high line, QREC has the higher duty ratio and thus the higher power dissipation as shown in Figure 36. TEST PROCEDURE Scope Electronic Load CH1 Power Supply IOUT − Multimeter 1 (MM1) − CH2 VOUT+ VIN+ + + NCP1562 Evaluation Board VIN− VOUT− + Multimeter 2 (MM2) + − Multimeter 3 (MM3) − Figure 38. Test Setup Required Equipment Test Procedure • Power Supply: Maximum voltage rating of 85 V and • • • 1. Configure Multimeter 1 (MM1) for measuring current. Connect Power Supply (+) terminal to MM1 current measurement terminal. 2. Connect MM1 ground terminal to evaluation board (Vin+) terminal. 3. Connect Power Supply (-) terminal to evaluation board (Vin−) terminal. maximum current rating of 4 A 3 Multimeters: Maximum current rating of 10 A and maximum voltage rating of 100 V Electronic Load: with current display and maximum current capability of 35 A Oscilloscope http://onsemi.com 20 NCP1562−100WGEVB 4. Configure Multimeter 2 (MM2) for measuring voltage. Connect MM2 voltage measurement terminal to evaluation board (Vout+) terminal. Connect MM2 ground terminal to evaluation board (Vout−) terminal. 5. Verify MM2 terminals are connected to evaluation board terminals. 6. Connect electronic load (EL) to evaluation board output. Connect EL (+) terminal to evaluation board (Vout+) terminal. Connect EL (-) terminal to evaluation board (Vout−) terminal. Set load current (Iout) to 0 A. 7. Configure Multimeter 3 (MM3) for measuring voltage. Connect MM3 voltage measurement terminal to evaluation board (Vout+) terminal. Connect MM3 ground terminal to evaluation board (Vout−) terminal. 8. Verify MM3 terminals are connected to the evaluation board terminals and not electronic load terminals. Otherwise, the voltage drop on the EL terminals will affect your measurements. 9. The complete test setup should be similar to Figure 38. 10. Slowly ramp the input voltage (Vin) to 10 V. If input current exceeds 30 mA, verify the setup. If connection is correct, stop testing. Board needs to be repaired. 11. Increase the input voltage to 25 V. The NCP1562 start-up circuit should be operating. Probe terminal 16 of U1. The waveform should look similar to Figure 39. If not, stop testing. Board needs to be repaired. 12. Increase the input voltage to 36 V. The evaluation board output should be between 3.135 V and 3.465 V. If not, stop testing. Board needs to be repaired. 13. Measure and collect input current (Iin) and voltage, as well as output current and voltage (Vout). Increase load current in steps of 10 A. Figure 39. Start-up Circuit Waveform 14. Calculate efficiency (h), load (REGload) and line regulation (REGline) using Equations 45, 46 and 47. h+ REG load + REG line + V out V in I out I in 100 V out(@noload) * V out(@loaded) Ť V out(@noload) Ť V out(@Vin1) * V out(@Vin2) V in1 * V in2 (eq. 45) 100 100 (eq. 46) (eq. 47) 15. Set load current to 0 A. 16. Repeat steps 13, 14 and 15 for input voltages of 48 V and 76 V. 17. Minimum Efficiency should not drop below 90% under all load and line conditions. 18. Load Regulation should not exceed 1% under all load and line conditions. 19. Line Regulation should not exceed 0.1% under all load and line conditions. http://onsemi.com 21 NCP1562−100WGEVB REFERENCES 5. Dhaval Dalal and Larry Wofford, “Novel Control IC for Single Ended Active−Clamp Converters,” in HFPC’95 Conf. Proc., pp. 136−146, 1995. 6. G. Stojcic, F. Lee and S. Hiti, “Small−Signal Characterization of Active Clamp PWM Converters,” in VPEC Seminar Conf. Proc., pp. 237−245, 1995. 1. Pressman, Abraham I. Switching Power Supply Design. 2nd ed. New York, NY: MacGraw Hill. 2. Ridley, Ray. “The Evolution of Power Electronics.” Switching Power Magazine. 3. Dennis Solley, “Improving Opto−Coupler Bandwidth,” AND8271/D, www.onsemi.com. 4. High Performance Active Clamp/Reset PWM Controller Datasheet NCP1562A/D, www.onsemi.com. http://onsemi.com 22 onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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