NCP1589A

NCP1589A, NCP1589B Product Preview Low Voltage Synchronous Buck Controller The NCP1589A/B is a low cost PWM controller designed to operate from a 5 V or 12 V supply. This device is capable of producing an output voltage as low as 0.8 V. This device is capable of converting voltage from as low as 2.5 V. This 10−pin device provides an optimal level of integration to reduce size and cost of the power supply. Features include a 1.5 A gate driver design and an internally set 300 kHz or 600 kHz oscillator. In addition to the 1.5 A gate drive capability, other efficiency enhancing features of the gate driver include adaptive non−overlap circuitry. The NCP1589A/B also incorporates an externally compensated error amplifier. Protection features include programmable short circuit protection and undervoltage lockout (UVLO). Features http://onsemi.com MARKING DIAGRAMS 1589x ALYWG G = Specific Device Code x = A or B = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Device DFN10 CASE 485C 1589x A L Y W G • • • • • • • • • • • • • • • • VCC Range from 4.5 V to 13.2 V 300 kHz and 600 kHz Internal Oscillator Boost Pin Operates to 30 V Voltage Mode PWM Control Precision 0.8 V Internal Reference Adjustable Output Voltage Internal 1.5 A Gate Drivers 80% Max Duty Cycle Input Under Voltage Lockout Programmable Current Limit This is a Pb−Free Device Graphics Cards Desktop Computers Servers / Networking DSP & FPGA Power Supply DC−DC Regulator Modules (Note: Microdot may be in either location) PIN CONNECTIONS BOOT LX UG LG GND 1 2 3 4 5 (Top View) 10 9 8 7 6 PGOOD VOS FB COMP/EN VCC Applications ORDERING INFORMATION Device NCP1589AMNTWG NCP1589BMNTWG NCP1589AMNTXG NCP1589BMNTXG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. DFN10 (Pb−Free) 3000 / Tape & Reel Package Shipping† This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. © Semiconductor Components Industries, LLC, 2009 May, 2009 − Rev. P4 1 Publication Order Number: NCP1589A/D NCP1589A, NCP1589B VCC = 4.5 V − 13.2 V VBST = 4.5 V − 15 V VIN = 2.5 V − 13.2 V 3x22mF 1500mF 1mF 1500mF 2x0.22mF VCC 0.1mF COMP/EN C1 0.0015mF R2 17.08kW C2 0.007mF UG LX FB GND R4 3.878kW R1 4.12kW C3 0.014mF 1.02k R3 74.2W R9 R10 1.02k LG VOS ROCSET NTD4806 NTD4809 PGOOD BOOT 1mH 2.2 VOUT 1.65 V 2x1800mF 4.7nF GND Figure 1. Typical Application Diagram PGOOD 10 VOS 9 PGOOD MONITOR OV and UV 0.8 V (Vref) ±10% of Vref ±25% of Vref POR UVLO 6 VCC FAULT FB 8 − + 0.8 V (Vref) LATCH + − FAULT VOCP 1 3 2 BOOT UG LX + − R S PWM OUT Q + CLOCK RAMP COMP/EN 7 OSC SOFT START − + − 2V VCC 4 FAULT 5 LG GND OSC Figure 2. Detailed Block Diagram http://onsemi.com 2 NCP1589A, NCP1589B PIN FUNCTION DESCRIPTION Pin No. 1 Symbol BOOT Description Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to BOOT pin). Connect a capacitor (CBOOT) between this pin and the LX pin. Typical values for CBOOT range from 0.1 mF to 1 mF. Ensure that CBOOT is placed near the IC. Switch node pin. This is the reference for the floating top gate driver. Connect this pin to the source of the top MOSFET. Top gate MOSFET driver pin. Connect this pin to the gate of the top N−channel MOSFET. Bottom gate MOSFET driver pin. Connect this pin to the gate of the bottom N−channel MOSFET. IC ground reference. All control circuits are referenced to this pin. Supply rail for the internal circuitry. Operating supply range is 4.5 V to 13.2 V. Decouple with a 1 mF capacitor to GND. Ensure that this decoupling capacitor is placed near the IC. Compensation Pin. This is the output of the error amplifier (EA) and the non−inverting input of the PWM comparator. Use this pin in conjunction with the FB pin to compensate the voltage−control feedback loop. Pull this pin low for disable. This pin is the inverting input to the error amplifier. Use this pin in conjunction with the COMP pin to compensate the voltage−control feedback loop. Connect this pin to the output resistor divider (if used) or directly to Vout. Voltage Offset Sense Power Good output. Pulled Low if VOS is ±10% of 0.8 V Vref. 2 3 4 5 6 7 LX UG LG GND VCC COMP/EN 8 FB 9 10 VOS PGOOD ABSOLUTE MAXIMUM RATINGS Pin Name Main Supply Voltage Input Bootstrap Supply Voltage Input Symbol VCC BOOT VMAX 15 V 35 V wrt/GND 40 V < 100 ns 15 V wrt/LX 35 V 40 V for < 100 ns 30 V wrt/GND 15 V wrt/LX 40 V for < 100 ns VCC + 0.3 V 5.0 V 3.6 V 7V VMIN −0.3 V −0.3 V −0.3 V −0.3 V −5 V −10 V for < 200 ns −0.3 V wrt/LX −2 V for < 200 ns −0.3 V −5 V for < 200 ns −0.3 V −0.3 V −0.3 V Switching Node (Bootstrap Supply Return) High−Side Driver Output (Top Gate) LX UG Low−Side Driver Output (Bottom Gate) Feedback, VOS COMP/EN PGOOD LG FB, VOS COMP/EN PGOOD MAXIMUM RATINGS Rating Thermal Resistance, Junction−to−Ambient Thermal Resistance, Junction−to−Case Operating Junction Temperature Range Operating Ambient Temperature Range Storage Temperature Range Moisture Sensitivity Level Symbol RqJA RqJC TJ TA Tstg MSL Value 165 45 0 to 150 0 to 70 −55 to +150 1 Unit °C/W °C/W °C °C °C − Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. This device is ESD sensitive. Use standard ESD precautions when handling. http://onsemi.com 3 NCP1589A, NCP1589B ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 4.5 V < [BST−PHASE] < 13.2 V, 4.5 V < BST < 30 V, 0 V < PHASE < 21 V, CTG = CBG = 1.0 nF, for min/max values unless otherwise noted.) Characteristic Input Voltage Range Boost Voltage Range 13.2 V wrt LX VFB = 1.0 V, No Switching, VCC = 13.2 V VFB = 1.0 V, No Switching VCC Rising VCC Falling VCC Rising or VCC Falling (FB Tied to Comp. Measure FB Pin.) 0.7936 270 TBD Conditions Min 4.5 4.5 1.0 0.1 3.8 3.4 4.0 3.6 0.4 0.8 300 600 1.1 0 70 75 500 70 Vfb < 0.8 V Vfb > 0.8 V 2.0 2.0 −2.0 15 0.6 0.8 10 VCC = 5 V, VUG − VLX = 2.5 V 1.5 1.4 1.5 VCC = 12 V VCC = 12 V, UG−LX < 2.0 V, LG > 2.0 V VCC = 12 V, LG < 2.0 V, UG > 2.0 V 12.4 12.4 3.0 Logic Low, Sinking 4 mA Ramp VOS from 0.7 to 1.2. Monitor when PGOOD goes Low Ramp VOS from 0.8 to 1.2. Monitor when outputs disable Ramp VOS from 800 mV to 500 mV. Monitor when PGOOD goes Low Ramp VOS from 800 mV to 500 mV. Monitor when utputs stop switching Sourced from LG pin, before SS 0.65 0.5 0.88 1.0 0.72 0.6 1.0 18 18 7.0 0.4 1.0 1.2 40 0 0.1 2.0 1.0 80 80 0.8064 330 TBD Typ Max 13.2 30 8.0 100 4.2 3.8 Unit V V mA mA V V V V kHz kHz V % % ns dB mA mV mA Mhz V mA A W A W ns ns ms V V V V V Supply Current Quiescent Supply Current (NCP1589A) Boost Quiescent Current Undervoltage Lockout UVLO Threshold UVLO Threshold UVLO Hysteresis Switching Regulator VFB Feedback Voltage Oscillator Frequency (NCP1589A) Oscillator Frequency (NCP1589B) Ramp−Amplitude Voltage Minimum Duty Cycle Maximum Duty Cycle LG Minimum on Time Error Amplifier Open Loop DC Gain (Note 1) Output Source Current Output Sink Current Input Offset Voltage (Note 1) Input Bias Current Unity Gain Bandwidth (Note 1) Disable Threshold Output Source Current During Disable Gate Drivers Upper Gate Source Upper Gate Sink Lower Gate Source Lower Gate Sink UG Falling to LG Rising Delay LG Falling to UG Rising Delay Soft−Start Soft−Start time Power Good Output Voltage OVP Threshold to PGOOD Output Low OVP Threshold to Part Disable UVP Threshold to PGOOD Output Low UVP Threshold to Part Disable Overcurrent Protection OC Current Source (Note 1) 9.0 10 11 mA 1. Guaranteed by design but not tested in production. http://onsemi.com 4 NCP1589A, NCP1589B TYPICAL CHARACTERISTICS 303 VCC = 12 V FSW, FREQUENCY (kHz) 302 VCC = 5 V Vref, REFERENCE (mV) 808 806 804 802 800 798 796 794 299 0 10 20 30 40 50 60 70 792 0 20 40 60 80 301 300 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 3. Oscillator Frequency (FSW) vs. Temperature 5.3 5.0 4.7 ICC (mA) 4.4 4.1 3.8 3.5 0 539 0 NCP1589A NCP1589B OCP THRESHOLD (mV) 542 543 Figure 4. Reference Voltage (Vref) vs. Temperature 541 540 20 40 60 80 20 40 60 80 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. ICC vs. Temperature Figure 6. OCP Threshold at 55k vs. Temperature http://onsemi.com 5 NCP1589A, NCP1589B APPLICATIONS INFORMATION Over Current Protection (OCP) The NCP1589A/B monitors the voltage drop across the low side mosfet and uses this information to determine if there is excessive output current. The voltage across the low side mosfet is measured from the LX pin, and is referenced to ground. The over current measurement is timed to occur at the end of the low side mosfet conduction period, just before the bottom mosfet is turned off. If the voltage drop across the bottom mosfet exceeds the over current protection threshold, then an internal counter is incremented. If the voltage drop does not exceed the over current protection threshold, then the internal counter is reset. The NCP1589A/B will latch the over current protection fault condition only if the over current protection threshold is exceeded for four consecutive cycles. When the NCP1589A/B latches an over current protection fault, both the high side and low side mosfets are turned off. To reset the over current protection fault, the power to the VCC pin must be cycled. The over current threshold voltage can be externally, by varying the value of the ROCSET resistor. The ROCSET resistor is a resistor connected between the LG pin (low side mosfet gate) and ground. During startup, after the VCC and BOOT pins reach the under voltage lock out threshold, the NCP1589A/B will source 10 mA of current out of the LG pin. This current will flow through the ROCSET resistor and produce a voltage that is sampled and then used as the over current protection threshold voltage. For example, if ROCSET is set to 10 kW, the 10 mA of current will yield a 100 mV threshold, and if the voltage drop across the low side mosfet exceeds 100 mV at the end of its conduction period, then an over current event will be detected. If the ROCSET resistor is not present, then the over current protection threshold will max out at 640 mV. The valid range for ROCSET is 5 kW to 55 kW which yields a threshold voltage range of 50 mV to 550 mV. Internal Soft-Start the under voltage lockout threshold, or if the NCP1589A/B is disabled by having the COMP pin pulled low. Startup into a Precharged Load During a startup and soft start sequence the NCP1589A will detect a residual charge on the output capacitors and not forcefully discharge the capacitors before beginning the softstart sequence, instead, the softstart ramping of the output will begin at the voltage level of the residual charge. For example, if the NCP1589A/B is configured to provide a regulated output voltage of 2.5 V, the normal softstart sequence will ramp the output voltage from 0 to 2.5 V in 4.2 ms; however if the output capcitors already have a 1.2 V charge on them, the NCP1589A/B will not discharge the capacitors, instead the softstart sequence will begin at 1.2 V and then ramp the output to 2.5 V. Power Good The PGOOD pin is an open drain active high output pin that signals the condition of the VOS (Voltage Output Sense) pin. PGOOD is pulled low during soft start cycle, and if there is a latched over current, over voltage, or under voltage fault. If the voltage on the VOS pin is within ±10% of Vref (800 mV) then the PGOOD pin will not be pulled low. The PGOOD pin does not have an internal pull-up resistor. Overvoltage Protection If the voltage on the VOS pin exceeds the over voltage threshold the NCP1589A/B will latch an over voltage fault. During an over voltage fault the UG pin will be pulled low, and the LG pin will be high while the until the voltage on the VOS pin goes below Vref/2 (400 mV). The NCP1589A will continue drive the LG pin, LG will go high if VOS exceeds 1 V and then go low when VOS goes below 400 mV. The power to the NCP1589 must be cycled to reset the over voltage protection fault. Under Voltage Protection To prevent excess inrush current during startup, the NCP1589A/B uses a calibrated current source with an internal soft start capacitor to ramp the reference voltage from 0 to 800 mV over a period of 4 ms. The softstart ramp generator will reset if the input power supply voltages reach If the voltage on the VOS pin falls below the under voltage threshold after the soft start cycle completes, then the NCP1589A/B will latch an under voltage fault. During an under voltage fault, both the UG and LG pins will be pulled low. The power to the NCP1589 must be cycled to reset the under voltage protection fault. http://onsemi.com 6 NCP1589A, NCP1589B 4.0 V 3.6 V VCC Internal UVLO Fault 1.45 V COMP −0.7 V 700 mV LG 50 mV OCP Programmable UG VOUT 0.8 V FB PGOOD POR UVLO SS NORMAL Figure 7. Typical Startup Sequence http://onsemi.com 7 NCP1589A, NCP1589B VOS 0.88V 1.0V 0.88V 0.8V 0.72V 0.4V 0.8V 0.6V PGOOD UG LG Overvoltage Undervoltage Figure 8. Typical Power Good Function Feedback and Compensation Design Example Voltage Mode Control Loop with TYPE III Compensation Converter Parameters: The NCP1589A/B allows the output voltage to be adjusted from 0.8 V to 5.0 V via an external resistor divider network. The controller will try to maintain 0.8 V at feedback pin. Thus, if a resistor divider circuit was placed across the feedback pin to VOUT, the controller will regulate the output voltage proportional to the resistor divider network in order to maintain 0.8 V at the FB pin. The same formula applies to the VOS pin and the controller will maintain 0.8 V at the VOS pin. VOUT Input Voltage: VIN = 5 V Output Voltage: VOUT = 1.65 V Switching Frequency: 300 kHz Total Output Capacitance: COUT = 3600 mF Total ESR: ESR = 6 mW Output Inductance: LOUT: 1 mH Ramp Amplitude: VRAMP = 1.1 V C1 R1 FB R4 R3 C3 R2 C2 Figure 9. VOUT R1 − E/A + Vref VCOMP The relationship between the resistor divider network above and the output voltage is shown in the following equation: R4 + R1 VREF VOUT * VREF R4 Figure 10. The same formula can be applied to the feedback resistors at VOS. R9 + R10 VREF VOUT * VREF a.. Set a target for the close loop bandwidth at 1/6th of the switching frequency. F cross_over :+ 50 kHz http://onsemi.com 8 NCP1589A, NCP1589B b.. Output Filter Double Pole Frequency F lc :+ 1 2@p@ L OUT @ C OUT Step 5: Place 2nd zero at the output filter double pole frequency. R3 :+ R1 F SW lc F lc + 2.653 kHz 2@ F *1 c.. ESR Zero Frequency: F ESR :+ 1 2 @ p @ C OUT @ C ESR R3 + 74.169 W Step 6: Place 2nd pole at half the switching frequency. C3 :+ 1 p @ R3 @ F SW F ESR + 7.368 kHz Step 1: Set a value for R1 between 2 kW and 5 kW R1 :+ 4.12 kW C3 + 0.014 mF Step 2: Pick compensation DC gain (R2/R1) for desired close loop bandwidth. V RAMP :+ 1.1 V R2 :+ R1 @ V RAMP V IN @ F cross_over F lc Step 7: R4 is sized to maintain the feedback voltage to Vref = 0.8 V. R4 :+ V REF @ R1 V OUT * V REF R4 + 3.878 kW The Component values for Type III Compensation are: R2 + 17.085 kW Step 3: Place 1st zero at half the output filter double pole frequency. C2 :+ 2 @ L OUT @ C OUT R2 10 −3 mF C2 C2 @ R2 @ 2 @ p @ F ESR * 1 10 −3 mF C2 + 7.024 Step 4: Place 1st pole at ESR zero frequency. C1 :+ R1 = 4.12 kW R2 = 17.085 kW R3 = 74.169 W R4 = 3.878 kW C1 = 0.0015 mF C2 = 0.007 mF C3 = 0.014 mF NOTE: Recommend to change values to industry standard component values. C1 + 1.542 http://onsemi.com 9 NCP1589A, NCP1589B PACKAGE DIMENSIONS DFN10, 3x3, 0.5P CASE 485C−01 ISSUE B D A B L1 EDGE OF PACKAGE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS ONTO BOTTOM SURFACE OF TERMINAL b. 6. DETAILS A AND B SHOW OPTIONAL VIEWS FOR END OF TERMINAL LEAD AT EDGE OF PACKAGE. DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 2.40 2.60 3.00 BSC 1.70 1.90 0.50 BSC 0.19 TYP 0.35 0.45 0.00 0.03 PIN 1 REFERENCE 2X 2X 0.15 C 0.15 C 0.10 C 10X DETAIL B (A3) A A1 SEATING PLANE 0.08 C SIDE VIEW D2 10X A1 DETAIL A 5 C L e 1 SOLDERING FOOTPRINT* 2.6016 10X K E2 10 10X 6 2.1746 b BOTTOM VIEW 10X 0.10 C A B 0.05 C NOTE 3 0.5651 0.3008 10X *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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