NCP1599
Buck Regulator Synchronous
1 MHz, 3 A
The NCP1599 is a fixed 1 MHz, high−output−current, synchronous
PWM converter that integrates a low−resistance, high−side P−channel
MOSFET and a low−side N−channel MOSFET. The NCP1599 utilizes
internally compensated current mode control to provide good transient
response, ease of implementation, and excellent loop stability.
The NCP1599 includes an internally fixed switching frequency
(FSW), and an internal soft−start to limit inrush current.
Other features include cycle−by−cycle current limiting,
short−circuit protection, power saving mode and thermal shutdown.
Features
• Internal 140 mW High−Side P−Channel and 90 mW Low−Side
•
•
•
•
•
•
•
•
•
N−Channel MOSFET
Fixed 1 MHz Switching Frequency
Cycle−by−Cycle Current Limiting
Hiccup Mode Short−Circuit Protection
Overtemperature Protection
Internal Soft−Start
Start−up with Pre−Biased Output Load
Adjustable Output Voltage Down to 0.8 V
Power Saving Mode During Light Load
These are Pb−Free Devices
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MARKING
DIAGRAM
1
1
DFN6
CASE 506AH
A
Y
WW
G
1599
AYWW
G
= Assembly Location
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
FB 1
6 COMP
GND 2
5 VCC
LX 3
4 VCCP
(Top View)
Applications
•
•
•
•
•
•
•
•
•
DSP Power
Hard Disk Drivers
Computer Peripherals
Home Audio
Set−Top Boxes
Networking Equipment
LCD TV
Wireless and DSL/Cable Modem
USB Power Devices
© Semiconductor Components Industries, LLC, 2013
August, 2019 − Rev. 1
ORDERING INFORMATION
Device
NCP1599MNTWG
Package
Shipping†
DFN6
3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1
Publication Order Number:
NCP1599/D
NCP1599
BLOCK DIAGRAM
NCP1599
VCCP
VCC
Power Reset
UVLO
THD
Hiccup
+
CA
−
OSC
+
COMP
PMOS
Soft−Start
M1
Vref
FB
−
PWM
+
+
+ gm
−
Control
Logic
LX
GND
Figure 1. Block Diagram
PIN DESCRIPTIONS
Pin No
Symbol
Description
1
FB
2
GND
3
LX
4
VCCP
Power input for the power stage
5
VCC
Input supply pin for internal bias circuitry. A 0.1 mF ceramic bypass capacitor is preferred to connect
to this pin.
6
COMP
Output of the Gm Amplifier and compensation node. Connect a series R−C network from this pin to
GND for control loop regulation.
EP
PAD
Feedback input pin of the Error Amplifier. Connect a resistor divider from the converter’s output voltage to this pin to set the converter’s output voltage.
Ground pin. Connect to thermal pad.
The drains of the internal MOSFETs. The output inductor should be connected to this pin.
Exposed pad of the package provides both electrical contact to the ground and good thermal contact
to the PCB. This pad must be soldered to the PCB for proper operation.
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NCP1599
APPLICATION CIRCUIT
VCCP
Vin
3.3 V − 5.5 V
C1
22 mF
VCC
0.1 mF
COMP
LX
L1 (Note 1)
1.5 − 4.7 mH
C2
2 x 22 mF
GND
FB
Vout
0.8 V − 3.3 V
R1
RC
3.65 k
R2
10 k
CC
3.3 nF
R1 = R2 x (Vout / 0.8) − 1)
Figure 2. NCP1599 Application Circuit
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Vin
6.5
−0.3 (DC)
−1.0 (t < 100 ns)
V
Vin + 0.7
Vin + 1.0 (t < 20 ns)
−0.7 (DC)
−5.0 (t < 100 ns)
V
6.0
−0.3 (DC)
−1.0 (t < 100 ns)
V
TA
−40 to +85
°C
Junction Temperature
TJ
−40 to +150
°C
Storage Temperature Range
TS
−55 to +150
°C
RqJA
68.5
°C/W
Power Supply Pin (Pin 4, 5) to GND
LX to GND
All other pins
Operating Temperature Range
Thermal Resistance Junction−to−Air (Note 2)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. See External Component Reference Data for inductor selection.
2. RqJA measured on approximately 1x1 inch sq. of 1 oz. Copper.
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NCP1599
EXTERNAL COMPONENT REFERENCE DATA
VOUT (V)
IOUT Max (A)
Inductor (L1)
CIN Min
(C1) (mF)
COUT (C2) (mF)
R1 (kW)
R2 (kW)
Rc (kW)
Cc (nF)
3.3
3
2.2 mH
22 mF
2 X 22 mF
31.6
10
3.4 − 6.81
2.2 − 3.3
1−2
3.3 mH
3.65 − 10
2.2 − 3.3
3
2.2 mH
3.4 − 4.99
2.2 − 3.3
2
3.3 mH
3.4 − 6.81
2.2 − 3.3
1
4.7 mH
3.4 − 6.81
2.2 − 3.3
3
1.5 mH
3.4 − 6.81
2.2 − 3.3
2
2.2 mH
3.4 − 4.99
2.2 − 3.3
1
3.3 mH
3.4 − 6.81
2.2 − 3.3
3
1.5 mH
3.4 − 6.81
2.2 − 3.3
2
2.2 mH
3.4 − 4.99
2.2 − 3.3
1
3.3 mH
3.4 − 4.99
2.2 − 3.3
3
1.5 mH
3.4 − 6.81
2.2 − 3.3
2
2.2 mH
3.4 − 4.99
2.2 − 3.3
1
3.3 mH
3.4 − 4.99
2.2 − 3.3
3
1.5 mH
3.4 − 6.81
2.2 − 3.3
2
2.2 mH
3.4 − 4.99
2.2 − 3.3
1
3.3 mH
3.4 − 4.99
2.2 − 3.3
2.5
1.8
1.5
1.2
0.9
22 mF
2 X 22 mF
22 mF
2 X 22 mF
22 mF
2 X 22 mF
22 mF
2 X 22 mF
22 mF
2 X 22 mF
21.5
12.7
8.87
5.11
1.24
10
10
10
10
10
NOTE: This table shows the recommended components for six common output voltages. Compensation components are given in a range
of values that one may use to stabilize the NCP1599 over a range of output voltages and currents. Figure 2 also shows a
recommended schematic.
Please note that input lead lengths and traces should be as short as possible, especially for high bandwidth crossover frequencies.
Input capacitance may have to increase at higher bandwidths and currents as well.
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NCP1599
ELECTRICAL CHARACTERISTICS (Vin = 3.0 V − 5.5 V, Vout = 1.2 V, TJ = +25°C for typical value; −40°C < TJ < +125°C for
min/max values unless noted otherwise)
Parameter
Vin Input Voltage Range
Symbol
Test Conditions
Vin
Min
Typ
3.0
VCC UVLO Threshold
2.3
UVLO Hysteresis
2.75
Max
Unit
5.5
V
2.99
V
500
VCC Quiescent Current
IinVCC
Vin = 5.0 V, VFB = 1.5 V, (No Switching)
1.8
VCCP Quiescent Current
IinVCCP
Vin = 5.0 V,VFB = 1.5 V, (No Switching)
39
Reference Voltage
VFB
VFB = VCOMP
Feedback Input Bias Current
IFB
VFB = 0.8 V
mV
2.2
mA
mA
FEEDBACK VOLTAGE
Feedback Voltage Line Regulation
0.788
0.800
0.812
V
10
100
nA
0.03
%/V
VFB = VCOMP, Vin = 2.7 V to 6.0 V
GM AMPLIFIER
Gm Amp Open Loop Voltage Gain
(Note 3)
Gm Amp Transconductance (Note 3)
55
AVgm
gmCOMP
dB
1000
VFB > 0.75 V, DICOMP=$10 mA
mA/V
PWM
82
Maximum Duty Cycle (Regulating)
%
Minimum Controllable ON Time (Note 3)
50
ns
CURRENT SENSE AMPLIFIER
Current Sense to COMP
Transconductance (Note 3)
gmPOWER
5.0
A/V
PULSE−BY−PULSE CURRENT LIMIT
Pulse−by−Pulse Current Limit (Note 4)
Pulse−by−Pulse Current Limit
(Soft−Start) (Note 4)
ILIM
Vin = 4.0 V − 5.5 V
3.83
4.18
4.54
A
ILIMSS
Vin = 4.0 V − 5.5 V
4.12
4.40
4.72
A
0.87
1.0
1.13
MHz
140
175
mW
10
mA
100
mW
10
mA
OSCILLATOR
Oscillator Frequency
FSW
MOSFET
High Side MOSFET ON Resistance
High Side MOSFET Leakage (Note 3)
Low Side MOSFET ON Resistance
RDS(on)
HS
IDS = 100 mA, VGS = 5 V
RDS(on)
LS
IDS = 100 mA, VGS = 5 V
VSW = 0 V
Low Side MOSFET Leakage (Note 3)
90
VSW = 5 V
SOFT−START
1.0
ms
2.0
ms
Thermal Shutdown Threshold
170
°C
Thermal Shutdown Hysteresis
40
°C
Soft−Start Ramp Time (Note 3)
tSS
FSW = 1 MHz
Hiccup Timer (Note 3)
THERMAL SHUTDOWN
3. Guaranteed by design.
4. Current limit operation not guaranteed below Vin = 4.0 V.
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NCP1599
TYPICAL OPERATING CHARACTERISTICS
2.9
815
VFB, FB INPUT THRESHOLD (V)
2.8
2.7
UVLO Rising Threshold
UVLO (V)
2.6
2.5
2.4
2.3
2.2
2.1
UVLO Falling Threshold
2.0
1.9
−40
−15
10
35
60
800
795
790
−15
10
35
60
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 3. Undervoltage Lockout vs.
Temperature
Figure 4. Feedback Input Threshold vs.
Temperature
85
5.5
1.2
ILIM, CURRENT LIMIT (A)
fSW, SWITCH FREQUENCY (MHz)
805
785
−40
85
1.3
1.1
1.0
0.9
0.8
0.7
−40
810
−15
10
35
ILIM (Soft−Start)
4.5
4.0
ILIM (Regulation)
3.5
3.0
−40
85
60
5.0
TA, AMBIENT TEMPERATURE (°C)
−15
10
35
60
85
TA, AMBIENT TEMPERATURE (°C)
Figure 5. Switching Frequency vs.
Temperature
Figure 6. Current Limit vs. Temperature
2.0
85.0
84.8
84.6
DUTY CYCLE MAX (%)
ICC, SWITCHING (mA)
1.8
1.6
1.4
1.2
84.4
84.2
84.0
83.8
83.6
83.4
83.2
1.0
−40
−15
10
35
83.0
−40
85
60
−15
10
35
60
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 7. Quiescent Current Into VCC vs.
Temperature
Figure 8. Maximum Duty Cycle vs.
Temperature
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85
NCP1599
TYPICAL OPERATING CHARACTERISTICS
100
VOUT = 3.3 V
VIN = 5.0 V
COUT = 2 x 22 mF
3.38
3.36
90
3.32
L = 3.3 mH
3.30
3.28
3.26
L = 2.2 mH
3.24
70
60
L = 2.2 mH
50
40
VOUT = 3.3 V
VIN = 5.0 V
COUT = 2 x 22 mF
30
3.22
3.20
L = 3.3 mH
80
3.34
EFFICIENCY (%)
VOUT, OUTPUT VOLTAGE (V)
3.40
20
0.01
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
Figure 9. Load Regulation for VOUT = 3.3 V
80
1.84
L = 3.3 mH
1.82
L = 3.3 mH
90
EFFICIENCY (%)
VOUT, OUTPUT VOLTAGE (V)
1.86
1.80
L = 1.5 mH
1.76
1.74
L = 1.5 mH
70
60
50
40
VOUT = 1.8 V
VIN = 5.0 V
COUT = 2 x 22 mF
30
1.72
20
0.01
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
IOUT, OUTPUT CURRENT (A)
10
100
VOUT = 1.2 V
VIN = 5.0 V
COUT = 2 x 22 mF
1.28
1.26
80
1.24
L = 3.3 mH
1.22
L = 3.3 mH
90
EFFICIENCY (%)
VOUT, OUTPUT VOLTAGE (V)
1
Figure 12. Efficiency vs. Output Current for
VOUT = 1.8 V
1.30
1.20
L = 1.5 mH
1.16
1.14
L = 1.5 mH
70
60
50
40
VOUT = 1.2 V
VIN = 5.0 V
COUT = 2 x 22 mF
30
1.12
1.10
0.1
IOUT, OUTPUT CURRENT (A)
Figure 11. Load Regulation for VOUT = 1.8 V
1.18
10
100
VOUT = 1.8 V
VIN = 5.0 V
COUT = 2 x 22 mF
1.88
1.70
1
Figure 10. Efficiency vs. Output Current for
VOUT = 3.3 V
1.90
1.78
0.1
IOUT, OUTPUT CURRENT (A)
IOUT, OUTPUT CURRENT (A)
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
20
0.01
IOUT, OUTPUT CURRENT (A)
0.1
1
IOUT, OUTPUT CURRENT (A)
Figure 13. Load Regulation for VOUT = 1.2 V
Figure 14. Efficiency vs. Output Current for
VOUT = 1.2 V
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10
NCP1599
(VIN = 5 V, ILOAD = 120 mA, L = 2.2 mH, COUT = 2 x 22 mF)
Upper Trace: LX Pin Switching Waveform, 2 V/div
Middle Trace: Output Ripple Voltage, 20 mV/div
Lower Trace: Inductor Current, 1 A/div
Time Scale: 1.0 ms/div
(VIN = 5 V, ILOAD = 1.5 A, L = 2.2 mH, COUT = 2 x 22 mF)
Upper Trace: LX Pin Switching Waveform, 2 V/div
Middle Trace: Output Ripple Voltage, 20 mV/div
Lower Trace: Inductor Current, 1 A/div
Time Scale: 1.0 ms/div
Figure 15. DCM Switching Waveform for
VOUT = 3.3 V
Figure 16. CCM Switching Waveform for
VOUT = 3.3 V
(VIN = 5 V, ILOAD = 120 mA, L = 2.2 mH, COUT = 2 x 22 mF)
Upper Trace: LX Pin Switching Waveform, 2 V/div
Middle Trace: Output Ripple Voltage, 20 mV/div
Lower Trace: Inductor Current, 200 mA/div
Time Scale: 1.0 ms/div
(VIN = 5 V, ILOAD = 1.5 A, L = 2.2 mH, COUT = 2 x 22 mF)
Upper Trace: LX Pin Switching Waveform, 2 V/div
Middle Trace: Output Ripple Voltage, 20 mV/div
Lower Trace: Inductor Current, 1 A/div
Time Scale: 1.0 ms/div
Figure 17. DCM Switching Waveform for
VOUT = 1.2 V
Figure 18. CCM Switching Waveform for
VOUT = 1.2 V
(VIN = 5 V, ILOAD = 200 mA, L = 2.2 mH, COUT = 2 x 22 mF)
Upper Trace: VIN Pin Voltage, 5 V/div
Middle Trace: Output Voltage, 1 V/div
Lower Trace: Input Current, 100 mA/div
Time Scale: 500 ms/div
(VIN = 5 V, ILOAD = 200 mA, L = 2.2 mH, COUT = 2 x 22 mF)
Upper Trace: VIN Pin Voltage, 5 V/div
Middle Trace: Output Voltage, 1 V/div
Lower Trace: Input Current, 100 mA/div
Time Scale: 500 ms/div
Figure 19. Soft−Start Waveforms for VOUT = 3.3 V
Figure 20. Soft−Start Waveforms for VOUT = 1.2 V
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NCP1599
(VIN = 5 V, ILOAD = 100 mA, L = 2.2 mH, COUT = 2 x 22 mF)
Upper Trace: Output Dynamic Voltage, 100 mV/div
Lower Trace: Output Current, 500 mA/div
Time Scale: 200 ms/div
(VIN = 5 V, ILOAD = 100 mA, L = 2.2 mH, COUT = 2 x 22 mF)
Upper Trace: Output Dynamic Voltage, 100 mV/div
Lower Trace: Output Current, 500 mA/div
Time Scale: 200 ms/div
Figure 21. Transient Response for VOUT =
3.3 V
Figure 22. Transient Response for VOUT =
3.3 V
(VIN = 5 V, ILOAD = 100 mA, L = 2.2 H, COUT = 2 x 22 mF)
Upper Trace: Output Dynamic Voltage, 100 mV/div
Lower Trace: Output Current, 500 mA/div
Time Scale: 200 ms/div
(VIN = 5 V, ILOAD = 100 mA, L = 2.2 H, COUT = 2 x 22 mF)
Upper Trace: Output Dynamic Voltage, 100 mV/div
Lower Trace: Output Current, 500 mA/div
Time Scale: 200 ms/div
Figure 23. Transient Response for VOUT =
1.2 V
Figure 24. Transient Response for VOUT =
1.2 V
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NCP1599
DETAILED DESCRIPTION
Overview
Output MOSFETs
The NCP1599 is a synchronous PWM controller that
incorporates all the control and protection circuitry
necessary to satisfy a wide range of applications. The
NCP1599 employs current mode control to provide good
transient response, simple compensation, and excellent
stability. The features of the NCP1599 include a precision
reference, fixed 1 MHz switching frequency, a
transconductance error amplifier, an integrated high−side
P−channel MOSFET and low−side N−Channel MOSFET,
internal soft−start, and very low shutdown current. The
protection features of the NCP1599 include internal
soft−start, pulse−by−pulse current limit, hiccup mode
short−circuit protection, and thermal shutdown.
The NCP1599 includes low RDS(on), both high−side
P−channel and low−side N−channel MOSFETs capable of
delivering up to 3.0 A of current. When the controller is
disabled or during a Fault condition, the controller’s output
stage is tri−stated by turning OFF both the upper and lower
MOSFETs.
Adaptive Dead Time Gate Driver
In a synchronous buck converter, a certain dead time is
required between the low side drive signal and high side
drive signal to avoid shoot through. During the dead time,
the body diode of the low side FET freewheels the current.
The body diode has much higher voltage drop than that of
the MOSFET, which reduces the efficiency significantly.
The longer the body diode conducts, the lower the
efficiency. In NCP1599, the drivers and MOSFETs are
integrated in a single chip. The parasitic inductance is
minimized. Adaptive dead time control method is used in
NCP1599 to prevent the shoot through from happening and
minimizing the diode conduction loss at the same time.
Reference Voltage
The NCP1599 incorporates an internal reference that
allows output voltages as low as 0.8 V. The tolerance of the
internal reference is guaranteed over the entire operating
temperature range of the controller. The reference voltage is
trimmed using a test configuration that accounts for error
amplifier offset and bias currents.
Pulse Width Modulation
A high−speed PWM comparator, capable of pulse widths
as low as 50 ns, is included in the NCP1599. The inverting
input of the comparator is connected to the output of the
error amplifier. The non−inverting input is connected to the
the current sense signal. At the beginning of each PWM
cycle, the CLK signal sets the PWM flip−flop and the upper
MOSFET is turned ON. When the current sense signal rises
above the error amplifier’s voltage then the comparator will
reset the PWM flip−flop and the upper MOSFET will be
turned OFF.
Oscillator Frequency
A fixed precision oscillator is provided. The oscillator
frequency range is 1 MHz with ±13% variation.
Transconductance Error Amplifier
The transconductance error amplifier’s primary function
is to regulate the converter’s output voltage using a resistor
divider connected from the converter’s output to the FB pin
of the controller, as shown in the applications Schematic. A
series RC compensation network must be connected from
the error amplifier’s output (COMP pin) to GND to stabilize
the converter. In some applications, a lower value capacitor
may be connected from the COMP pin to GND to reduce the
loop gain at higher frequencies. However, if this capacitor
is too large the phase margin of the converter will be
reduced. If a Fault occurs, the COMP pin is immediately
pulled to GND and PWM switching is inhibited.
Power Save Mode
If the load current decreases, the converter will enter
power save mode operation automatically. During power
save mode, the converter skips switching and operates with
reduced frequency, which minimizes the quiescent current
and maintain high efficiency.
Internal Soft−Start
Current Sense Amplifier
To limit the startup inrush current, an internal soft start
circuit is used to ramp up the reference voltage from 0 V to
its final value linearly. The internal soft start time is 1 ms
typically.
The NCP1599 monitors the current in the upper
MOSFET. The current signal is required by the PWM
comparator, the pulse−by−pulse current limiter, and the
hiccup mode/over current counter.
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NCP1599
PROTECTIONS
Undervoltage Lockout (UVLO)
another normal soft−start. During soft−start, the overcurrent
protection threshold is increased to prevent false
overcurrent detection while charging the output capacitors.
The hiccup mode scheme reduces input supply current and
power dissipation during a short−circuit. It also allows for
much improved system up−time by allowing auto−restart
upon removal of a temporary short−circuit.
The undervoltage lockout feature prevents the controller
from switching when the input voltage is too low to power
the internal power supplies and reference. Hysteresis must
be incorporated in the UVLO comparator to prevent
resistive drops in the wiring or PCB traces from causing
ON/OFF cycling of the controller during heavy loading at
power up or power down.
The UVLO threshold allows steady−state operation at
input voltages as low as 3.3 V. However, the current limit at
these input voltage levels may not function appropriately
due to increased RDSon . This could cause excessive heating
and possible device failure.
Pre−Bias Startup
In some applications the controller will be required to start
switching when its output capacitors are charged anywhere
from slightly above 0 V to just below the regulation voltage.
This situation occurs for a number of reasons: the
converter’s output capacitors may have residual charge on
them or the converter’s output may be held up by a low
current standby power supply. NCP1599 supports pre−bias
start up by holding the low side FETs off till soft start ramp
reaches the FB Pin voltage.
Overcurrent Protection (OCP)
NCP1599 detects high side switch current and then
compares to a voltage level representing the overcurrent
threshold limit. If the current through the high side FET
exceeds the overcurrent threshold limit for seven
consecutive switching cycles, overcurrent protection is
triggered.
Once the overcurrent protection occurs, hiccup mode
engages. First, hiccup mode turns off both FETs and
discharges the internal compensation network at the COMP
pin. Next, the IC waits typically 2 ms and then resets the
overcurrent counter. After this reset, the circuit attempts
Thermal Shutdown
The NCP1599 protects itself from over heating with an
internal thermal monitoring circuit. If the junction
temperature exceeds the thermal shutdown threshold the
voltage at the COMP pin will be pulled to GND and both the
upper and lower MOSFETs will be shut OFF.
APPLICATION INFORMATION
Programming the Output Voltage
The output voltage is set using a resistive voltage divider
from the output voltage to FB pin (see Figure 25). So the
output voltage is calculated according to Eq.1.
V out + V FB @
R1 ) R2
R2
L+
V out
f @ I ripple
ǒ
@ 1*
V out
V in(max)
Ǔ
(eq. 2)
Where Vout − the output voltage;
f − switching frequency, 1.0 MHz;
Iripple − Ripple current, usually it’s 20% − 30% of output
current;
Vin(max) − maximum input voltage.
Choose a standard value close to the calculated value to
maintain a maximum ripple current within 30% of the
maximum load current. If the ripple current exceeds this
30% limit, the next larger value should be selected.
The inductor’s RMS current rating must be greater than
the maximum load current and its saturation current should
be about 30% higher. For robust operation in fault conditions
(start−up or short circuit), the saturation current should be
high enough. To keep the efficiency high, the series
resistance (DCR) should be less than 0.1 W, and the core
material should be intended for high frequency applications.
(eq. 1)
Vout
R1
FB
R2
Figure 25. Output divider
Output Capacitor Selection
Inductor Selection
The output capacitor acts to smooth the dc output voltage
and also provides energy storage. So the major parameter
necessary to define the output capacitor is the maximum
allowed output voltage ripple of the converter. This ripple is
The inductor is the key component in the switching
regulator. The selection of inductor involves trade−offs
among size, cost and efficiency. The inductor value is
selected according to the equation 2.
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NCP1599
network is to stabilize the control loop and achieve high
performance in terms of the transient response, audio
susceptibility and output impedance. Specifically, the
compensator is added to increase low frequency magnitude,
extend the 0 dB frequency (crossover frequency), and
improve the phase characteristic.
related to capacitance and the ESR. The minimum
capacitance required for a certain output ripple can be
calculated by Equation 4.
C OUT(min) +
I ripple
(eq. 3)
8 @ f @ V ripple
Where Vripple is the allowed output voltage ripple.
The required ESR for this amount of ripple can be
calculated by equation 5.
ESR +
Current Mode
Power Stage
LX
R1
V ripple
(eq. 4)
I ripple
+
Gm
Based on Equation 2 to choose capacitor and check its
ESR according to Equation 3. If ESR exceeds the value from
Eq.4, multiple capacitors should be used in parallel.
Ceramic capacitors can be used in most of the
applications. In addition, both surface mount tantalum and
through−hole aluminum electrolytic capacitors can be used
as well.
FB
R2
−
RGM
0.8 V
−
RC
I lim(min) * I load(max) *
Figure 26. NCP1599 Compensation Components
There are several different types of compensation that can
be used to improve the frequency response of the control
loop. To determine which compensation scheme to use,
some information about the power stage is needed. Use Vin
= Vin(min) and R = Rmin (Iout(max)) when calculating
compensation components.
The DC gain of the voltage feedback loop is given by:
Di p−p
2
V outńT SS(min)
(eq. 5)
A DC + R
The input capacitor can be calculated by Equation 6.
C in(min) + I out(max) @ D max @
1
f @ V in(ripple)
(eq. 6)
Where Vin(ripple) is the required input ripple voltage.
is the maximum duty cycle.
G CS
A EA
V FB
V out
(eq. 8)
Where AEA is the error amplifier voltage gain, 560 V/V
(55 db), GCS is the current sense transconductance, 5.0 A/V,
and R is the load resistor value.
The power stage has one pole due to the output capacitor
Cout and the load resistor R. It’s located at:
Input Capacitor Selection
V in(min)
CC2
CC1
Where TSS(min) is the minimum soft−start period (1ms);
DiPP is the current ripple.
This is assuming that a constant load is connected. For
example, with 3.3 V/2.0 A output and 20% ripple, the
maximum allowed output capacitance is 546 mF.
D max +
Cout
COMP
NCP1599 family has internal 1 ms fixed soft−start and
overcurrent limit. It limits the maximum allowed output
capacitor to startup successfully. The maximum allowed
output capacitance can be determined by the equation:
V out
RL
+
Maximum Output Capacitor
C out(max) +
ESR
CFF
f p1 +
1
2p @ C out @ R
(eq. 9)
The power stage may have a zero of importance, if the
output capacitor has a large capacitance and/or a high ESR
value. The zero, due to the ESR and capacitance of the
output capacitor, is located at:
(eq. 7)
Compensation Design
The NCP1599 is a current mode controller, therefore there
are two feedback loops. The inner feedback loop derives its
feedback from the sensed inductor current, while the outer
loop monitors the output voltage.
The compensation network is designed around the power
components, or the power stage. An isolated schematic of
the error amplifier and the various compensation
components is shown in Figure 26. The error amplifier in
conjunction with the compensation network makes up the
compensator network. The purpose of the compensator
f ESRZ +
1
2p @ C out @ R ESR
(eq. 10)
A compensator is designed to achieve improved
performance and stability. The NCP1599 will typically
require only a single resistor and capacitor for
compensation, but depending on the power stage it could
require three or four external components.
First, a target crossover frequency (fc) for the loop gain
must be selected. The crossover frequency is the bandwidth
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NCP1599
of the converter. A higher bandwidth generally corresponds
to faster response times and lower overshoots to load
transients. However, the bandwidth should not be much
higher than 1/10 the switching frequency. The NCP1599
operates with a 1.0 MHz switching frequency, so it is
recommended to choose a crossover frequency between
40 kHz − 100 kHz. The schematic of the NCP1599
compensator is shown in Figure 2. The default design uses
Rc and CC1 to form a lag (Type 2) compensator. The CC2
capacitor can be added to form an additional pole that is
typically used to cancel out the ESR zero of the output
capacitor. Finally, if extra phase margin is needed, the CFF
capacitor can be added (this does not help at low output
voltages, see below). The strategy taken here for choosing
Rc and CC1 is to set the crossover frequency with Rc, and set
the compensator zero with CC1.
Using the selected target crossover frequency, fc, set Rc to:
RC +
2p @ f C @ C out
Gm EA @ G CS
@
V out
V FB
W
C C2 +
2p
1
C C1
f Zff +
(eq. 11)
f pff +
3.16
v C C1 v
1
2p f p1 R C
(eq. 13)
The compensation capacitor (Cc1) and the output resistor
of error amplifier RGM creates another pole of the system,
and it’s located at:
f p2 +
1
2p
R GM
C C1
,
1
,
R R
2p @ C C2 @ R
C GM
)R
C
fS
2
R FB1 ) R FB2
2p R FB1C ff
R FB2
Where:
(eq. 14)
I RMS_FET +
+ f Zff
V out
V FB
(eq. 19)
2
RMS_HSFET
Ǹǒ
I out 2 )
R DS(on)HS
DI PP
12
Ǔ
(eq. 20)
2
D
(eq. 21)
DIPP is the peak−to−peak inductor current ripple.
The power lost due to switching the internal power high side
MOSFET is:
(eq. 15)
GM
P HSSW +
For the typical case, use CC2 if:
f ESR t
1
P HSON + I
Where RGM = 66 • 103 W.
In this compensation scheme, the pole created by CC2 is
used to cancel out the zero created by the ESR of the output
capacitor. This pole is located at:
f p3 +
(eq. 18)
2p R FB1 C ff
The NCP1599 is available in thermally enhanced 6−pin,
DFN package. When the die temperature reaches +185°C,
the NCP1599 shuts down (see the Thermal−Overload
Protection section). The power dissipated in the device is the
sum of the power dissipated from supply current (PQ),
power dissipated due to switching the internal power
MOSFET (PSW), and the power dissipated due to the RMS
current through the internal power MOSFET (PON). The
total power dissipated in the package must be limited so the
junction temperature does not exceed its absolute maximum
rating of +150°C at maximum ambient temperature.
Calculate the power lost in the NCP1599 using the following
equations:
1. High side MOSFET
The conduction loss in the top switch is:
When fast transient responses are desired, fZ1 should be
placed as high as possible, however it should not be higher
than the selected crossover frequency fc. The guideline
proposed here is to choose CC1 such that fZ1 falls somewhere
between the power pole fP1 and 1⁄2 decade before the
selected crossover frequency fc:
2p R C f C
1
Power Dissipation
(eq. 12)
RC
(eq. 17)
2p f ESR R GM R C
A feed−forward capacitor is recommended for most
designs. The large resistor value and the parasitic
capacitance of the FB Pin can cause a high frequency pole
that can reduce the overall system phase margin. By placing
a feed−forward capacitor CFF, these effects can be
significantly reduced. CFF will provide a positive phase shift
(lead) that can be used to increase phase margin. However,
it is important to note that the effectiveness of CFF decreases
with output voltage. This is due to the fact that the frequency
of the zero fzff and pole fpff get closer together as the output
voltage is reduced.
The frequency of the feed−forward zero and pole are:
fC = Crossover frequency in Hertz (50kHz − 200kHz is
recommended).
The zero, due to the compensation capacitor (Cc1) and the
compensation resistor (Rc), is located at:
f Z1 +
R GM ) R C
V in @ I out @ ǒt r ) t fǓ @ f SW
(eq. 22)
2
tr and tf are the rise and fall times of the internal power
MOSFET measured at SW node.
(eq. 16)
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NCP1599
rating. A ground plane should always be used under the
switcher circuitry to prevent interplane coupling and overall
noise.
The COMP and FB components should be kept as far
away as possible from the switch node. The ground for these
components should be separated from the switch current
path. Failure to do so will result in poor stability or
subharmonic like oscillation.
Board layout also has a significant effect on thermal
resistance. Reducing the thermal resistance from the ground
pin and exposed pad onto the board will reduce die
temperature and increase the power capability of the
NCP1599. This is achieved by providing as much copper
area as possible around the exposed pad. Adding multiple
thermal vias under and around this pad to an internal ground
plane will also help. Similar treatment to the inductor pads
will reduce any additional heating effects.
2. Low side MOSFET
The power dissipated in the top switch is:
P LSON + I RMS_LSFET 2 @ R DS(on)LS
Where:
I RMS_LSFET +
Ǹǒ
I out 2 )
DI PP
12
Ǔ
(eq. 23)
2
@ (1 * D )
(eq. 24)
DIPP is the peak−to−peak inductor current ripple.
The switching loss for the low side MOSFET can be
ignored.
The power lost due to the quiescent current (IQ) of the device
is:
P Q + V in @ I Q
(eq. 25)
IQ is the switching quiescent current of the NCP1599.
P TOTAL + P HSON ) P HSSW ) P LSON ) P Q
Derating
(eq. 26)
The following graph shows the maximum output current
of the NCP1599 with a typical 4−layer PCB layout vs input
voltage (Vin) and output current (Iout). The maximum
allowable current is 3 A. The maximum junction
temperature (TJ) of the device, so the ”thermal limit” shows
when maximum TJ is reached. The maximum duty cycle of
the NCP1599 is also shown. The PCB used for this data is
the standard evaluation board (NCP1599GEVB) and is
available at www.onsemi.com.
Calculate the temperature rise of the die using the following
equation:
T J + T C ) ǒP TOTAL @ q JCǓ
(eq. 27)
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. To prevent noise
both radiated and conducted, the high speed switching
current path must be kept as short as possible. Shortening the
current path will also reduce the parasitic trace inductance
of approximately 25 nH/inch. At switch off, this parasitic
inductance produces a flyback spike across the NCP1599
switch. When operating at higher currents and input
voltages, with poor layout, this spike can generate voltages
across the NCP1599 that may exceed its absolute maximum
3.0
2.9
2.8
2.7
2.6
2.5
2.4
Maximum
Current
Thermal
Limit
VIN = 5.0 V
Thermal
Limit
VIN = 3.3 V
2.3
2.2
2.1
2.0
0.8 1.1 1.4 1.7 2.0 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4
VOUT, OUTPUT VOLTAGE (V)
Figure 27. Derating Curves
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14
Maximum Duty Cycle
Layout
3.2
3.1
Maximum Duty Cycle
MAXIMUM OUTPUT CURRENT (A)
qJC is the junction−to−case thermal resistance equal to
1.7°C/W. TC is the temperature of the case and TJ is the
junction temperature, or die temperature. The case−to−
ambient thermal resistance is dependent on how well heat
can be transferred from the PC board to the air. Solder the
underside−exposed pad to a large copper GND plane. If the
die temperature reaches the thermal shutdown threshold the
NCP1599 shuts down and does not restart again until the die
temperature cools by 30°C.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN6 3*3 MM, 0.95 PITCH
CASE 506AH−01
ISSUE O
1
SCALE 2:1
PIN 1
REFERENCE
2X
0.15 C
2X
0.15 C
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMESNION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30
MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
D
B
ÇÇÇ
ÇÇÇ
ÇÇÇ
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.10 C
A
6X
0.08 C
(A3)
SIDE VIEW
6X
C
A1
SEATING
PLANE
e
4X
3
1
E2
K
MILLIMETERS
MIN
NOM MAX
0.80
0.90
1.00
0.00
0.03
0.05
0.20 REF
0.35
0.40
0.45
3.00 BSC
2.40
2.50
2.60
3.00 BSC
1.50
1.60
1.70
0.95 BSC
0.21
−−−
−−−
0.30
0.40
0.50
GENERIC
MARKING DIAGRAM*
D2
L
1
6X
DATE 17 NOV 2004
xxxxx
xxxxx
AYWW
Standard
6
4
6X
b
xxxxx
A
Y
WW
G
(NOTE 3)
0.10 C A B
BOTTOM VIEW
0.05 C
SOLDERING FOOTPRINT*
0.450
0.0177
0.63
0.025
1.700
0.685
DOCUMENT NUMBER:
DESCRIPTION:
2.60
0.1023
SCALE 10:1
98AON19891D
xxxxx
AYWW
G
Pb−Free
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.950
0.0374
3.31
0.130
1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
mm Ǔ
ǒinches
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DFN6 3*3 MM, 0.95 PITCH, SINGLE FLAG
PAGE 1 OF 1
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