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NCP1603
PFC/PWM Combo Controller
with Integrated High
Voltage Startup and Standby
Capability
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The NCP1603 is a Power Factor Correction (PFC) and Pulse Width
Modulation (PWM) combo controller. It offers extremely low
no−load standby power consumption that is suitable for the
low−power consumer markets. The key features of the device are
listed below.
Features
MARKING
DIAGRAM
1
• This is a Pb−Free Device*
SO−16
D SUFFIX
CASE 751B
PFC Features
• Near−Unity Power Factor in Discontinuous and Critical Mode
•
•
•
•
•
•
•
•
•
(DCM and CRM)
Voltage−Mode Operation
Low Startup and Shutdown Current Consumption
Programmable Switching Frequency for DCM
Synchronization Capability
Overvoltage Protection (107% of Nominal Output Level)
Undervoltage Protection or Shutdown
(8% of Nominal Output Level)
Programmable Overcurrent Protection
Thermal Shutdown with Hysteresis (95/140°C)
Undervoltage Lockout with Hysteresis (9.0/10.5 V)
PWM Features
• Integrated Lossless High Voltage Startup Current Source
• 100 kHz PWM Current−Mode Operation with Skipping Cycle
•
•
•
•
•
•
•
Capability During Standby Condition
PFC Bias Voltage is Disabled in Standby Condition to Achieve
Extremely Low No−Load Standby Power Consumption
Fault Protection Implemented by a Timer and Independent of Badly
Coupled Auxiliary Transformer Winding
Primary Overcurrent Protection and Latched Overvoltage Protection
Internal 2.5 ms Soft−Start
"6.4% Frequency Jittering for Improved EMI Performance
Latched Thermal Shutdown with Hysteresis (140/165°C)
Undervoltage Lockout with Hysteresis (5.6/7.7/12.6 V)
Applications
A
WL
Y
WW
G
16
1603D100G
AWLYWW
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
Vaux 1
16 HV
FB2 2
15 NC
CS2 3
14 VCC2
GND2 4
13 Out2
Osc 5
12 Ramp
GND1 6
11 CS1
Out1 7
10 Vcontrol
VCC1 8
9
FB1
(Top View)
ORDERING INFORMATION
Device
NCP1603D100R2G
Package
Shipping†
SO−16
2500 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Notebook Adapters
• TV/Monitors
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 9
1
Publication Order Number:
NCP1603/D
NCP1603
AC
Input
+
EMI
Filter
Output
Voltage
−
OVP
NCP1603
Not Synchronized and VCC OVP Latch Implemented
AC
Input
+
EMI
Filter
Output
Voltage
−
OVP
NCP1603
Synchronized and Output OVP Latch Implemented
Figure 1. Typical Application Circuits
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2
NCP1603
FB2
VFB2
2
5V
20k
10V
+
Thermal
Shutdown
(140/165°C)
0.75V
Gnd2
2.5 ms
Softstart
1V max
4
100 kHz
5ms Jittering
0~2.3V ramp
CS2
VCS2
3
+
−
VSS
1
0
200ns
LEB
10V
3V
VCC1
UVLO
(9 / 10.5V)
8
18V
FB1
9V
IS
CS1 11
9V
Current
Mirror
Current
Mirror
45A
Osc
5
9V
94A
0
1
S
OR
20V
3.2mA
initially
disable
Vaux
R
VCC2 mgmt
(12.6 / 7.7V)
(5.6 / 4V)
16 HV
Fault−2
PWM
VCC2
13 Out2
PWM
PFC
300k
Vreg
14 VCC2
Internal bias
96%I ref
C1
I ref I FB1
Regulation Block
Overvoltage
Protection
(IFB1 > 107% IREF)
Zero Current
Detection
(IS < 14 A)
+
−
5/ 3.5 V
R1
0
&
Overcurrent
Protection
(IS > 203 A)
R2
−
+
Thermal
Shutdown
(95/140°C)
&
PFC
Modulation
1
12
Ramp
7
Out1
6
GND1
9V
0
VCC1
R
delay
Figure 2. Functional Block Diagram
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3
Ich
Vton
clock
S Q
R
C3
1
R3
3.9V max
clamp
OR
10 Vcontrol
9V
+
−
Shutdown / UVP
(IFB1 < 8% IREF)
IFB1
9
Fault−2
&
Voltage
Regulator
&
disable Vaux
when VCC2 < 7.7V
latchoff, reset
when VCC2 < 4V
−
Internal bias
+
OR
+
R Q
S Q
−
100 kHz
S
R
OVP
Max duty
Fault−1 5ms Jittering
= 80%
latchoff, reset
Oscillator
when VCC2 < 4V
Error
18k
R Q
Q
125 ms
delay
Vaux
&
Fault−1
start_Vaux
1
S
&
125 ms
delay
Standby
−
0.75V/ 1.25V
55k
25k
start_Vaux
−
+
S Q
NCP1603
PIN FUNCTION DESCRIPTION
Pin
Symbol
Function
Description
1
Vaux
Auxiliary Supply
This pin connects to the VCC1 pin externally. It delivers a bias voltage from the VCC2 to the
PFC section. The Vaux is disabled when either one of the following conditions occurs:
(1) Vaux is initially off;
(2) Fault (VFB2 > 3.0 V for more than 125 ms);
(3) Standby (VFB2 < 0.75 V and then VFB2 is smaller than 1.25 V for more than 125 ms);
(4) Overvoltage protection latch activated from CS2 pin;
(5) Thermal shutdown latch in the PWM section;
(6) Insufficient supply voltage (VCC2 < 7.7 V).
The transistor turns on (or Vaux is enabled) when VFB2 is within the normal mode regulation
window (0.75 V < VFB2 < 3.0 V).
2
FB2
PWM Feedback
An external optocoupler collector pulls the voltage of this pin VFB2 down to regulate the
output voltage. The PWM regulation window between VFB2 = 0.75 V and VFB2 = 3.0 V. When
VFB2 drops below 0.75 V, the controller enters standby operation.
When no feedback signal is received from the optocoupler, VFB2 is internally pulled to be
higher than 3.0 V. If this condition lasts for longer than 125 ms, the controller enters
double−hiccup fault condition.
3
CS2
PWM Current Sense
This pin cumulates three different functions: current−mode PWM regulation, primary
overcurrent protection and overvoltage protection (OVP). If the voltage of this pin is above
3.0 V for OVP, the circuit is latched off until VCC2 resets. The PWM Drive Output is disabled.
An external noise decoupling pF−order capacitor is connected to the pin to prevent the latch
protection activated due to noise.
4
GND2
PWM Ground
−
5
Osc
PFC Oscillator
In oscillator mode, this pin is connected to an external capacitor to set the oscillator
frequency in DCM operation. In synchronization mode, this pin is connected to an external
driving signal. However, if the PFC−stage inductor current is non−zero at the end of a
switching period, the PFC−stage circuit will be forced to CRM and the Out1 is out of
synchronization to the Osc pin signal.
6
GND1
PFC Ground
7
Out1
PFC Drive Output
8
VCC1
PFC Supply Voltage
This pin is the positive supply of the PFC section. the operating range is between 9.0 V and
18 V with UVLO start threshold 10.5 V.
9
FB1
PFC Feedback
This pin receives a current IFB1 that represents the PFC circuit output voltage. The current is
for the output regulation, PFC section overvoltage protection (OVP) and PFC section output
undervoltage protection (UVP). When IFB1 goes above 107% Iref, OVP is activated and the
Drive Output is disabled. When IFB1 goes below 14 A, the PFC section enters a
low−current consumption shutdown mode.
10
Vcontrol
PFC Control Voltage
The control voltage Vcontrol directly controls the input impedance and hence the power factor
of the circuit. This pin is connected to an external capacitor to limit the control voltage
bandwidth typically below 20 Hz to achieve Power Factor Correction purpose.
11
CS1
PFC Current Sense
This pin receives a current IS that is proportional to the inductor current. The current is for
overcurrent protection (OCP), and zero current detection. When IS goes above 200 A, OCP
is activated and the Drive Output (Out1) is disabled. When IS goes below 14 A, it is
recognized to be a zero current for feedback regulation and DCM or CRM operation in the
PFC oscillator section.
12
Ramp
PFC Ramp
13
Out2
PWM Drive Output
14
VCC2
PWM Supply Voltage
15
NC
No Connected
16
HV
High Voltage
−
This pin provides an output to an external MOSFET in the PFC section.
This pin is connected to an external capacitor to set a ramp signal. The capacitor value
directly affects the input impedance of the PFC circuit and its maximum input power.
This pin provides an output to an external MOSFET in the PWM section.
This pin is basically the positive supply of the PWM section. It is also the positive supply of
the whole device because the PFC section is also supplied from this pin indirectly through
Vaux pin (Pin 1). The operating range is between 7.7 V and 18 V. The circuit resets when
VCC2 drops below 4.0 V.
This pin is for high voltage clearance of the HV pin.
This pin connects to the bulk DC voltage to deliver power to the controller in startup or fault
condition. The internal startup circuit is disabled in normal and standby condition for power
saving purpose. The UVLO stop and start thresholds of the startup circuit are VCC2 = 12.6 V
and VCC2 = 5.6 V.
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4
NCP1603
MAXIMUM RATINGS
Symbol
Value
Unit
Vaux Pin (Pin 1)
Maximum Voltage Range
Maximum Continuous Current
Rating
Vmax
Imax
−0.3 to +18
35
V
mA
FB2 and CS2 Pin (Pins 2−3)
Maximum Voltage Range
Maximum Current
Vmax
Imax
−0.3 to +10
100
V
mA
Ramp, CS1, Vcontrol, FB1, and Osc Pins (Pins 5, 9−12)
Maximum Voltage Range
Maximum Current
Vmax
Imax
−0.3 to +9.0
100
V
mA
Out1 Pin (Pin 7)
Maximum Voltage Range
Maximum Current
Vmax
Imax
−0.3 to +18
−500 to +750
V
mA
VCC1 and VCC2 Pins (Pins 8, 14)
Maximum Voltage Range
Maximum Current
Vmax
Imax
−0.3 to +18
100
V
mA
Out2 Pin (Pin 13)
Maximum Voltage Range
Maximum Current
Vmax
Imax
−0.3 to +17.5
1.0
V
A
HV Pin (Pin 16)
Maximum Voltage Range
Maximum Current
Vmax
Imax
−0.3 to +500
100
V
mA
Power Dissipation and Thermal Characteristics
Maximum Power Dissipation (TA = 25°C)
Thermal Resistance, Junction−to−Air
PD
RJA
770
111
mW
°C/W
Operating Junction Temperature Range
TJ
−40 to +125
°C
Maximum Storage Temperature Range
Tstg
−60 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device contains ESD protection and exceeds the following tests:
Pin 1−14: Human Body Model 2000 V per Mil−Std−883, Method 3015.
Machine Model Method 200 V.
Pin 16 is the HV startup of the device and is rated to the maximum rating of the part, or 500 V.
2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
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5
NCP1603
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values, TJ = −40°C to +125°C, VCC2 = 13 V,
HV = 30 V, VCC1 = 15 V, Vcontrol = 100 nF, Ramp = 330 pF, Osc = 220 pF unless otherwise specified).
Characteristic (PWM Section)
Pin
Symbol
Min
Typ
Max
Unit
Oscillation Frequency (TJ = 25_C) (Note 3)
Oscillation Frequency (TJ = 0_C to +125_C)
Oscillation Frequency (TJ = −40_C to +125_C)
−
fosc2
93
90
85
100
−
−
107
110
110
kHz
Oscillator Modulation Swing, in Percentage of fosc2
−
−
−
"6.4
−
%
Oscillator Modulation Swing Period
−
−
−
5.0
−
ms
Maximum Duty Ratio (VCS2 = 0 V, VFB2 = 2.0 V)
−
Dmax
75
80
85
%
ROH2
ROL2
6.0
3.0
12.3
7.5
25
18
PWM OSCILLATOR
PWM GATE DRIVE
Gate Drive Resistor
Output High (VCC2 = 13 V, Out2 = 300 to GND2)
Output Low (Out2 = 1.0 V, VFB2 = 0 V)
13
Gate Drive Rise Time from 10% to 90% (Out2 = 1.0 nF to GND2)
13
tr2
−
40
−
ns
Gate Drive Fall Time from 90% to 10% (Out2 = 1.0 nF to GND2)
13
tf2
−
15
−
ns
Maximum Current Threshold (TJ = 25_C)
Maximum Current Threshold (TJ = −40_C to +125_C)
3
ILimit
0.991
0.96
1.043
−
1.095
1.106
V
Soft−Start Duration
−
tSS
−
2.5
−
ms
Leading Edge Blacking Duration
3
tLEB
100
200
350
ns
Propagation Delay from CS Detected to Turn Out2 Off
−
Tdelay(CS)
−
90
180
ns
Overvoltage Protection Threshold
3
VOVP
2.7
3.0
3.3
V
Internal Compensation Ramp (Peak−to−Peak) (Note 4)
3
Vcomp
−
2.3
−
V
Internal Resistor to Ramp (Note 4)
3
Rcomp
9.0
18
36
k
Vstby
Vstby−out
0.6
1.0
0.75
1.25
0.9
1.5
V
V
PWM CURRENT SENSE/OVERVOLTAGE PROTECTION
PWM STANDBY THRESHOLDS/FEEDBACK
Standby Thresholds
Feedback Voltage VFB2 to Start Standby
Feedback Voltage VFB2 to Stop Standby
2
Validation Time for Leaving Standby
2
tstby−aux
−
125
−
ms
Validation Time for Recognize a Fault
2
tfault
−
125
−
ms
Feedback Pin Sinking Capability (VFB2 = 0.75 V)
2
IFB2
200
235
270
A
1
Raux
6.0
11.7
23
Thermal Shutdown Threshold (Note 4)
−
TSD2
150
165
−
°C
Thermal Shutdown Hysteresis
−
TH2
−
25
−
°C
IHV1
IHV2
IHV3
1.8
1.8
10
3.2
4.4
30
4.2
5.6
80
mA
mA
A
Vstart(min)
−
20
23
V
AUXILIARY SUPPLY
Vaux MOSFET Resistance
(VCC2 = 13 V, VFB = 2.0 V, Vaux = 20 mA Sinking)
PWM THERMAL SHUTDOWN
PWM STARTUP CURRENT SOURCE
High−Voltage Current Source
Startup (VCC2 = VCC2(on)−0.2 V, VFB2 = 2.0 V, HV = 30 V)
Startup (VCC2 = 0 V, HV = 30 V)
Leakage (VCC2 = 13 V, HV = 700 V)
16
Minimum Startup Voltage (VCC2 = VCC2(on)−0.2 V, IHV = 0.5 mA)
16
3. Consult factory for other frequency options.
4. Guaranteed by design.
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6
NCP1603
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values, TJ = −40°C to +125°C, VCC2 = 13 V,
HV = 30 V, VCC1 = 15 V, Vcontrol = 100 nF, Ramp = 330 pF, Osc = 220 pF unless otherwise specified).
Characteristic (PFC Section)
Pin
Symbol
Min
Typ
Max
Unit
VCC2(on)
VCC2(off)
VCC2(latch)
VCC2(reset)
11.6
7.0
5.0
−
12.6
7.7
5.6
4.0
13.6
8.4
6.2
−
V
V
V
V
ICC2(op1)
ICC2(op2)
ICC2(latch)
0.6
1.3
400
1.1
2.2
680
1.8
3.0
1000
mA
mA
A
PWM SUPPLY SECTION
Supply Voltage
Startup Threshold, VCC2 Increasing
Minimum Operating Valley Voltage after Turn−On
Undervoltage Lockout Threshold Voltage, VCC2 Decreasing
Logic Reset Level
14
Supply Current
Operating (VCC2 = 13 V, Out2 = Open, VFB2 = 2.0 V)
Operating (VCC2 = 13 V, Out2 = 1.0 nF to GND2, VFB2 = 2.0 V)
Latch−Off Phase (VCC2 = 6.5 V, VFB2 = 2.0 V)
14
PFC OSCILLATOR
Oscillator Frequency (Osc = 220 pF to GND)
5
fosc1
52
58
64
kHz
Internal Capacitance of the Oscillator Pin
5
Cosc(int)
−
36
−
pF
Maximum Oscillator Switching Frequency
5
fosc1(max)
−
405
−
kHz
Oscillator Discharge Current (Osc = 5.5 V)
5
Iodch
40
49
60
A
Oscillator Charge Current (Osc = 3.0 V)
5
Ioch
40
45
60
A
Comparator Lower Threshold (Osc = 220 pF to GND) (Note 5)
5
Vsync(L)
3.0
3.5
4.0
V
Comparator Upper Threshold (Osc = 220 pF to GND)
5
Vsync(H)
4.5
5.0
5.5
V
Synchronization Pulse Width for Detection
5
tsync(min)
500
−
−
ns
Synchronization Propagation Delay
5
tsync(d)
−
371
−
ns
ROH1
5.0
11.6
20
ROL1
2.0
7.2
18
PFC GATE DRIVE
Gate Drive Resistor
Output High and Draw 100 mA out of Out1 Pin
(Isource = 100 mA)
Output Low and Insert 100 mA into Out1 Pin
(Isink = 100 mA)
7
Gate Drive Rise Time from 1.5 V to 13.5 V
(Out1 = 1.0 nF to GND)
7
tr1
−
53
−
ns
Gate Drive Fall Time from 13.5 V to 1.5 V
(Out1 = 1.0 nF to GND)
7
tf1
−
32
−
ns
PFC FEEDBACK/OVERVOLTAGE PROTECTION/UNDERVOLTAGE PROTECTION
Reference Current
9
Iref
192
203
208
A
Regulation Block Ratio
9
IregL/Iref
95
96
97
%
Vcontrol Pin Internal Resistor
10
Rcontrol
−
300
−
k
Maximum Control Voltage (IFB1 = 100 A)
10
Vcontrol(max)
0.95
1.05
1.15
V
Feedback Pin Voltage (IFB1 = 100 A)
9
VFB1−100
−
3.0
−
V
Overvoltage Protection Current Ratio
9
IOVP/Iref
104
107
−
%
Overvoltage Protection Current Threshold
9
IOVP
−
217
225
A
Undervoltage Protection Current Threshold
9
IUVP/Iref
4.0
8.0
15
%
5. Comparator lower threshold is also the synchronization threshold.
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7
NCP1603
ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max values, TJ = −40°C to +125°C,
VCC2 = 13 V, HV = 30 V, VCC1 = 15 V, Vcontrol = 100 nF, Ramp = 330 pF, Osc = 220 pF unless otherwise specified).
Characteristic (PFC Section)
Pin
Symbol
Min
Typ
Max
Unit
Current Sense Pin Offset Voltage (IS = 100 A)
11
VS
−
4.0
−
mV
Overcurrent Protection Level
11
IS(OCP)
190
203
210
A
Current Sense Pin Offset Voltage at Overcurrent Level
11
VS(OCP)
0
3.2
20
mV
Zero Current Detection Level
11
IS(ZCD)
9
14
19
A
Current Sense Pin Offset Voltage at Zero Current Level
11
VS(ZCD)
0
7.5
20
mV
Zero Current Sense Resistor (RS(ZCD) = VS(ZCD)/IS(ZCD))
11
RS(ZCD)
−
0.536
1.0
k
Charging Current (Ramp = 0 V)
12
Ich
95
100
105
A
Maximum Power Resistance (Rpower = Vcontrol(max)/Ich)
12
Rpower
9.5
10
11.5
k
Internal Clamping of Voltage Vton
−
Vton(max)
−
3.9
−
V
Internal Capacitance of the Ramp Pin
12
Cramp(int)
−
22
−
pF
Ramp Pin Sink Resistance
(Osc = 0 V, Ramp = 1.0 mA sourcing)
12
Rramp
−
71.5
−
Thermal Shutdown Threshold (Note 6)
−
TSD1
140
170
−
°C
Thermal Shutdown Hysteresis
−
TH1
−
45
−
°C
VCC1(on)
VCC1(off)
VH1
9.6
8.25
1.0
10.5
9.0
1.5
11.4
9.75
−
V
V
V
ICC1(stup)
ICC1(op1)
ICC1(op2)
ICC1(stdn)
−
−
−
−
17
2.7
3.7
24
40
5.0
5.0
50
A
mA
mA
A
PFC CURRENT SENSE
PFC RAMP
PFC THERMAL SHUTDOWN
PFC SUPPLY SECTION
Supply Voltage
Startup Threshold (UVLO)
Minimum Voltage for Operation after Turn−On
UVLO Hysteresis
8
Supply Current
Start−Up (VCC1 = VCC1(on)–0.2 V)
Operating (VCC1 = 15 V, Out1 = Open, Osc = 220 pF)
Operating (VCC1 = 15 V, Out1 = 1.0 nF to GND1, Osc = 220 pF)
Shutdown (VCC1 = 15 V, IFB = 0 A)
8
6. Guaranteed by design.
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8
PWM SECTION FREQUENCY JITTERING (%)
PWM SECTION OSCILLATOR FREQUENCY (kHz)
NCP1603
110
108
106
104
102
100
98
96
94
92
90
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
12
10
8
6
4
2
0
−50
85
84
83
82
81
80
79
78
CS2 Pin = 0 V
FB2 Pin = 2 V
77
76
75
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
16
14
1
0.95
125
PWM SECTION SOFT−START PERIOD (ms)
PWM SECTION CURRENT LIMIT (V)
1.05
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
ROH2
12
10
8
ROL2
6
4
2
0
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 6. PWM Section Gate Drive Resistance
vs. Temperature
1.1
−25
125
18
Figure 5. PWM Section Maximum Duty
vs. Temperature
0.9
−50
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 4. PWM Section Oscillator Frequency
Jittering vs. Temperature
PWM SECTION GATE DRIVE RESISTANCE ()
PWM SECTION MAXIMUM DUTY (%)
Figure 3. PWM Section Oscillator Frequency
vs. Temperature
−25
3
2.5
2
1.5
1
0.5
0
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 8. PWM Section Soft−Start Period
vs. Temperature
Figure 7. PWM Section Current Limit
vs. Temperature
http://onsemi.com
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125
PWM SECTION CS PROPAGATION DELAY (ns)
PWM SECTION LEAD EDGE BLANKING (ns)
NCP1603
350
300
250
200
150
100
50
0
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
120
100
80
60
40
20
0
−50
500
450
400
350
300
250
200
150
VCS2 = 2 V
VFB2 = 2 V
100
50
0
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
3.1
3.05
3
2.95
2.9
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 12. CS2 Pin Overvoltage Protection
Threshold vs. Temperature
1.4
160
1.2
PWM SECTION VALIDATION TIME
FOR LEAVING STANDBY (ms)
PWM SECTION STANDBY THRESHOLDS (V)
125
3.15
Figure 11. PWM Section Minimum Output Pulse
vs. Temperature
Vstby−out
1
0.8
Vstby
0.6
0.4
0.2
0
−50
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 10. CS2 Pin Propagation Delay
vs. Temperature
PWM SECTION CS PIN OVP THRESHOLD (V)
PWM SECTION MINIMUM PULSE (ns)
Figure 9. PWM Section Lead Edge Blanking
vs. Temperature
−25
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
140
120
100
80
60
40
20
0
−50
Figure 13. PWM Section Standby Thresholds
vs. Temperature
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 14. PWM Section Validation Time for
Leaving Standby vs. Temperature
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10
125
250
PWM SECTION VALIDATION TIME FOR
RECOGNIZE A FAULT (ms)
PWM SECTION FB PIN SINKING CAPABILITY (A)
NCP1603
245
240
235
230
225
220
215
VFB2 = 0.75 V
210
205
200
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
160
140
120
100
125
80
60
40
20
0
−50
STARTUP HIGH VOLTAGE CURRENT
SOURCE (mA)
Vaux PIN MOSFET RESISTANCE ()
20
18
16
14
Vaux = 20 mA Sinking
VCC2 = 13 V
10
8
6
4
2
0
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
5
HV PIN MINIMUM STARTUP VOLTAGE (V)
HV PIN LEAKAGE CURRENT (A)
HV Pin = 700 V
VCC2 = 13 V
40
30
20
10
−25
IHV1 (VCC2 = 0 V)
4
3
2
IHV2 (VCC2 = VCC2(on) − 0.2 V)
1
HV Pin = 30 V
0
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 18. PWM Section High Voltage Startup
Current Source vs. Temperature
60
0
−50
125
6
Figure 17. Vaux Pin Internal MOSFET
Resistance vs. Temperature
50
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 16. PWM Section Validation Time for
Recognizing a Fault vs. Temperature
Figure 15. FB2 Pin Sinking Capability
vs. Temperature
12
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
25
24
23
VCC2 = VCC2(on) − 0.2 V
IHV = 0.5 mA
22
21
20
19
18
17
16
15
−50
Figure 19. PWM Section HV Pin Leakage
Current vs. Temperature
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 20. PWM Section HV Pin Minimum
Operating Voltage vs. Temperature
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11
125
PWM SECTION SUPPLY VOLTAGE
THRESHOLDS (V)
14
12
VCC2(on)
10
VCC2(off)
8
VCC2(latch)
6
4
VCC2(reset)
2
0
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
PWM SECTION SUPPLY CURRENTS (mA)
NCP1603
2.5
2
1.5
0.5
0
−50
ICC2(latch) (VCC2 = 6.5 V)
−25
VFB2 = 2 V
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 22. PWM Section Supply Currents
vs. Temperature
51
60
PFC SECTION OSC PIN CHARGE
AND DISCHARGE CURRENT (A)
PFC SECTION OSCILLATOR FREQUENCY (kHz)
ICC2(op2) (VCC2 = 13 V, Out2 = Open)
1
Figure 21. PWM Section Supply Voltage
Thresholds vs. Temperature
59
58
57
56
55
54
53
52
51
50
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
50
49
48
46
COSC = 220 pF
4
Vsync(L)
3.5
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
PFC SECTION GATE DRIVE RESISTANCE ()
Vsync(H)
4.5
3
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 24. PFC Section Osc Pin Charge and
Discharge Current vs. Temperature
5.5
5
Ioch (Osc Pin = 3 V)
45
44
−50
125
Iodch (Osc Pin = 5.5 V)
47
Figure 23. PFC Section Oscillator Frequency
vs. Temperature
PFC SECTION SYNCHRONIZATION
THRESHOLDS (V)
ICC2(op1) (VCC2 = 13 V, 1 nF Load)
18
16
14
ROH1
12
10
8
ROL1
6
4
2
0
−50
Figure 25. PFC Section Synchronization
Thresholds vs. Temperature
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 26. PFC Section Gate Drive Resistance
vs. Temperature
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12
210
PFC SECTION REGULATION BLOCK (V)
PFC SECTION REFERENCE CURRENT (A)
NCP1603
208
206
204
202
200
198
196
194
192
190
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
1.2
1
TJ = 25°C
0.8
TJ = −40°C
0.6
0.4
TJ = 125°C
0.2
0
150
160
99
98
97
96
95
94
93
92
91
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
1.08
1.06
1.04
IFB = 100 A
1.02
1
−50
Figure 29. PFC Section Regulation Block
vs. Temperature
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
110
5
TJ = 25°C
4
TJ = 125°C
TJ = −40°C
3
2
1
0
50
100
150
200
IFB, FEEDBACK CURRENT (A)
PFC SECTION OVERVOLTAGE
PROTECTION RATIO (%)
FB1 PIN OFFSET VOLTAGE (V)
−25
Figure 30. PFC Section Maximum Control
Voltage vs. Temperature
6
0
220
1.1
100
90
−50
210
Figure 28. PFC Section Regulation Block
Transfer Function
PFC SECTION MAXIMUM CONTROL
VOLTAGE (V)
PFC SECTION REGULATION BLOCK RATIO (%)
Figure 27. PFC Section Reference Current
vs. Temperature
170
180
190
200
IFB, FEEDBACK CURRENT (A)
109.5
109
108.5
108
107.5
107
106.5
106
105.5
105
−50
250
Figure 31. Feedback Pin Voltage
vs. Feedback Current
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 32. PFC Section Overvoltage Protection
Ratio vs. Temperature
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220
10
218
9
PFC SECTION OVERVOLTAGE
PROTECTION RATIO (%)
PFC SECTION OVERVOLTAGE
PROTECTION THRESHOLD (A)
NCP1603
216
214
212
210
208
206
204
202
200
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
8
7
6
5
4
3
2
1
0
−50
125
Figure 33. PFC Section Overvoltage Protection
Threshold vs. Temperature
PFC SECTION CS PIN OFFSET (mV)
CS1 PIN OFFSET VOLTAGE (mV)
100
80
60
TJ = −40°C
20
0
0
50
TJ = 125°C
TJ = 25°C
100
150
200
IS1, CS1 PIN CURRENT (A)
250
10
9
8
7
5
4
3
PFC SECTION ZERO CURRENT THRESHOLD (A)
PFC SECTION OVERCURRENT
PROTECTION THRESHOLD (A)
VS(OCP)
2
1
0
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 36. PFC Section CS Pin Offset
vs. Temperature
210
208
206
204
202
200
198
196
194
192
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
VS(ZCD)
6
Figure 35. CS1 Pin Offset Voltage
vs. Current
190
−50
125
Figure 34. PFC Section Overvoltage Protection
Ratio vs. Temperature
120
40
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
15
14.5
14
13.5
13
12.5
12
11.5
11
10.5
10
−50
Figure 37. PFC Section Overcurrent
Protection Threshold vs. Temperature
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 38. PFC Section Zero Current
Threshold vs. Temperature
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125
NCP1603
600
500
400
300
200
100
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
104
103
102
101
100
99
98
97
96
95
−50
Figure 39. PFC Section Zero Current Sense
Resistance vs. Temperature
12
11.5
11
10.5
10
9.5
9
8.5
8
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
10.5
VCC1(on)
10
9.5
9
VCC1(off)
8.5
125
8
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 42. PFC Section Supply Voltage
Undervoltage Lockout Thresholds vs. Temperature
35
4
PFC SECTION OPERATING SUPPLY
CURRENTS (mA)
PFC SECTION SUPPLY STARTUP AND
SHUTDOWN CURRENTS (A)
125
11
Figure 41. PFC Section Maximum Power
Resistance vs. Temperature
30
25
ICC1(stdn)
20
15
ICC1(stup)
10
5
0
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 40. PFC Section Charging Current
vs. Temperature
PFC SECTION SUPPLY VOLTAGE UVLO
THRESHOLDS (V)
PWM SECTION MAXIMUM POWER RESISTANCE (k)
0
−50
105
PFC SECTION CHARGING CURRENT (A)
PFC SECTION ZERO CURRENT
SENSE RESISTOR ()
700
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 43. PFC Section Supply Current in Startup
and Shutdown Conditions vs. Temperature
3.8
3.6
3.4
ICC1(op2), 1 nF Load
3.2
3
2.8
ICC1(op1), No Load
2.6
2.4
2.2
2
−50
VCC1 = 15 V, COSC = 220 pF
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 44. PFC Section Operating Supply Currents
vs. Temperature
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15
NCP1603
OPERATING DESCRIPTION
Vin
Vac
EMI
Filter
D1
L
Q1
Cfilter
D2
Vbulk
+
Cbulk
D3
Cout
Cosc
IFB1
IL
Zref
RFF
ZOVP
RS1
RCS1
ID
NCP1603
RFB1
Vout
−
Cs
Q2
IS
RS2
Ccontrol
Cramp
RCS2
Figure 45. Typical Application Circuit
Introduction
The NCP1603 is a PWM/PFC combo controller for
two−stages PFC low−power application. A typical
application circuit is listed in Figure 45. The first−stage PFC
boost circuit draws a near−unity power factor current from the
input but it also steps up the rectified input voltage Vin to a
high bulk voltage Vbulk in the bulk capacitor Cbulk. Then, the
second−stage PWM flyback circuit converts the bulk voltage
Vbulk to a usable low voltage and isolated output voltage Vout.
The controllers of the two stages are combined to become a
single PWM/PFC combo controller. The advantages of
NCP1603 are the following:
1. Integrated maximum 500 V lossless high voltage
startup circuit that saves area and power loss.
2. Low standby power consumption because of PFC
shutdown and skipping cycle operation.
3. Proprietary PFC methodology limits the
maximum switching frequency and frequency
jittering feature of the second−stage make the
easier front−ended EMI filter design.
4. Internal ramp compensation for stability
improvement in the second stage converter.
5. Minimum number of external components.
6. Optional synchronization capability between the
PFC and PWM sections for bulk capacitor ripple
current reduction.
7. Safety protection features.
NCP1603 is a co−package of two individual IC dies.
(NCP1601 and NCP1230, 100 kHz) The PFC die links up
pin 5 to pin 12 that are in the lower half of Figure 46. The
PWM die links up the other pins that are in the upper half
of Figure 46. For simplicity, the PFC pins are named with
suffix one that stands for the first stage and the PWM pins
are named with suffix two that stands for the second stage.
This dual−dies architecture allows the PFC die to be
completely powered off in the standby low−power
condition. It makes the power supply an excellent
low−power no load standby performance.
Vaux 1
16 HV
FB2 2
PWM
Die
CS2 3
GND2 4
15 NC
14 VCC2
13 Out2
Osc 5
12 Ramp
GND1 6
PFC
Die
Out1 7
VCC1 8
11 CS1
10 Vcontrol
9
FB1
Figure 46. Internal Connection
Biasing the Controller
The PWM section is the master section that always
operates. The PFC section is the slave section that is
powered off in standby condition for power saving. It is
implemented by connecting Vaux pin (Pin 1) and VCC1 pin
(Pin 8) together externally. The VCC1 pin generally
requires a small decoupling external capacitor (0.1 F) or
nothing. The PWM section powers the PFC section. The
VCC of the whole device refers to VCC2 (Pin 14) in the
PWM section (i.e., VCC = VCC2).
Vbulk
16
VCC2
14
NCP1603
1
4
6
CVCC
8
GND1 = GND2
VCC1 = Vaux
Figure 47. Bias Supply Schematic
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16
NCP1603
example, the PWM die consumes ICC2(op2) (2.2 mA typical),
a 47 F VCC capacitor can maintain the VCC above 7.7 V for
105 ms. It is the available time to establish a VCC voltage
from the flyback transformer auxiliary winding.
The recommended biasing schematic of the controller is in
Figure 47 while a typical completed application schematic
can be referred to Figure 45. These two dies have their own
individual supply voltages at Pin 8 and Pin 14. The grounds
of the two dies are physically connected through the package
substrate but they are needed to be connected externally. The
bias voltage to the NCP1603 comes from the bulk voltage
Vbulk through the HV pin (Pin 16) during startup. After
startup, a second−stage flyback transformer auxiliary winding
delivers the supply voltage to VCC.
47 F·(12.6 V−7.7 V)
C
V
tstartup + VCC
+
+ 105 ms
ICC2(op2)
2.2 mA
(eq. 1)
A large enough VCC capacitor can also help to maintain
VCC2 always above VCC2(off) to prevent the IC accidentally
powered off during the standby condition where the
low−frequency ripple of VCC2 can be very high.
The PFC section does not consume any current in the
startup phase since Vaux is disabled initially (i.e., Vaux =
VCC1 = 0 V).
When VCC2 falls below VCC2(off) (7.7 V typical) for
whatever reason, the PWM section sleeps and it consumes
ICC2(latch) (680 A typical) until VCC2 reaches VCC2(latch)
(5.6 V typical). When VCC2 reaches VCC2(latch) (5.6 V
typical), the startup current source activates and VCC2 rises
again.
Lossless High Voltage Startup Circuit
Vbulk
HV
16
3.2 mA
Turn Off
UVLO
Q S
R
Double
Hiccup
B2
Counter
+
-
VFB2
Fault Condition (VFB2 > 3.0 V)
Non−
usable
Vaux
Enabled
Region
7.7 V
+
&
3.0 V
12.6/
5.6 V
VCC
0.75 V
14
Usable
Vaux
Enabled
Region
Standby Condition (VFB2 < 0.75 V)
VCC2 (PWM)
20 V
7.7 V
12.6 V
18 V
VCC1 (PFC)
Turn on Internal Bias
Figure 48. VCC2 Management
9.0 V 10.5 V
The HV pin (Pin 16) is capable of the maximum 500 V so
that this pin can be directly connected to the bulk voltage
Vbulk and delivers startup supply voltage to the controller.
Figure 48 illustrates the block diagram of the startup circuit.
An UVLO comparator monitors the VCC at Pin 14. A startup
current source is activated and deactivated whenever the
voltage reaches VCC2(latch) (5.6 V typical) and VCC2(on)
(12.6 V typical) thresholds respectively. Therefore, the VCC
never drops below VCC2(latch) after powering up unless the
circuit is unplugged (i.e., Vbulk disappears or smaller than its
minimum required operating threshold Vstart(min) (20 V
typical)). This feature makes the controller memorize the
external latch off function implemented in Pin 3.
This in−chip startup circuit can minimize the number of
external components and Printed Circuit Board (PCB) area.
It also minimizes the loss due to startup resistor because
startup resistor always dissipates power but this startup circuit
can be turned off when the VCC voltage is sufficient. Actually,
there is a small leakage current IHV3 (30 A typical at
HV = 700 V) when the startup circuit is off.
The VCC capacitor is recommended to be at least 47 F to
ensure that VCC is always above the minimum operating
voltage VCC2(off) (7.7 V typical) in the startup phase. For
18 V
Figure 49. Vaux Enabled Regions
Auxiliary Supply Vaux
The Vaux pin (Pin 1) connects to the VCC1 pin (Pin 8)
externally. Internally, the Vaux pin is connected to VCC2
through an internal MOSFET. The MOSFET on−resistance
is Raux (11.7 typical). It delivers a supply voltage from
the PWM section to the PFC section. The Vaux is disabled
when one of the following conditions occurs.
1. Vaux is initially disabled because of no feedback
signal (VFB2 > 3.0 V) initially.
2. Fault condition (VFB2 > 3.0 V for more than
125 ms).
3. Standby condition (VFB2 < Vstby (0.75 V typical)
and then VFB2 < Vstby−out (1.25 V typical) for
more than 125 ms).
4. Insufficient operating supply voltage (VCC2 <
VCC2(off) (7.7 V typical)).
5. Overvoltage protection (OVP) latch activated from
CS2 pin (Pin 3) (VCS2 > VOVP (3.0 V typical)).
6. Thermal shutdown latch in the PWM section
activated when the junction temperature is over
typical 150_C.
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NCP1603
Regulation in the PWM Section
The UVLO start thresholds of VCC1 is VCC1(on) (10.5 V
typical) and the maximum allowable limit is 18 V. On the
other hand, the Vaux is enabled when VCC2 is over VCC2(off)
(7.7 V typical). Hence, there are two possible operating
regions in Figure 49. In the non−usable region the Vaux is
not high enough to turn on the PFC section. Therefore, the
flyback transformer auxiliary winding must be between
VCC1(on) (10.5 V typical) and 18 V.
The PWM section (or the second stage) of the NCP1603
is NCP1230 that is a current−mode fixed−frequency PWM
flyback controller with internal compensation ramp. The
simplified block diagram of the duty cycle regulation
section is in Figure 50. A 100 kHz clock oscillator is
modulated by adding a frequency jittering feature. This
modulated 100 kHz clock signal turns the Out2 (pin 13)
high in each switching cycle. The Out2 goes low when the
current−loop feedback signal intersects with the output
voltage−loop feedback signal. A duty cycle is therefore
generated. The maximum duty ratio is limited to Dmax
(80% typical).
Vdd
Vout
20 k
FB2
2
VFB2
55 k
Opto
Coupler
25 k
Vbulk
VFB2
3
VFB2
3
Soft−Start
Processing
Circuit
1 V Max
Soft−Start Period 2.5 ms
+
200 ns
LEB
R
PWM
2.3 V
0V
100 kHz
Jittering Ramp
18 k
VCC2
Out2
13
Q
Flyback
Drain
Current
ID
S
Max Duty
= 80%
6.4% Frequency
Jittering
Modulation
CS2
3
RS2
RCS2
100 kHz
Oscillator
Figure 50. Block Diagram of Duty Cycle Regulation in the PWM Section
The current−loop feedback circuit consists of a typical
200 ns Leading Edge Blanking (LEB) that is to prevent a
premature reset of the output due to noise, a pair of sense
resistors RCS2 and RS2 that sense the flyback drain current
ID, and a 0−to−2.3 V jittering ramp that adds a ramp
compensation for a stability improvement to the
current−mode control possibly in continuous mode
operation.
The VFB2 is approximately divided by 3 by an internal
pair of resistors (55 k and 25 k). The soft−start
processing circuit reduces the initial voltage−loop
feedback signal (VFB2 / 3) for 2.5 ms. After this 2.5 ms, the
soft−start disappears. As a result, the startup envelope of
the peak drain current (or duty ratio) ramps up gradually for
2.5 ms. It is noted that the 2.5 ms is counted when the PWM
die circuit is reset that is when VCC2 reaches VCC2(on)
(12.6 V typical). This soft−start feature offers a reduced
transient voltage and current stress on the power circuit
during the startup.
Excessive output voltage causes more the optocoupler
current. It pulls down the VFB2 through FB2 pin (Pin 2) and
generates a lower duty ratio. The output voltage reduces.
Insufficient output voltage reduces the optocoupler
current. If the current is too small, the VFB2 is eventually
pulled high than 3.0 V (3.8 V typical). The (VFB2 /3) signal
is then clamped to an internal 1.0 V limit. If the ramp is
ignored (i.e., RS2 = 0), the maximum possible drain current
is derived as:
1V
ID(max) +
RCS2
(eq. 2)
It is noted that resistor RS2 will affect the percentage of
the ramp getting compared for the modulation. Hence, a
large value of the RS2 increase the ramp and will reduce the
possible maximum duty ratio.
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NCP1603
Frequency Jittering
Fault Condition
Figure 52 illustrates the fault detection circuitry and its
timing diagram. When fault (or output short circuit)
happens, the output voltage collapses and the optocoupler
is opened. VFB2 is internally pulled to be higher than 3.0 V
(3.8 V typical). Then, the controller activates an error flag
when (VFB2/3) is greater than the soft−start voltage VSS
that is 1.0 V after the 2.5 ms from startup.
When the circuit is powering up in the beginning, the
output voltage is not yet established and FB2 pin (Pin 2) is
opened. Therefore, there is a 125 ms timer to allow the
circuit to establish an initial output voltage. Then, a fault
(or short circuit) condition is recognized when an error flag
(VFB2 q 3.0 V) can last for 125 ms. When a fault is
detected, Out2 (Pin 13) goes low. The power supply stops
delivering power to the output. On the other hand, the Vaux
(= VCC1) also goes low. The Vaux will restore immediately
when the error flag disappears.
This fault detection method offers advantage of getting
rid of the auxiliary winding information that cannot truely
represent the output voltage when the flyback transformer
is badly coupled.
PWM Section Oscillator Frequency
106.4 kHz
100 kHz
93.6 kHz
5 ms
time
Figure 51. Frequency Jittering of PWM Oscillator
Frequency jittering is a method used to soften the EMI
signature by spreading the energy in the vicinity of the main
switching component. The PWM Section offers a typical
±6.4% deviation on the nominal switching frequency
(100 kHz typical). A sweep sawtooth modulates the
100 kHz clock up and down with a 5.0 ms period.
Figure 51 illustrates the ±6.4% variation of the jittering
oscillator frequency versus time.
Vdd
VFB2/3
20 k
FB2
2
1V
VFB2
55 k
25 k
VFB2
3
VSS
VSS
Start Vaux
Enable Vaux/PFC
+
-
Soft−Start
1 V Max
125 ms
Delay
&
1V
time
125ms
Fault
Disable
Vaux/PFC
and Out2
Vaux
Vaux starts when VFB2 is
within regulation window
(VFB2 < 3 V).
(i.e., normal operation)
Soft−Start Period 2.5 ms
time
Vaux stops when VFB2 is out of
regulation window (VFB2 > 3 V)
for more than 125 ms.
(i.e., fault condition)
Figure 52. Block Diagram and Timing Diagram of Fault Detection
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NCP1603
Startup current source
charging the VCC capacitor
Startup circuit turns off
when VCC2 is 12.6 V
12.6 V
Circuit sleeps when
VCC2 is below 7.7 V
VCC2
7.7 V
5.6 V
ID
Maximum drain current
is limited to 1 / RCS2
Startup circuit turns on
when VCC2 is 5.6 V
Peak drain current follows
a 2.5 ms soft−start envelope
time
0A
Switching starts when
VCC2 reaches 12.6 V
Switching is missing
in every two VCC hiccup cycles
featuring a “double hiccup”
Figure 53. Timing Diagram of Fault Condition
Figure 53 illustrates the timing diagram of VCC2 and the
second−stage drain current ID in fault condition. The VCC
drops because output voltage collapses. When VCC drops
below VCC(off) (7.7 V typical), the Drive Output signal
disappears and the VCC continues to drop. When bias
voltage VCC drops to VCC(latch) (5.6 V typical), the startup
current source activates and charge up the VCC until VCC
reaches VCC(on) (12.6 V typical). The internal 2.5 ms
soft−start activates after VCC reaches VCC(on) (12.6 V
typical). The peak drain current follows its 2.5 ms
envelope. The power supply dissipates some power due to
the switching signal of Out2 and waits for possible
auto−recovery of operation when the fault is cleared.
As shown in Figure 53, NCP1603 has a “double hiccup”
feature that allows the drain current in every two VCC
hiccup cycle in fault condition. The “double hiccup”
feature offers fewer power dissipation during fault
condition comparing to “single hiccup”.
If the fault is cleared (VFB2 < 3.0 VSS) and VCC remains
above VCC2(off) (7.7 V typical), the circuit will resume its
operation. Otherwise, the VCC will continue this
12.6−7.7−5.6−12.6 V hiccup mode until the fault or bulk
voltage is cleared.
FB2
2
V FB2
Leave standby
enable Vaux /
PFC Section
−
+
0.75 V / 1.25 V
125 ms
delay
&
Standby
disable
Vaux/
PFC
Section
VFB2
1.25 V
0.75 V
time
Vaux
125 ms
time
Vaux stops when VFB2 is
below 0.75 V and cannot go
above 1.25 V for 125 ms
Standby Condition
The output voltage rises up excessively in standby
condition and the VFB2 drops. A set point of 25% of the
maximum of VFB2 (i.e., 3.0 V) is defined to be the standby
threshold. Hence, the standby threshold is Vstby = 25% ×
3.0 V = 0.75 V.
Vaux restores when
VFB2 goes above 1.25 V
Figure 54. Block Diagram and Timing Diagram of
Standby Detection
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NCP1603
PFC in Discontinuous/Critical Mode
Figure 54 illustrates the standby detection circuitry and
its timing diagram. When standby condition happens (i.e.,
VFB2 < 0.75 V), the controller will wait for a typical 125 ms
to ensure that the output power remains low for a while.
Then, the Vaux is disabled to shut down the PFC section for
power saving. The Vaux (or the PFC) restores when VFB2
goes above 1.25 V immediately because VFB2 can be
possibly above the 0.75 V threshold during standby
operation (referring to Figure 55) and the PFC section is
needed after the circuit restores from standby condition.
VCC2
The PFC section of the NCP1603 is NCP1601 that is
designed for low−power PFC boost circuit in DCM or CRM
and takes advantages on both operating modes. DCM limits
the maximum switching frequency. It simplifies the
front−ended EMI filter design. CRM limits the maximum
currents of diode, MOSFET and inductor. It reduces the
costs and improves the reliability of the circuit. This device
substantially exhibits unity power factor while operating in
DCM and CRM. It minimizes the number of external
components.
The PFC section primarily designed to operate in
fixed−frequency DCM. In the most stressful conditions,
CRM can be an alternative option that is without power
factor degradation. On the other hand, the PFC section can
be viewed as a CRM controller with a frequency clamp
(maximum switching frequency limit) alternative option
that is also without power factor degradation. In summary,
the PFC section can cover both CRM and DCM without
power factor degradation. Based on the selections of the
boost inductor and the oscillator frequency, the circuit is
capable of the following three applications.
1. CRM only by setting the oscillator frequency
higher than the CRM frequency range.
2. CRM and DCM by setting the oscillator
frequency somewhere within the CRM frequency
range.
3. DCM only by setting the oscillator frequency
lower than the CRM frequency range.
VCC2 needs to be above 7.7 V to ensure
proper operation of the controller and
main output within regulation
7.7 V
Out2 goes low (no drain current) when VFB2 < 0.75 V
1.25 V
0.75 V
VFB2
ID
time
Figure 55. Timing Diagram in Standby Condition
FB2 2
VFB2
− Standby
+
+
− 0.75 V
CS2 3
PWM
Vcc2
OR
R Q
S
Vin
Out2
13
time
Vcontrol
clock
time
Vton
Figure 56. Block Diagram in Standby Operation in
PWM Section
time
Figure 55 and 56 show the timing diagram and block
diagram of the standby operation respectively. A skipping
cycle behavior of the drain current is made by reset the
latch whenever VFB2 is smaller than 0.75 V. When VFB2 is
greater than 0.75 V, the duty ratio is modulated by the
PWM block that is illustrated in Figure 50.
Inductor current, IL
current
Input current, Iin
time
DCM
critical mode
DCM
Figure 57. Timing Diagram of the PFC Stage
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NCP1603
case of DCM when t3 = 0. When the PFC boost converter
MOSFET is on, the inductor current IL increases from zero
to Ipk for a time duration t1 with inductance L and input
voltage Vin. Equation 3 is formulated.
DCM needs higher peak inductor current comparing to
CRM in the same averaged input current. Hence, CRM is
generally preferred at around the sinusoidal peak for lower
the maximum current stress but DCM is also preferred at
the non−peak region to avoid excessive switching
frequencies. Because of the variable−frequency feature of
the CRM and constant−frequency feature of DCM,
switching frequency is the maximum in the DCM region
and hence the minimum switching frequency will be found
at the moment of the sinusoidal peak.
Ipk
Vin + L
t1
The input filter capacitor Cfilter and the front−ended EMI
filter absorb the high−frequency component of inductor
current. It makes the input current Iin a low−frequency
signal.
DCM PFC Circuit
Iin +
A DCM/CRM PFC boost converter is shown in
Figure 58. Input voltage is a rectified 50 or 60 Hz
sinusoidal signal. The MOSFET is switching at a high
frequency (typically around 100 kHz) so that the inductor
current IL basically consists of high−frequency and
low−frequency components.
Iin
IL
(eq. 4)
(eq. 5)
From Equations 3, 4, and 5, the input impedance Zin is
formulated.
Vout
Cfilter
Ipk (t1 ) t2)
for DCM
2T
Ipk
Iin +
for CRM
2
L
Vin
(eq. 3)
Cbulk
V
2TL
Zin + in +
for DCM
Iin
t1(t1 ) t2)
(eq. 6)
V
Zin + in + 2L for CRM
t1
Iin
(eq. 7)
Power factor is corrected when the input impedance Zin
in Equations 6 and 7 are constant or slowly varying.
Figure 58. DCM/CRM PFC Boost Converter
Ich
Ramp
Filter capacitor Cfilter is an essential and very small value
capacitor in order to eliminate the high−frequency content
of the DCM inductor current IL. This filter capacitor cannot
be too bulky because it can pollute the power factor by
distorting of the rectified sinusoidal input voltage.
12
closed when
output low
Cramp
PWM
Comparator
+
−
Vton
Turns off
MOSFET
PFC Methodology
The PFC section uses a proprietary PFC methodology
particularly designed for both DCM and CRM operation.
The PFC methodology is described in this section.
Vton
ramp
out1
Figure 60. PFC Modulation Circuit and Timing
Diagram
Inductor Current
The MOSFET on time t1 of PFC modulation duty is
generated by a feedback signal Vton and a ramp. The PFC
modulation circuit and timing diagram are shown in
Figure 60. A relationship in Equation 8 is obtained.
Ipk
t1 +
t1
t2
t3
Cramp Vton
Ich
(eq. 8)
The charging current Ich is constant 100 A current and
the ramp capacitor Cramp is constant for a particular design.
Hence, according to Equation 8, the MOSFET on time t1
is proportional to Vton.
In order to protect the PFC modulation comparator, the
maximum voltage of Vton is limited to internal clamp
Vton(max) (3.9 V typical) and the ramp pin (Pin 12) is with
time
T
Figure 59. Inductor Current in DCM
As shown in Figure 59, the inductor current IL of each
switching cycle starts from zero in DCM. CRM is a special
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NCP1603
a 9.0 V ESD zener diode. The 3.9 V maximum limit of this
Vton indirectly limits the maximum on time.
The Vcontrol processing circuit generates Vton from
control voltage Vcontrol and time information of zero
inductor current. The circuit in Figure 61 makes
Equations 9 and 10 where the value of resistor R1 is much
higher than the value of resistor R2 (R1 >> R2).
Vreg
96% Iref
300k
Iref IFB1
Vcontrol
Processing
Circuit
Regulation Block
Vcontrol
closed when zero current
10
Ccontrol
R1
R2
Figure 62. Vcontrol Low−Pass Filtering
C1
Vcontrol
10
−
+
R3
If the bandwidth of Vcontrol is much less than the 50 or
60 Hz line frequency, the input impedance Zin is slowly
varying or roughly constant. Then, the power factor
correction is achieved in DCM and CRM.
Vton
C3
Ccontrol
Maximum Power in PFC Section
Input and output power (Pin and Pout) are derived in
Equations 13 and 14 when the circuit efficiency η is
obtained or assumed. The variable Vac stands for the RMS
input voltage.
Figure 61. Vcontrol Processing Circuit
Vton +
T Vcontrol
for DCM
t1 ) t2
Vton + Vcontrol for CRM
(eq. 9)
Vac2CrampVcontrol
V 2
Pin + ac +
Zin
2LIch
(eq. 10)
It is noted that Vton is always greater than or equal to
Vcontrol (Vton q Vcontrol).
In summary, the input impedance Zin in Equation 11 is
obtained from Equations 3 through 10.
2LIch
V
Zin + in +
Iin
Cramp Vcontrol
Pout + Pin +
(eq. 14)
From Equations 13 and 14, control voltage Vcontrol
controls the amount of output power, input power, or input
impedance. The maximum value of the control voltage
Vcontrol is 1.05 V (i.e., Vcontrol(max) = 1.05 V). A parameter
called maximum power resistor Rpower (10.5 k typical) is
defined in Equation 18 and restricted to have a maximum
±10% variation (i.e., 9.5 k p Rpower p 11.5 k) for
defining the maximum power in an application.
(eq. 11)
Control voltage Vcontrol comes from the PFC boost
circuit output voltage (i.e., bulk voltage Vbulk) that is a
slowly varying signal. The bandwidth of Vcontrol can be
additionally limited by inserting an external capacitor
Ccontrol to the Vcontrol pin (Pin 10) in Figure 62. The
internal 300 k resistor and the capacitor Ccontrol create a
low−pass filter that has a bandwidth fcontrol in Equation 12.
It is generally recommended to limit the bandwidth below
20 Hz to achieve power factor correction. Typical value of
Ccontrol is 0.1 F.
1
Ccontrol u
2300k fcontrol
Vac2CrampVcontrol
2LIch
(eq. 13)
Rpower +
1.05 V
Vcontrol(max)
+
+ 10.5 k
Ich
100 A
(eq. 15)
It means that the maximum input and output power
(Pin(max) and Pout(max)) are limited to ±10% variation.
Pin(max) +
(eq. 12)
Vac2CrampRpower
2L
Pout(max) +
Vac2CrampRpower
2L
(eq. 16)
(eq. 17)
The maximum input current Iac(max) to deliver the
maximum input power Pin(max) is also derived in (eq.14).
The suffix ac stands for RMS value.
Iac(max) +
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Pin(max)
VacCrampRpower
+
Vac
2L
(eq. 18)
NCP1603
Feedback in PFC Section
The feedback resistor RFB1 consists of two or three high
precision resistors in order to set the nominal Vbulk
precisely and for safety purpose.
The regulation block output Vreg is connected to control
voltage Vcontrol through an internal resistor Rcontrol
(300 k typical) for the low−pass filter in Figure 62. The
Vcontrol and the time information of zero current are
collected in the Vcontrol processing circuit to generate Vton
that is then compared to a ramp signal to generate the
MOSFET on time t1 for power factor correction.
The output voltage of the PFC circuit (i.e., bulk voltage
Vbulk) is sensed as a feedback current IFB1 flowing into the
FB1 pin (Pin 9) of NCP1603. The FB1 pin voltage VFB1 is
typically smaller than 5.0 V referring to Figure 31. It is
much lower than Vbulk that is typically 400 V. Therefore,
VFB1 is generally neglected.
V
* VFB1
V
IFB1 + bulk
[ bulk
RFB1
RFB1
(eq. 19)
where RFB1 is the feedback resistor connected the FB1 pin
(Pin 9) and the output voltage referring to Figure 45.
Then, the feedback current IFB1 represents the bulk
voltage Vbulk and will be used in the PFC section voltage
regulation, undervoltage protection (UVP), and
overvoltage protection (OVP).
Current Sense in PFC Section
The PFC section senses the inductor current IL by the
current sense scheme in Figure 64. This scheme has the
advantages of: (1) the inrush current limitation by the
resistor. RCS1. and (2) the overcurrent protection and zero
current detection implemented in the same pin.
Bulk Voltage Regulation in PFC Section
PFC−stage feedback current IFB1, that presents bulk
voltage Vbulk or the PFC−stage output voltage, is regulated
with a reference current (Iref = 203 A typical) as shown in
Figure 63. When IFB1 is lower than 96% of Iref, the Vreg that
is the output of the regulation block is as high as
Vcontrol(max) (1.05 V typical) that it gives the maximum
value on Vton and the maximum MOSFET on time and
Vbulk increases. When IFB1 is higher than Iref, the Vreg
becomes 0 V that gives no MOSFET on time and Vbulk
decreases. As a result, the bulk voltage Vbulk is regulated
around the range between 96% and 100% of the nominal
value of RFB1 × Iref.
IL
RS1
RCS1
IL
VS
−
NCP1603
Gnd1
Figure 64. Current Sense in PFC Section
Inductor current IL passes through RCS1 and creates a
negative voltage. This voltage is measured by a current IS
flowing out of the CS1 pin (Pin 11). CS1 pin has an offset
voltage VS. This offset voltage is studied in the setting of
zero inductor current IL(ZCD) and the maximum inductor
current IL(OCP) (i.e., overcurrent protection threshold). A
typical variation of offset voltage VS versus sense current
IS is shown in Figure 35. Based on Figure 64, Equation 20
is derived.
1V
Iref
CS1
+
Vreg
96% Iref
IS
IFB1
Figure 63. Regulation Block
Based on Equations 13 and 14 for a particular power
level, the Vcontrol is inversely proportional to Vac2. Hence,
in high Vac condition Vcontrol is lower. It means that IFB1 or
output voltage is higher based on the regulation block
characteristic in Figure 63. In other words, the Vcontrol in
the low Vac condition is much higher than the high Vac
condition. In order to not over−design the circuit in the
application, the Vcontrol in the low Vac condition is usually
very closed to Vcontrol(max). It makes the output voltage be
almost 96% of the nominal value of RFB1 × Iref in high Vac
condition.
VS * RS1 IS + −RCS1 IL
(eq. 20)
Zero Current Detection (ZCD) in PFC Section
The device recognizes zero inductor current when CS1
pin (Pin 11) sense current IS is smaller than IS(ZCD) (14 A
typical). The offset voltage of the CS1 pin in this condition
is VS(ZCD) (7.5 mV typical). The inductor current IL(ZCD)
at the ZCD condition is derived in Equation 21.
IL(ZCD) +
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RS1IS(ZCD) * VS(ZCD)
RCS1
(eq. 21)
NCP1603
It is obvious that the IL(ZCD) is not always zero. In order
to make it reasonably close to zero, the setting of RS1 and
RCS1 are crucial.
VS
IL = 0
VS
VS(ZCD)
Operating ZCD point
IS
RS1 = RS(ZCD)
Figure 66. CS Pin Characteristic with Different
Inductor Current
IS
It is noted in Figure 66 and Equation 23 that when the
(RCS1 IL) term is smaller the error or distance between the
lines to the line IL = 0 is smaller. Therefore, the value of the
current sense resistor RCS1 is also recommended to be as
small as possible to minimize the error in the zero current
detection.
IS(ZCD)
Figure 65. CS Pin Characteristic when IL = 0
Based on the CS pin (Pin 4) characteristics in Figure 35,
Figure 65 is studied here. When the inductor current is
exactly zero (i.e., IL(ZCD) = 0), the ideal ZCD point in the
Figure 65 is reached where RS1 is RS(ZCD) (536 typical).
Considering the tolerance, the actual sense resistor RS1 is
needed to be higher than the ideal value of RS(ZCD) to
ensure that zero current signal is generated when sense
current is smaller than the ZCD threshold (i.e., IS <
IS(ZCD)). That is,
Overcurrent Protection (OCP) in PFC Section
Overcurrent protection is reached when IS is larger than
IS(OCP) (200 A typical). The offset voltage of the CS pin
is VS(OCP) (3.2 mV typical) in this condition. That is:
IL(OCP) +
(eq. 22)
RS1IS(OCP) * VS(OCP)
RCS1
(eq. 24)
When overcurrent protection threshold is reached, the
Drive Output of the device goes low.
The higher value of RS1 makes the bigger distance
between the operating and ideal ZCD points in Figure 65.
Hence, RS1 has to be as low value as possible. The best
recommended value of RS1 is therefore the maximum of
RS(ZCD) that is 1.0 k.
Now that the RS1 is set at a particular value that is greater
than RS(ZCD). From Equation 20, the operating lines in
Equation 23 with different inductor currents IL of
Equation 20 are studied.
VS + RS1IS * RCS1IL
Operating
ZCD point
IS(ZCD)
Ideal ZCD point
VS(ZCD)
RS u RS(ZCD) +
IS(ZCD)
IL > IL(ZCD)
Best
ZCD
point
RS1 > RS(ZCD)
VS(ZCD)
IL = IL(ZCD)
Oscillator/Synchronization Block in PFC Section
Oscillator Clock
45 A
Osc 5
+
−
94 A
(eq. 23)
0
These operating lines are added in Figure 65 to formulate
Figure 66. When the inductor current IL is smaller than
IL(ZCD), the sense current IS is smaller than IS(ZCD) and
hence the zero current signal is generated.
5 V/3.5 V
1
Zero Current
S Q
&
Turn on
MOSFET
R
delay
Figure 67. Oscillator / Synchronization Block
in PFC Section
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NCP1603
The PFC section is designed to operate in either DCM or
CRM. In order to keep the operation in DCM and CRM
only, the Drive Output cannot turn on as long as there is
some inductor current flowing through the circuit. Hence,
the zero current signal is provided to the oscillator/
synchronization block in Figure 67. An input comparator
monitors the Osc pin (Pin 5) voltage and generates a clock
signal. The negative edge of the clock signal is stored in a
RS latch. When zero current is detected, the RS latch will
be reset and a set signal is sent to the output drive latch that
turns on the MOSFET in the PFC boost circuit. Figure 68
illustrates a typical timing diagram of the oscillator block.
C osc , Oscillator Capacitor (pF)
700
600
500
400
300
200
100
0
0
200
Figure 70. Osc Pin Frequency Setting
clock
clock edge
(latch set signal)
Synchronization Option
clock latch
(latch output)
In synchronization mode, the Osc pin (Pin 5) receives an
external digital signal with level high defined to be higher
than Vsync(H) (5.0 V typical) and level low defined to be
lower than Vsync(L) (3.5 V typical). An internal 9.0 V ESD
Zener diode is connected to the Osc pin and hence the
maximum allowable synchronization voltage is 9.0 V. The
circuit recognizes a synchronization frequency by the time
difference between two falling edge instants when the
synchronization signal across the 3.5 V threshold point.
The actual synchronization threshold point is a little bit
higher than the 3.5 V threshold point. The minimum
synchronization pulse width is 500 ns.
There is a typical 350 ns propagation delay from
synchronization threshold point to the moment of output goes
high and there is also a typical 300 ns propagation delay from
the synchronization threshold point to the moment of crossing
3.5 V. Hence, the output goes high apparently when the sync
signal turns to 3.5 V. A timing diagram of synchronization
mode is summarized in Figure 71.
inductor
current
Discontinuous mode
time
Critical mode
Figure 68. Oscillator Block Timing Diagram
Oscillator Mode in PFC Section
In oscillator mode, the Osc pin (Pin 5) is connected to an
external capacitor Cosc. When the voltage of this pin is above
Vsync(H) (5.0 V typical), the pin sinks a current Iodch (94–45
= 49 A typical) and the external capacitor Cosc discharges.
When the voltage reaches Vsync(L) (3.5 V typical), the pin
sources a current Ioch (45 A typical) and the external
capacitor Cosc is charged. It is noted that there is a typical
300 ns propagation delay and the 3.5 V and 5.0 V threshold
conditions are measured on 220 pF Cosc capacitor. Hence, the
actual oscillator hysteresis is a little bit smaller.
Sync Signal
5V
3.5 V
Osc pin
voltage
5V
3.5 V
Osc Clock
Osc clock
Clock Edge
Clock edge
Drive Output
(DCM)
Drive output
(DCM)
Figure 71. Synchronization Mode Timing Diagram in
DCM
Figure 69. Oscillator Mode Timing Diagram in DCM
The PWM and PFC Section can be synchronized
together in order to minimize some of the ripple current in
the bulk capacitor as shown in Figure 72 and 73. The Out2
pin (Pin 13) is the external synchronization signal in
Figure 71 to the PFC Section. When the Out2 is in high
state, the voltage is potentially higher than the maximum
allowable voltage in Osc pin (Pin 5). Hence, a pair of
resistors divides the voltage from Out2 reduces the voltage
There is an internal capacitance Cosc(int) (36 pF typical)
in the oscillator pin and the oscillator frequency is to
fosc(max) (405 kHz typical) when the Osc pin is opened.
Hence, the oscillator switching frequency can be
formulated in Equation 25 and represented in Figure 70.
Cosc +
50
100
150
f osc , Oscillator Frequency (kHz)
36 pF @ 405 kHz
fosc
* 36 pF
(eq. 25)
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NCP1603
Safety Features of NCP1603
OSC
NCP1603
entering Osc pin and a capacitor is added to remove some
possible noise As a result, the current in Figure 73 may not
necessarily passes through the bulk capacitor for fewer
ripple current there.
(1) Bulk Voltage Overvoltage Protection (OVP)
When the PFC feedback current IFB1 is higher than 107%
of the reference current Iref (i.e., the bulk voltage Vbulk is
higher than 107% of its nominal value), the PFC Drive
Output pin (Pin 7) of the device goes low for protection and
the switch of the Vcontrol processing circuit is kept off. The
circuit automatically resumes operation when the output
voltage is lower than 107%.
The maximum OVP threshold is limited to 225 A that
corresponds to 225 A × 1.95 M + 5.0 V = 443.75 V
when RFB1 = 1.95 M (e.g., 910 k + 910 k + 130 k)
and VFB1 = 5.0 V (for the worst case referring to
Figure 31). Hence, it is generally recommended to use
450 V rating output capacitor to allow some design margin.
Out2
(2) Bulk Voltage Undervoltage Protection (UVP)
When the PFC feedback current IFB1 is smaller than 8%
of the reference current Iref, the PFC section is shutdown
and consumes less than 50 A. In normal situation of the
boost converter configuration, the output bulk voltage
Vbulk is always higher than input voltage Vin and the IFB1
is higher than 8% of the reference current. It enables the
PFC section to operate. Hence, UVP happens when the
bulk voltage Vbulk is abnormally under−voltage, the FB1
pin (Pin 9) is opened, or the FB1 pin (Pin 9) is manually
pulled low.
Figure 72. Synchronization Configuration
PWM drive
PFC drive
(DCM)
current
(3) PFC−Stage Overcurrent Protection
When the PFC sense current IS1 is higher than typically
200 A, the PFC Drive Output (Pin 7) goes low. It
represents the PFC−stage inductor current iL exceeds a
user−defined value. The operation automatically resumes
when the inductor current becomes lower than this
user−defined value at the next clock cycle.
Phase 1
(4) PWM−Stage Short−Circuit Protection
When VFB2 remains higher than 3.0 V for 125 ms, a fault
is recognized. The PFC−stage (i.e., Vaux) will be disabled
and the VCC2 will operate a double hiccup shown in
Figure 53. The operation will be self−recovered if VCC2 is
above 7.7 V and VFB2 is below 3.0 V. This fault protection
is implemented by a timer and independent of badly
coupled auxiliary transformer winding.
current
Phase 2
Figure 73. Synchronization Timing Diagram
(5) Latched VCC Overvoltage Protection
Output Drive
The normal operating voltage range of the CS2 pin
(Pin 3) is between 0 V and Ilimit (1.0 V typical). When the
voltage is above 1.0 V, the Out2 (Pin 13) goes low. When
the voltage increases above 3.0 V, the Out2 goes low and
stays latched off until the circuit is reset by unplugging
from main supply to make VCC2 drop below VCC(reset)
(4.0 V typical). This feature also offers the designer the
flexibility to implement an externally pull−high latched
protection or latched shutdown circuit.
The output stages of the PFC section and PWM section are
designed for direct drive of power MOSFET. However, it is
recommended to connect a current limiting resistor to the gate
of the power MOSFET. The PFC section output is capable of
up to −500 mA and +750 mA peak drive current and has a
typical rise and fall time of 53 and 32 ns with a 1.0 nF load
while the PWM section output is capable of up to "1.0 A
peak drive current and has a typical rise and fall time of 40 ns
and a fall time of 15 ns with a 1.0 nF capacitive load.
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27
NCP1603
leakage current of the zener diode due to temperature
variation. The Zener diode at the output voltage is
recommended to be a 1 mA operating current at the
threshold voltage. Then, this current is coupled through the
optocoupler and inserts a similar order of current
(depending on the current−transfer−ratio CTR of the
optocoupler) into CS2 pin. The CS2 pin is capable of up to
100 mA and with an internal 9 V anti−parallel ESD diode
but it is recommended to put a 8.2 V Zener diode there to
further protect the pin.
In order to prevent wrongly triggering the latch
protection function, it is generaly recommended to put a
pF−order decoupling ceramic capacitor across the CS2 pin
to remove possible high−frequency noise there.
To set the VCC overvoltage protection, the circuit is
configured in Figure 74. A PNP bipolar transistor is added
to open the Zener diode ZOVP when Out2 is high in order
to stop any interference of the normal operation of current
sense. It is because the Zener diode easily pulls high the
CS2 pin voltage to 1.0 V and that interferes with the normal
operation of the current sense when the output is high. The
OVP threshold VCC2(OVP) is expressed in Equation 26.
VCC2
CS2
NCP1603
VCC2
NCP1603
(eq. 26)
VCC2(OVP) + VZOVP ) 3 V
CS2
Vout
ZOVP
ZOVP
RS2
RCS2
RS2
Figure 75. Output Latched OVP Application Circuit
RCS2
(7) Dual Thermal Shutdown (TSD)
The NCP1603 consists of two individual dies that
incorporates their individual thermal shutdown. The PFC
thermal circuitry disables the PFC gate drive Out1 and then
keeps the power switch off when its junction temperature
exceeds 170 °C typically. The PFC gate drive Out1 is then
enabled once the temperature drops below typically 125°C
(i.e., 45°C hysteresis).
The PWM thermal circuitry disables the PWM gate drive
Out2 and then keeps the power switch off when its junction
temperature exceeds 165°C typically. The PWM gate drive
Out2 is then enabled once the temperature drops below
typically 140°C and the circuit is unplugged (to make VCC2
drops below 4.0 V).
Figure 74. VCC Latched OVP Application Circuit
(6) Latched Overvoltage Protection (OVP)
As long as an external protection on CS2 pin (Pin 3) does
not affect the normal regulation operation of current sense,
the protection can be implemented. An alternative is to
implement the output overvoltage protection by an
optocoupler in Figure 75. The leakage current of the added
circuit is up to the zener diode at the output voltage. When
there is no overvoltage, the leakage is small and it does not
affect the normal operation. A resistor paralleled to the
optocoupler is added to share the potential increasing
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28
NCP1603
PFC Toggling
Vaux
The variation of the duty ratio in the PWM stage between
the PFC−on or PFC−off can be very large. When the
NCP1603 circuit is operating at some conditions between
PFC on and off boundary, the duty ratio variation can lead
to unwanted on/off toggling in the PFC stage. A current
feedforward resistor RFF is hence recommended to added
between Vaux and CS2 pin (pins 1 and 3) in Figure 76 to
prevent the toggling. The value of RFF is much larger than
current sense feedback resistor RS2 and plays very little
effect when Vaux = 0 (or PFC is off). When Vaux is available
(or PFC is on), the RFF creates a positive offset on the CS2
pin voltage and it allows the feedback voltage VFB2 to only
shift slightly but provide a dramatic duty cycle reduction
in Figure 77. It slight movement of the feedback voltage
can reduce the change to reach the PFC stage on/off
threshold. Hence, the current feedforward resistor can help
to improve the toggling.
VFB2
3
VCS2
Out 2
High duty when PFC is off.
Figure 77. Timing Diagram of PWM Stage When RFF
is Added
Vbulk
CS2
NCP1603
Vaux
RFF
Low duty when PFC is on.
RS2
Figure 76. Feedforward Resistor RFF Added
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NCP1603
PACKAGE DIMENSIONS
SO−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
16
9
1
8
−B− P
8 PL
0.25 (0.010)
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
S
The products described herein (NCP1603), may be covered by one or more of the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,597,221,
6,970,365. There may be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
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