NCP1608BDR2G

NCP1608 Critical Conduction Mode PFC Controller Utilizing OTA The NCP1608 is an active power factor correction (PFC) controller specifically designed for use as a pre−converter in ac−dc adapters, electronic ballasts, and other medium power off−line converters (typically up to 350 W). It uses Critical Conduction Mode (CrM) to ensure near unity power factor across a wide range of input voltages and output power. The NCP1608 minimizes the number of external components by integrating safety features, making it an excellent choice for designing robust PFC stages. It is available in a SOIC−8 package. General Features http://onsemi.com MARKING DIAGRAM 1 SOIC−8 D SUFFIX CASE 751 A L Y W G 8 1608B ALYW G 8 • Near Unity Power Factor • No Input Voltage Sensing Requirement • Latching PWM for Cycle−by−Cycle On Time Control (Voltage • Wide Control Range for High Power Application (>150 W) Noise • • • • • • • • • • • • • • • • • Immunity Transconductance Amplifier High Precision Voltage Reference (±1.6% Over the Temperature Range) Very Low Startup Current Consumption (≤ 35 mA) Low Typical Operating Current Consumption (2.1 mA) Source 500 mA / Sink 800 mA Totem Pole Gate Driver Undervoltage Lockout with Hysteresis Pin−to−Pin Compatible with Industry Standards This is a Pb−Free and Halide−Free Device Overvoltage Protection Undervoltage Protection Open/Floating Feedback Loop Protection Overcurrent Protection Accurate and Programmable On Time Limitation Solid State Lighting Electronic Light Ballast AC Adapters, TVs, Monitors All Off−Line Appliances Requiring Power Factor Correction Mode) 1 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTION FB Control Ct CS (Top View) VCC DRV GND ZCD ORDERING INFORMATION Device NCP1608BDR2G Package SOIC−8 (Pb−Free) Shipping† 2500 / Tape & Reel Safety Features †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Typical Applications © Semiconductor Components Industries, LLC, 2009 April, 2009 − Rev. 0 1 Publication Order Number: NCP1608/D NCP1608 Vin L NB:NZCD RZCD + AC Line EMI Filter Cin Rout1 1 2 Rout2 CCOMP Ct 3 4 NCP1608 FB VCC Control DRV Ct CS GND ZCD D Vout LOAD (Ballast, SMPS, etc.) + VCC 8 7 6 5 Rsense M Cbulk Figure 1. Typical Application + Vout Cbulk + OVP − POK + (Enable EA) + UVLO VCC VDD VDDGD VDD Reg VCC Rout1 FB Rout2 VOVP − UVP + + VUVP E/A − + RFB + D gm Fault mVDD VREF Haversine L Vin Control CCOMP VControl VEAH Clamp VDD Icharge PWM Add Ct Offset − + SQ RQ VCC SQ RQ Reset SQ Off Timer mVDD RQ SQ RQ All SR Latches are Reset Dominant POK + − VZCD(TRIG) Demag UVLO SQ RQ VDDGD mVDD GND DRV NB:NZCD Ct Ct M CS POK DRV LEB + + − VZCD(ARM) + + OCP − VILIM Rsense + ZCD RZCD ZCD Clamp Figure 2. Block Diagram http://onsemi.com 2 NCP1608 Table 1. PIN FUNCTION DESCRIPTION Pin 1 Name FB Function The FB pin is the inverting input of the internal error amplifier. A resistor divider scales the output voltage to VREF to maintain regulation. The feedback voltage is used for overvoltage and undervoltage protections. The controller is disabled when this pin is forced to a voltage less than VUVP, a voltage greater than VOVP, or floating. The Control pin is the output of the internal error amplifier. A compensation network is connected between the Control pin and ground to set the loop bandwidth. A low bandwidth yields a high power factor and a low Total Harmonic Distortion (THD). The Ct pin sources a current to charge an external timing capacitor. The circuit controls the power switch on time by comparing the Ct voltage to an internal voltage derived from VControl. The Ct pin discharges the external timing capacitor at the end of the on time. The CS pin limits the cycle−by−cycle current through the power switch. When the CS voltage exceeds VILIM, the drive turns off. The sense resistor that connects to the CS pin programs the maximum switch current. The voltage of an auxiliary winding is sensed by this pin to detect the inductor demagnetization for CrM operation. The GND pin is analog ground. The integrated driver has a typical source impedance of 12 W and a typical sink impedance of 6 W. The VCC pin is the positive supply of the controller. The controller is enabled when VCC exceeds VCC(on) and is disabled when VCC decreases to less than VCC(off). 2 3 Control Ct 4 5 6 7 8 CS ZCD GND DRV VCC Table 2. MAXIMUM RATINGS Rating FB Voltage FB Current Control Voltage Control Current Ct Voltage Ct Current CS Voltage CS Current ZCD Voltage ZCD Current DRV Voltage DRV Sink Current DRV Source Current Supply Voltage Supply Current Power Dissipation (TA = 70°C, 2.0 Oz Cu, 55 mm2 Printed Circuit Copper Clad) Thermal Resistance Junction−to−Ambient (2.0 Oz Cu, 55 mm2 Printed Circuit Copper Clad) Junction−to−Air Low conductivity PCB (Note 3) , Junction−to−Air High conductivity PCB (Note 4) , Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 s) Symbol VFB IFB VControl IControl VCt ICt VCS ICS VZCD IZCD VDRV IDRV(sink) IDRV(source) VCC ICC PD RqJA RqJA RqJA TJ TJ(MAX) TSTG TL Value −0.3 to 10 ±10 −0.3 to 6.5 −2 to 10 −0.3 to 6 ±10 −0.3 to 6 ±10 −0.3 to 10 ±10 −0.3 to VCC 800 500 −0.3 to 20 ±20 450 178 168 127 −40 to 125 150 −65 to 150 300 °C °C °C °C Unit V mA V mA V mA V mA V mA V mA mA V mA mW °C/W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Pins 1– 8: Human Body Model 2000 V per JEDEC Standard JESD22−A114E. Pins 1– 8: Machine Model Method 200 V per JEDEC Standard JESD22−A115−A. 2. This device contains Latch−Up protection and exceeds ± 100 mA per JEDEC Standard JESD78. 3. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 80 mm2 of 2 oz copper traces and heat spreading area. As specified for a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection or zero air flow. 4. As mounted on a 40x40x1.5 mm FR4 substrate with a single layer of 650 mm2 of 2 oz copper traces and heat spreading area. As specified for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection or zero air flow. http://onsemi.com 3 NCP1608 VFB = 2.4 V, VControl = 4 V, Ct = 1 nF, VCS = 0 V, VZCD = 0 V, CDRV = 1 nF, VCC = 12 V, unless otherwise specified (For typical values, TJ = 25°C. For min/max values, TJ = −40°C to 125°C, unless otherwise specified) Characteristic STARTUP AND SUPPLY CIRCUITS Startup Voltage Threshold Minimum Operating Voltage Supply Voltage Hysteresis Startup Current Consumption No Load Switching Current Consumption Switching Current Consumption Fault Condition Current Consumption 0 V < VCC < VCC(on) − 200 mV CDRV = open, 70 kHz Switching, VCS = 2 V 70 kHz Switching, VCS = 2 V No Switching, VFB = 0 V VFB = Increasing VFB = 2 V to 3 V ramp, dV/dt = 1 V/ms VFB = VOVP to VDRV = 10% VFB = Decreasing VFB = 1 V to 0 V ramp, dV/dt = 10 V/ms VFB = VUVP to VDRV = 10% VCC Increasing VCC Decreasing VCC(on) VCC(off) HUVLO Icc(startup) Icc1 Icc2 Icc(fault) VOVP/VREF VOVP(HYS) tOVP 11 8.8 2.2 − − − − 12 9.5 2.5 24 1.4 2.1 0.75 12.5 10.2 2.8 35 1.7 2.6 0.95 V V V mA mA mA mA Test Conditions Symbol Min Typ Max Unit Table 3. ELECTRICAL CHARACTERISTICS OVERVOLTAGE AND UNDERVOLTAGE PROTECTION Overvoltage Detect Threshold Overvoltage Hysteresis Overvoltage Detect Threshold Propagation Delay Undervoltage Detect Threshold Undervoltage Detect Threshold Propagation Delay ERROR AMPLIFIER Voltage Reference Voltage Reference Line Regulation Error Amplifier Current Capability TJ = 25°C TJ = −40°C to 125°C VCC(on) + 200 mV < VCC < 20 V VFB = 2.6 V VFB = 1.08*VREF VFB = 0.5 V VFB = 2.4 V to 2.6 V TJ = 25°C TJ = −40°C to 125°C VFB = VUVP to VREF VFB = 2.5 V VFB = 0 V IControl(pullup) = 10 mA, VFB = VREF VControl = Decreasing until VDRV is low, VCt = 0 V VEAH – Ct(offset) VREF VREF(line) IEA(sink) IEA(sink)OVP IEA(source) gm 90 70 RFB IFB IControl VEAH Ct(offset) VEA(DIFF) 2 0.25 −1 5 0.37 4.5 110 110 4.6 0.54 − 5.5 0.65 4.9 120 135 10 1.25 1 6 0.88 5.3 MW mA mA V V V 2.475 2.460 −10 6 10 −110 2.500 2.500 − 10 20 −210 2.525 2.540 10 20 30 −250 V mV mA 105 20 − 106 60 500 108 100 800 % mV ns VUVP tUVP 0.25 100 0.31 200 0.4 300 V ns Transconductance mS Feedback Pin Internal Pull Down Resistor Feedback Bias Current Control Bias Current Maximum Control Voltage Minimum Control Voltage to Generate Drive Pulses Control Voltage Range http://onsemi.com 4 NCP1608 Table 3. ELECTRICAL CHARACTERISTICS (Continued) VFB = 2.4 V, VControl = 4 V, Ct = 1 nF, VCS = 0 V, VZCD = 0 V, CDRV = 1 nF, VCC = 12 V, unless otherwise specified (For typical values, TJ = 25°C. For min/max values, TJ = −40°C to 125°C, unless otherwise specified) Characteristic RAMP CONTROL Ct Peak Voltage On Time Capacitor Charge Current Ct Capacitor Discharge Duration PWM Propagation Delay VControl = open VControl = open VCt = 0 V to VCt(MAX) VControl = open VCt = VCt(MAX) −100 mV to 500 mV dV/dt = 30 V/ms VCt = VControl − Ct(offset) to VDRV = 10% VCt(MAX) Icharge tCt(discharge) tPWM 4.775 235 − − 4.93 275 50 130 5.025 297 150 220 V mA ns ns Test Conditions Symbol Min Typ Max Unit CURRENT SENSE Current Sense Voltage Threshold Leading Edge Blanking Duration Overcurrent Detection Propagation Delay Current Sense Bias Current ZERO CURRENT DETECTION ZCD Arming Threshold ZCD Triggering Threshold ZCD Hysteresis ZCD Bias Current Positive Clamp Voltage Negative Clamp Voltage ZCD Propagation Delay VZCD = 5 V IZCD = 3 mA IZCD = −2 mA VZCD = 2 V to 0 V ramp, dV/dt = 20 V/ms VZCD = VZCD(TRIG) to VDRV = 90% VZCD = Increasing VZCD = Decreasing VZCD(ARM) VZCD(TRIG) VZCD(HYS) IZCD VCL(POS) VCL(NEG) tZCD 1.25 0.6 500 −2 9.8 −0.9 − 1.4 0.7 700 − 10 −0.7 100 1.55 0.83 900 +2 12 −0.5 170 V V mV mA V V ns VCS = 2 V, VDRV = 90% to 10% dV/dt = 10 V/ms VCS = VILIM to VDRV = 10% VCS = 2 V VILIM tLEB tCS ICS 0.45 100 40 −1 0.5 190 100 − 0.55 350 170 1 V ns ns mA Minimum ZCD Pulse Width Maximum Off Time in Absence of ZCD Transition DRIVE Drive Resistance Rise Time Fall Time Drive Low Voltage Isource = 100 mA Isink = 100 mA 10% to 90% 90% to 10% VCC = VCC(on)−200 mV, Isink = 10 mA Falling VDRV = 10% to Rising VDRV = 90% tSYNC tstart − 75 70 165 − 300 ns ms ROH ROL trise tfall Vout(start) − − − − − 12 6 35 25 − 20 13 80 70 0.2 W ns ns V http://onsemi.com 5 NCP1608 TYPICAL CHARACTERISTICS VOVP/VREF, OVERVOLTAGE DETECT THRESHOLD 107.0 VOVP(HYS), OVERVOLTAGE HYSTERESIS (mV) −25 0 25 50 75 100 125 150 80 106.5 70 106.0 60 105.5 50 105.0 −50 40 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) VUVP, UNDERVOLTAGE DETECT THRESHOLD (V) TJ, JUNCTION TEMPERATURE (°C) Figure 3. Overvoltage Detect Threshold vs. Junction Temperature RFB, FEEDBACK PIN INTERNAL PULL DOWN RESISTOR (MW) 150 7 6 5 4 3 2 1 Figure 4. Overvoltage Hysteresis vs. Junction Temperature 0.330 0.325 0.320 0.315 0.310 0.305 0.300 −50 −25 0 25 50 75 100 125 0 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. Undervoltage Detect Threshold vs. Junction Temperature 2.54 2.53 2.52 2.51 2.50 2.49 2.48 2.47 2.46 −50 −25 0 25 50 75 100 125 IEA, ERROR AMPLIFIER OUTPUT CURRENT (mA) VREF, REFERENCE VOLTAGE (V) 100 50 0 −50 Figure 6. Feedback Pin Internal Pull Down Resistor vs. Junction Temperature Device in UVP −100 −150 −200 −250 0 0.5 1.0 1.5 2.0 2.5 3.0 150 TJ, JUNCTION TEMPERATURE (°C) VFB, FEEDBACK VOLTAGE (V) Figure 7. Reference Voltage vs. Junction Temperature Figure 8. Error Amplifier Output Current vs. Feedback Voltage http://onsemi.com 6 NCP1608 TYPICAL CHARACTERISTICS 16 IEA(sink), ERROR AMPLIFIER SINK CURRENT (mA) 14 12 10 8 6 −50 IEA(source), ERROR AMPLIFIER SOURCE CURRENT (mA) VFB = 2.6 V 220 215 210 205 200 195 190 185 180 −50 −25 0 25 50 75 VFB = 0.5 V −25 0 25 50 75 100 125 150 100 125 150 TJ, JUNCTION TEMPERATURE (°C) gm, ERROR AMPLIFIER TRANSCONDUCTANCE (mS) TJ, JUNCTION TEMPERATURE (°C) gm, ERROR AMPLIFIER TRANSCONDUCTANCE (mS) Figure 9. Error Amplifier Sink Current vs. Junction Temperature Figure 10. Error Amplifier Source Current vs. Junction Temperature 200 Phase 180 160 140 Transconductance 120 100 RControl = 100 kW CControl = 2 pF VFB = 2.5 Vdc, 1 Vac VCC = 12 V TA = 25°C 0.01 0.1 1 10 100 80 60 40 20 0 1000 q, PHASE (DEGREES) 125 120 115 110 200 180 160 140 120 100 80 60 40 20 0 105 100 95 90 85 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) f, FREQUENCY (kHz) Figure 11. Error Amplifier Transconductance vs. Junction Temperature Ct(offset), MINIMUM CONTROL VOLTAGE TO GENERATE DRIVE PULSES (V) 1.0 Icharge, Ct CHARGE CURRENT (mA) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 −50 −25 0 25 50 75 100 125 150 278 276 274 272 270 268 266 Figure 12. Error Amplifier Transconductance and Phase vs. Frequency 264 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 13. Minimum Control Voltage to Generate Drive Pulses vs. Junction Temperature Figure 14. On Time Capacitor Charge Current vs. Junction Temperature http://onsemi.com 7 NCP1608 TYPICAL CHARACTERISTICS tPWM, PWM PROPAGATION DELAY (ns) 125 6.0 VCt(MAX), Ct PEAK VOLTAGE (V) 170 160 150 140 130 120 110 100 −50 −25 0 25 50 75 100 125 150 5.5 5.0 4.5 4.0 −50 −25 0 25 50 75 100 150 TJ, JUNCTION TEMPERATURE (°C) VILIM, CURRENT SENSE VOLTAGE THRESHOLD (V) TJ, JUNCTION TEMPERATURE (°C) Figure 15. Ct Peak Voltage vs. Junction Temperature 0.520 0.515 0.510 0.505 0.500 0.495 0.490 0.485 0.480 −50 −25 0 25 50 75 100 125 tLEB, LEADING EDGE BLANKING DURATION (ns) 220 Figure 16. PWM Propagation Delay vs. Junction Temperature 210 200 190 150 180 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 17. Current Sense Voltage Threshold vs. Junction Temperature tstart, MAXIMUM OFF TIME IN ABSENCE OF ZCD TRANSITION (ms) 190 185 DRIVE RESISTANCE (W) 180 175 18 16 14 12 10 8 6 4 2 −25 0 25 50 75 100 125 150 Figure 18. Leading Edge Blanking Duration vs. Junction Temperature ROH 170 165 160 155 150 −50 ROL 0 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 19. Maximum Off Time in Absence of ZCD Transition vs. Junction Temperature Figure 20. Drive Resistance vs. Junction Temperature http://onsemi.com 8 NCP1608 TYPICAL CHARACTERISTICS 13 ICC(startup), STARTUP CURRENT CONSUMPTION (mA) 75 100 125 150 12 11 VCC(on) 26 24 22 20 18 16 14 −50 VCC, SUPPLY VOLTAGE THRESHOLDS (V) 10 9 8 −50 VCC(off) −25 0 25 50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 21. Supply Voltage Thresholds vs. Junction Temperature 2.16 ICC2, SWITCHING CURRENT CONSUMPTION (mA) 2.14 2.12 2.10 2.08 2.06 2.04 2.02 2.00 −50 −25 0 25 50 75 Figure 22. Startup Current Consumption vs. Junction Temperature 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 23. Switching Current Consumption vs. Junction Temperature http://onsemi.com 9 NCP1608 Introduction The NCP1608 is a voltage mode, power factor correction (PFC) controller designed to drive cost effective pre-converters to comply with input line harmonic regulations. This controller operates in CrM suitable for applications up to 350 W. Its voltage mode scheme enables it to obtain near unity power factor without the need for a line-sensing network. A high precision transconductance error amplifier regulates the output voltage. The controller implements comprehensive safety features for robust designs. The key features of the NCP1608 are: • Constant On Time (Voltage Mode) CrM Operation. A high power factor is achieved without the need for input voltage sensing. This enables low standby power consumption. • Accurate and Programmable On Time Limitation. The NCP1608 uses an accurate current source and an external capacitor to generate the on time. • Wide Control Range. In high power applications (> 150 W), inadvertent skipping can occur at high input voltage and high output power if noise immunity is not provided. The noise immunity provided by the NCP1608 prevents inadvertent skipping. • High Precision Voltage Reference. The error amplifier reference voltage is guaranteed at 2.5 V ±1.6% over process and temperature. This results in accurate output voltages. • Low Startup Current Consumption. The current consumption is reduced to a minimum (< 35 mA) during startup, enabling fast, low loss charging of VCC. The NCP1608 includes undervoltage lockout and provides sufficient VCC hysteresis during startup to reduce the value of the VCC capacitor. • Powerful Output Driver. A Source 500 mA / Sink 800 mA totem pole gate driver enables rapid turn on and turn off times. This enables improved efficiencies and the ability to drive higher power MOSFETs. A combination of active and passive circuitry ensures that the driver output voltage does not float high if VCC does not exceed VCC(on). • Accurate Fixed Overvoltage Protection (OVP). The OVP feature protects the PFC stage against excessive output overshoots that may damage the application. Overshoots typically occur during startup or transient loads. • Undervoltage Protection (UVP). The UVP feature protects the application if there is a disconnection in the power path to Cbulk (i.e. Cbulk is unable to charge). • Protection Against Open Feedback Loop. The OVP and UVP features protect against the disconnection of the output divider network to the FB pin. An internal resistor (RFB) protects the application when the FB pin is floating (Floating Pin Protection, FPP). • Overcurrent Protection. The peak current is accurately • limited on a cycle-by-cycle basis. The maximum peak current is adjustable by modifying the current sense resistor. An integrated LEB filter reduces the probability of noise inadvertently triggering the overcurrent limit. Shutdown Feature. The PFC pre-converter is shutdown by forcing the FB pin voltage to less than VUVP. In shutdown mode, the ICC current consumption is reduced and the error amplifier is disabled. Application Information Most electronic ballasts and switching power supplies use a diode bridge rectifier and a bulk storage capacitor to produce a dc voltage from the utility ac line (Figure 24). This DC voltage is then processed by additional circuitry to drive the desired output. Rectifiers AC Line + Bulk Storage Capacitor Converter Load Figure 24. Typical Circuit without PFC This rectifying circuit consumes current from the line when the instantaneous ac voltage exceeds the capacitor voltage. This occurs near the line voltage peak and the resulting current is non-sinusoidal with a large harmonic content. This results in a reduced power factor (typically < 0.6). Consequently, the apparent input power is higher than the real power delivered to the load. If multiple devices are connected to the same input line, the effect increases and a “line sag” is produced (Figure 25). Vpeak Rectified DC 0 AC Line Voltage 0 AC Line Current Line Sag Figure 25. Typical Line Waveforms without PFC Government regulations and utilities require reduced line current harmonic content. Power factor correction is implemented with either a passive or an active circuit to comply with regulations. Passive circuits contain a combination of large capacitors, inductors, and rectifiers that operate at the ac line frequency. Active circuits use a http://onsemi.com 10 NCP1608 high frequency switching converter to regulate the input current harmonics. Active circuits operate at a higher frequency, which enables them to be physically smaller, weigh less, and operate more efficiently than a passive circuit. With proper control of an active PFC stage, almost any complex load emulates a linear resistance, which Rectifiers significantly reduces the harmonic current content. Active PFC circuits are the most popular way to meet harmonic content requirements because of the aforementioned benefits. Generally, active PFC circuits consist of inserting a PFC pre−converter between the rectifier bridge and the bulk capacitor (Figure 26). Converter PFC Pre−converter AC Line + High Frequency Bypass Capacitor + NCP1608 Bulk Storage Capacitor Load Figure 26. Active PFC Pre−Converter with the NCP1608 The boost (or step up) converter is the most popular topology for active power factor correction. With the proper control, it produces a constant voltage while consuming a sinusoidal current from the line. For medium power (150 W), VControl is reduced to a low voltage at a large output power and Ct(offset) remains constant. The result is that VCt(off) is reduced to a low voltage at a large output power. The low VControl and VCt(off) voltages are susceptible to noise. The large output power combined with the low VControl and VCt(off) increase the probability of noise interfering with the control signals and on time duration (Figures 36 and 37). The noise induces voltage spikes on the Control pin and Ct pin that reduces the drive on time from the on time determined by the feedback loop (ton(loop)). The reduced on time causes the energy VZCD(ARM) is Not Exceeded 0V ton(loop) DRV Remains Off ton tstart Figure 36. Control Pin Noise Induced On Time Reduction and Pulse Skipping http://onsemi.com 16 NCP1608 VCt(off), Ct CHARGING THRESHOLD (V) VControl Ct(offset) Low VControl Voltage VCt Noise Induced Voltage Spike VCt(off) VControl − Ct(offset) Low VCt(off) Voltage DRV 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 3 V Control Range Vac = 265 Vac NCP1608 25 VZCD VZCD(ARM) VZCD(TRIG) VCL(NEG) 75 125 175 Pout, OUTPUT POWER (W) 225 275 VZCD(ARM) is Not Exceeded Figure 38. Comparison of Ct Charging Threshold vs. Output Power Startup 0V ton(loop) DRV Remains Off ton tstart Figure 37. Ct Pin Noise Induced On Time Reduction and Pulse Skipping Generally, a resistor connected between the rectified ac line and VCC charges the VCC capacitor to VCC(on). The low startup current consumption (< 35 mA) enables minimized standby power dissipation and reduced startup durations. When VCC exceeds VCC(on), the internal references and logic of the NCP1608 are enabled. The controller includes an undervoltage lockout (UVLO) feature that ensures that the NCP1608 is enabled until VCC decreases to less than VCC(off). This hysteresis ensures sufficient time for the auxiliary winding to supply VCC (Figure 39). The wide control range of the NCP1608 increases VControl and VCt(off) in comparison to devices with less control range. Figure 38 compares VCt(off) of the NCP1608 to a device with a 3 V control range for an application with the following parameters: Pout = 250 W L = 200 mH h = 92% VacLL = 85 Vac VacHL = 265 Vac Figure 38 shows that VCt(off) of the NCP1608 is 50% larger than the 3 V control range device. The 50% increase enables the NCP1608 to prevent inadvertent skipping at high input voltages and high output power. VCC VCC(on) VCC(off) Figure 39. Typical VCC Startup Waveform When the PFC pre-converter is loaded by a switch−mode power supply (SMPS), it is generally preferable for the SMPS controller to startup first. The SMPS then supplies the NCP1608 VCC. Advanced controllers, such as the NCP1230 or NCP1381, control the enabling of the PFC stage (see Figure 40) and achieve optimal system performance. This sequence eliminates the startup resistors and improves the standby power dissipation of the system. http://onsemi.com 17 NCP1608 D + 1 2 3 4 NCP1608 8 7 6 5 PFC(Vcc) + 1 2 3 4 NCP1230 8 7 6 5 VCC + + + Cbulk Figure 40. NCP1608 Supplied by a Downstream SMPS Controller (NCP1230) Soft Start VCC When VCC exceeds VCC(on), tstart begins counting. When tstart expires, the error amplifier is enabled and begins charging the compensation network. The drive is enabled when VControl exceeds Ct(offset). The charging of the compensation network slowly increases the drive on time from the minimum time (tPWM) to the steady state on time. This creates a natural soft start mode that reduces the stress of the power components (Figure 41). Output Driver VCC(on) VCC(off) Iswitch FB VREF The NCP1608 includes a powerful output driver capable of sourcing 500 mA and sinking 800 mA. This enables the controller to drive power MOSFETs efficiently for medium power (≤ 350 W) applications. Additionally, the driver stage provides both passive and active pull down clamps (Figure 42). The clamps are active when VCC is off and force the driver output to a voltage less than the turn on threshold voltage of a power MOSFET. Control Ct(offset) Vout Natural Soft Start tstart Figure 41. Startup Timing Diagram Showing the Natural Soft Start of the Control Pin VCC + − + UVLO VDD REG VDD VddGD UVLO DRV IN DRV mVDD GND Figure 42. Output Driver Stage and Pull Down Clamps http://onsemi.com 18 NCP1608 Overvoltage Protection (OVP) The low bandwidth of the feedback network causes active PFC stages to react to changes in output load or input voltages slowly. Consequently, there is a risk of overshoots during transient conditions (i.e. startup, load steps, etc.). For reliable operation, it is critical that overvoltage protection (OVP) prevents the output voltage from exceeding the ratings of the PFC stage components. The NCP1608 detects excessive Vout voltages and disables the driver until Vout decreases. OVP ensures that Vout is within the PFC stage component ratings. A comparator connected to the FB pin provides the OVP protection. The maximum PFC output voltage (the OVP voltage that activates an OVP fault) is calculated using Equation 13: (eq. 13) The Cbulk value is sized to ensure that OVP is not inadvertently triggered by the 100 Hz or 120 Hz ripple of Vout. The minimum value of Cbulk is calculated using Equation 14: Cbulk w P out 2 @ p @ V ripple(peak−peak) @ fline @ Vout (eq. 14) Where Vripple(peak-peak) is the peak−to−peak output voltage ripple and fline is the ac line frequency. Vripple(peak-peak) is calculated using Equation 15: Vripple(peak−peak) v 2 @ Vout(OVP) * Vout (eq. 15) Vout(OVP) V R ) RFB + OVP @ V REF @ R out1 @ out2 )1 VREF R out2 @ RFB The OVP logic includes hysteresis (VOVP(HYS)) to ensure that Vout has sufficient time to discharge before the NCP1608 attempts to restart and to ensure noise immunity. The output voltage at which the NCP1608 attempts a restart (Vout(OVPL)) is calculated using Equation 16: Where VOVP/VREF is the OVP detection threshold. Vout(OVPL) + V OVP @ V REF * V OVP(HYS) VREF @ R out1 @ Rout2 ) RFB )1 Rout2 @ RFB (eq. 16) Figure 43 depicts the operation of the OVP circuitry. Vout Vout(OVP) Vout(OVPL) DRV OVP Fault Figure 43. OVP Operation Undervoltage Protection (UVP) Open Feedback Loop Protection When the input voltage is applied to the PFC stage, Vout is forced to equate to the peak of the line voltage. The NCP1608 detects an undervoltage fault if Vout is unusually low, such that VFB is less than VUVP . During an UVP fault, the drive and error amplifier are disabled. The UVP feature protects the application if there is a disconnection in the power path to Cbulk (i.e. Cbulk is unable to charge) or if Rout1 is disconnected. The output voltage that causes a UVP fault is calculated using Equation 17: Vout(UVP) + V UVP @ R out1 @ R out2 ) R FB )1 R out2 @ R FB (eq. 17) The NCP1608 features comprehensive protection against open feedback loop conditions by including OVP, UVP, and FPP. Figure 44 illustrates three conditions in which the feedback loop is open. The corresponding number below describes each condition shown in Figure 44. 1. UVP Protection: The connection from Rout1 to the FB pin is open. Rout2 pulls down the FB pin to ground. The UVP comparator detects an UVP fault, the drive and error amplifier are disabled. 2. OVP Protection: The connection from Rout2 to the FB pin is open. Rout1 pulls up the FB pin to Vout. The ESD diode clamps the FB voltage to 10 V and Rout1 limits the current into the FB pin. The OVP comparator detects an OVP fault and the drive is disabled. http://onsemi.com 19 NCP1608 3. FPP Protection: The FB pin is floating. The internal pull down resistor RFB pulls down the FB voltage below VUVP. The UVP comparator detects an UVP fault, the drive and error amplifier are disabled. UVP and OVP protect the system from low bulk voltages and rapid operating point changes respectively, while FPP protects the system against floating feedback pin conditions. If FPP is not implemented and a manufacturing error causes the FB pin to float, then VFB is dependent on the coupling within the system and the surrounding environment. The coupled VFB may be within the regulation limits (i.e. VUVP < VFB < VREF) and cause the controller to deliver excessive power. The result is that Vout increases until a component fails due to the voltage stress. + OVP − VOVP UVP − + VUVP (Enable EA) − + + gm Fault POK Vout Cbulk Condition 1 Condition 2 Rout1 FB Condition 3 Rout2 RFB E/A Control CCOMP Figure 44. Open Feedback Loop Protection Overcurrent Protection (OCP) Shutdown Mode The dedicated CS pin of the NCP1608 senses the peak current and limits the driver on time if the voltage of the CS pin exceeds VILIM. The maximum peak current is programmed by adjusting Rsense. The peak current is calculated using Equation 18: IL(peak) + V ILIM R sense (eq. 18) An internal LEB filter (Figure 45) reduces the probability of switching noise inadvertently triggering the overcurrent limit. This filter blanks out the CS signal for a duration of tLEB. If additional filtering is necessary, a small RC filter is connected between Rsense and the CS pin. DRV CS LEB + + − VILIM OCP Rsense optional Figure 45. OCP Circuitry with Optional External RC Filter http://onsemi.com 20 + + VREF VControl VEAH Clamp The NCP1608 enables the user to set the controller in a standby mode of operation. To shutdown the controller, the FB pin is forced to less than VUVP. When using the FB pin for shutdown (Figure 46), the designer must ensure that no significant leakage current exists in the shutdown circuitry. Any leakage current affects the output voltage regulation. Vout Rout1 NCP1608 1 2 3 Shutdown Rout2 4 8 7 6 5 Figure 46. Shutting Down the PFC Stage NCP1608 Application Information ON Semiconductor provides an electronic design tool, a demonstration board, and an application note to facilitate the design of the NCP1608 and reduce development cycle time. All the tools can be downloaded or ordered at www.onsemi.com . Rstart1 The electronic design tool allows the user to easily determine most of the system parameters of a boost pre−converter. The demonstration board is a boost pre−converter that delivers 100 W at 400 V. The circuit schematic is shown in Figure 47. The pre−converter design is described in Application Note AND8396/D. Rstart2 Dboost NTC t° J3 Lboost F1 J2 L1 L2 C1 C2 Bridge Rctup1 R1 C3 Daux D1 CVcc + Dvcc Ro1a Ro1b U1 NCP1608 Cbulk + CVcc2 Ddrv Rdrv Q1 Rout2a Rout2b Czcd Rs3 Rs2 Rs1 Rctup2 Rzcd Cin J1 Rct Rcomp1 Ccomp Ccomp1 Ct2 Ct1 1 8 Vcc FB 2 7 Control DRV 3 6 GND Ct 4 ZCD 5 CS Rcs Ccs Figure 47. Application Schematic http://onsemi.com 21 NCP1608 BOOST DESIGN EQUATIONS Components are identified in Figure 1 rms Input Current Pout Iac + h @ Vac IL(peak),MAX + Vac 2 @ Lv Vout 2 h (the efficiency of only the PFC stage) is generally in the range of 90 − 95%. Vac is the rms ac line input voltage. Where VacLL is the minimum line input voltage. IL(peak),MAX occurs at minimum line input voltage. fSW(MIN) is the minimum desired switching frequency. The maximum L is calculated at both the minimum line input voltage and maximum line input voltage. The maximum on time occurs at the minimum line input voltage and maximum output power. The off time is a maximum at the peak of the ac line voltage and approaches zero at the ac line zero crossings. Theta (q) represents the angle of the ac line voltage. Maximum Inductor Peak Current Inductor Value 2 @ 2 @ P out h @ Vac LL * Vac @ h 2 @ V out @ P out @ fSW(MIN) ton(MAX) + 2 @ L @ P out h @ Vac LL 2 t on *1 Maximum On Time Off Time toff + Vout Vac@ sin q @ 2 Switching Frequency fSW + On Time Capacitor Vac 2 @ h @ 2 @ L @ P out Ct w 1* Vac @ |sin q| @ 2 V out Icharge and VCt(MAX) are shown in the specification table. Where VacHL is the maximum line input voltage. VZCD(ARM) is shown in the specification table. The maximum value of VZCD(ARM) is used for this calculation. Where IZCD(MAX) is maximum rated current for the ZCD pin (10 mA) Where VREF is the internal reference voltage and RFB is the pull down resistor used for FPP. VREF and RFB are shown in the specification table. Ibias(out) is the bias current of the output voltage divider. 2 @ Pout @ L @ Icharge h @ Vac LL @ V Ct(MAX) 2 Inductor Turns to ZCD Turns Ratio NB : N ZCD v Resistor from ZCD winding to the ZCD pin Output Voltage and Output Divider V out * 2 @ Vac HL VZCD(ARM) RZCD w 2 @ Vac HL I ZCD(MAX) @ (N B : N ZCD) R out2 ) R FB )1 R out2 @ R FB Vout + V REF @ R out1 @ Rout1 + Rout2 + R FB @ V out I bias(out) Rout1 @ RFB Vout * 1 * Rout1 VREF VOVP/VREF and VOVP(HYS) are shown in the specification table. Maximum Output Voltage for OVP Detection and Recovery Vout(OVP) + Vout(OVPL) + ) RFB V OVP R @ V REF @ R out1 @ out2 )1 VREF R out2 @ RFB VOVP VREF R out2 ) R FB @ VREF −V OVP(HYS) @ R out1 @ )1 R out2 @ R FB Output Capacitor Cbulk w P out 2 @ p @ V ripple(peak−peak) @ fline @ Vout Where fline is the ac line frequency and Vripple(peak−peak) is the peak−to− peak output ripple voltage. Use fline = 47 Hz for universal input worst case. The ripple voltage must not exceed the OVP voltage for Vout. Where Iload(RMS) is the rms load current. Output Capacitor rms Current IC(RMS) + 2 @ 32 @ P out 2 * Iload(RMS) 2 9 @ p @ Vac LL @ Vout @ h2 http://onsemi.com 22 NCP1608 BOOST DESIGN EQUATIONS Components are identified in Figure 1 (Continued) Minimum Output Voltage for UVP Recovery Inductor rms Current Vout(UVP) + V UVP @ R out1 @ IL(RMS) + ID(RMS),MAX + 4 @ 3 R out2 ) R FB R out2 @ R FB )1 VUVP is shown in the specification table. 2 @ P out 3 @ Vac LL @ h 2@2 p@ P out h @ Vac LL @ Vout 1* V ILIM 2 @ 8 @ Vac LL 3 @ p @ Vout VILIM is shown in the specification table. Output Diode rms Current MOSFET rms Current Pout IM(RMS) + 2 @ @ h @ Vac LL 3 Rsense + PR sense MOSFET Sense Resistor I L(peak) + I M(RMS) 2 @ Rsense Where fCROSS is the crossover frequency and is typically less than 20 Hz. gm is shown in the specification table. Type 1 Compensation gm CCOMP + 2 @ p @ f CROSS http://onsemi.com 23 NCP1608 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AJ A 8 5 −X− B 1 S 4 0.25 (0.010) M Y M −Y− G K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 C −Z− H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The products described herein (NCP1608), may be covered by one or more of the following U.S. patents: 6,362,067, 5,359,281, 5,073,850. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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