NCP1622BECSNT1G

DATA SHEET www.onsemi.com Enhanced, High-Efficiency Power Factor Controller NCP1622 1 The 6−pin PFC controller NCP1622 is designed to drive PFC boost stages. It is based on an innovative Valley Synchronized Frequency Fold−back (VSFF) method. In this mode, the circuit classically operates in Critical conduction Mode (CrM) when Vcontrol voltage exceeds a programmable value Vctrl,FF. When Vcontrol is below this preset level Vctrl,FF, the NCP1622 (versions [B**] and [D**]) linearly decays the frequency down to about 30 kHz until Vcontrol reaches the SKIP mode threshold. VSFF maximizes the efficiency at both nominal and light load. In particular, the stand−by losses are reduced to a minimum. Like in FCCrM controllers, internal circuitry allows near−unity power factor even when the switching frequency is reduced. Housed in a TSOP6 package, the circuit also incorporates the features necessary for robust and compact PFC stages, with few external components. General Features • Near−Unity Power Factor • Critical Conduction Mode (CrM) • Valley Synchronized Frequency Fold−back (VSFF): Low Frequency • • • • • • • • • • TSOP−6 SN SUFFIX CASE 318G Operation is Forced at Low Current Levels (9 Pre−programmed Settings) Works With or Without a Transformer w/ ZCD Winding (Simple Inductor) On−time Modulation to Maintain a Proper Current Shaping in VSFF Mode Skip Mode at Very Low Load Current (versions [B**] and [D**]) Fast Line / Load Transient Compensation (Dynamic Response Enhancer) Valley Turn−on High Drive Capability: −500 mA / +800 mA VCC Range: from 9.5 V to 30 V Low Start−up Consumption for: [**C] Version: Low Vcc Start−up level (10.5 V) [**A] Version: High Vcc Start−up level (17.0 V) Line Range Detection for Reduced Crossover Frequency Spread This is a Pb−Free Device MARKING DIAGRAM XXXAYWG G 1 XXX A Y W G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS VCTRL 1 6 FB GND 2 5 VCC CS / ZCD 3 4 DRV (Top View) ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 2 of this data sheet. Safety Features • • • • • • • • • Typical Applications Thermal Shutdown Non−latching, Over−Voltage Protection Second Over−Voltage Protection Brown−Out Detection Soft−Start for Smooth Start−up Operation ([**C] Version) Over Current Limitation Disable Protection if the Feedback Pin is Not Connected Low Duty−Cycle Operation if the Bypass Diode is Shorted Open Ground Pin Fault Monitoring © Semiconductor Components Industries, LLC, 2017 August, 2021 − Rev. 5 • • • • 1 PC Power Supplies Lighting Ballasts (LED, Fluorescent) Flat TV All Off Line Appliances Requiring Power Factor Correction Publication Order Number: NCP1622/D NCP1622 DEVICE ORDERING INFORMATION The coding letters for the product options does not correspond to the marking on the TSOP6 package. This table shows the correspondence between product option coding and TSOP6 marking. Operating Part Number (OPN) L1, L2, L3 Option Marking NCP1622AEASNT1G AEA A5A NCP1622BCASNT1G BCA 3CA NCP1622BCCSNT1G BCC 3CC NCP1622BECSNT1G BEC 3EC NCP1622DCCSNT1G DCC DC6 NOTE: Package Type Shipping TSOP−6 (Pb−Free) 3000 / Tape & Reel Other L1, L2, L3 options are available upon request. Several product configurations coded with three letters (L1, L2, L3) will be available. Table 1. NCP1622 1st LETTER CODING OF PRODUCT VERSIONS L1 Brown−out Function Skip Mode Function A (default) NO (default) NO (default) B NO (default) YES (trim) C YES (trim) NO (default) D YES (trim) YES (trim) Table 2. NCP1622 2nd LETTER CODING OF PRODUCT VERSIONS L2 CrM to DCM VCTRL Threshold (V) tON,max,LL (ms) tON,max,HL(ms) A 0.816 25 8.33 B 1.026 25 8.33 C 1.296 25 8.33 D 1.132 12.5 4.17 E (default) 1.553 12.5 4.17 F 2.079 12.5 4.17 G 1.459 8.3 2.77 H 2.079 8.3 2.77 I 2.840 8.3 2.77 J 0.816 30 10 K 1.026 30 10 L 1.296 30 10 Table 3. NCP1622 3rd LETTER CODING OF PRODUCT VERSIONS L3 VCC Startup Level (V) A (default) 17.0(default) C 10.5 The non−trimmed (default) version of the product, will be then coded AEA (L1=A, L2=E, L3=A) L1 = A meaning NO Brow−out and NO SKIP Mode L2 = E meaning E version of Frequency Foldback L3 = A meaning 17V VCC Startup voltage www.onsemi.com 2 NCP1622 Vin IL Caux D1 L1 Vaux Rfb1 Raux Qaux V bulk Rcs1 DRV AC line VCTRL Cin EMI Filter GND Rcs0 Rz Cp CS / ZCD 1 6 2 5 3 4 Cbulk FB LOAD VCC DRV Q1 Rcs2 Cz Rfb2 Rsense Figure 1. NCP1622 Application Schematic using Auxiliary Winding Voltage Table 4. DETAILED PIN DESCRIPTION Pin Number Name Function 1 VCTRL The error amplifier output is available on this pin. The network connected between this pin and ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high Power Factor ratios. VCTRL pin is internally pulled down when the circuit is off so that when it starts operation, the power increases slowly to provide a soft−start function. VCTRL pin must not be controlled or pulled down externally. 2 GND 3 CS / ZCD Connect this pin to the PFC stage ground. 4 DRV The high−current capability of the totem pole gate drive (−0.5 / +0.8 A) makes it suitable to effectively drive high gate charge power MOSFETs. 5 VCC This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 17.0 V ([**A] Versions) or 10.5 V ([**C] Versions) and turns off when VCC goes below 9.0 V (typical values). After start−up, the operating range is 9.5 V up to 30 V. 6 FB This pin monitors the MOSFET current to limit its maximum current. This pin is the output of a resistor bridge connected between the drain and the source of the power MOSFET. Internal circuitry takes care of extracting Vin , Vout , Iind and ZCD This pin receives a portion of the PFC output voltage for the regulation and the Dynamic Response Enhancer (DRE) that drastically speeds−up the loop response when the output voltage drops below 95.5% of the desired output level. FB pin voltage VFB is also the input signal for the (non−latching) Over−Voltage (OVP) and Under−Voltage (UVP) comparators. The UVP comparator prevents operation as long as FB pin voltage is lower than VUVPH internal voltage reference. A SOFTOVP comparator gradually reduces the duty−ratio when FB pin voltage exceeds 105% of VREF. If the output voltage still increases, the driver is immediately disabled if the output voltage exceeds 107% of the desired level (fast OVP). A 250 nA sink current is built−in to trigger the UVP protection and disable the part if the feedback pin is accidently open. www.onsemi.com 3 NCP1622 Table 5. MAXIMUM RATINGS TABLE Symbol Pin Rating VCTRL 1 VCONTROL pin CS/ZCD 3 CS/ZCD Pin DRV 4 Driver Voltage Driver Current VCC 5 Power Supply Input VCC 5 Maximum (dV/dt) that can be applied to VCC FB 6 Feedback Pin Value Units −0.3, Vctrl,max(*) V −0.3, +9 V −0.3, VDRV (*) −500, +800 V mA −0.3, + 30 V TBD upon test engineer measurements V/s −0.3, +9 V 550 145 mW °C/W −40 to+125 °C 150 °C −65 to 150 °C 300 °C Power Dissipation and Thermal Characteristics Maximum Power Dissipation @ TA = 70°C Thermal Resistance Junction to Air PD RqJA TJ Operating Junction Temperature Range TJ,max Maximum Junction Temperature TS,max Storage Temperature Range TL,max Lead Temperature (Soldering, 10 s) MSL Moisture Sensitivity Level 1 − ESD Capability Human Body Model per JEDEC Standard JESD22−A114F Charge Device Model per JEDEC Standard JESD22−C101F Machine Model per JEDEC Standard JESD22−A115C 3000 1000 200 Latch−Up Protection per JEDEC Standard JESD78 ±100 V mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. *“Vctrl,max” is the VCTRL pin clamp voltage. “VDRV” is the DRV clamp voltage (VDRVhigh) if VCC is higher than (VDRVhigh). “VDRV” is VCC otherwise. Table 6. TYPICAL ELECTRICAL CHARACTERISTICS (Conditions: VCC = 18 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 1) Rating Min Typ Max Start−Up Threshold, VCC increasing: [**C] Versions [**A] Versions 9.75 15.80 10.50 17.00 11.25 18.20 Minimum Operating Voltage, VCC falling 8.50 9.00 9.50 Hysteresis (VCC ,on − VCC ,off) [**C] Versions [**A] Versions 0.75 6.00 1.50 8.00 − − Symbol Unit Start−up and Supply Circuit VCC,on VCC,off VCC,hyst V V V ICC,start Start−Up Current, VCC = 9.4 V, below startup voltage − − 70 mA ICC,op1 Operating Consumption, no switching. − 0.5 1.00 mA ICC,op2 Operating Consumption, 50−kHz switching, no load on DRV pin − 2.00 3.00 mA Frequency Fold−back Dead Time for configurations L2= A,B,C,D,E,F,G,H,I,J,K,L tDT,A,1 Dead−Time, Vctrl = 0.65V w/ A config 2.00 2.67 3.5 ms tDT,A,2 Dead−Time, Vctrl = 0.75V w/ A config 0.51 0.68 0.85 ms tDT,B,1 Dead−Time, Vctrl = 0.65V w/ B config 5.73 7.64 9.55 ms tDT,B,2 Dead−Time, Vctrl = 0.75V w/ B config 2.91 3.88 4.85 ms tDT,C,1 Dead−Time, Vctrl = 0.65V w/ C config 8.90 11.87 14.84 ms tDT,C,2 Dead−Time, Vctrl = 0.75V w/ C config 5.69 7.58 9.48 ms 1. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit characterization has been performed. www.onsemi.com 4 NCP1622 Table 6. TYPICAL ELECTRICAL CHARACTERISTICS (Conditions: VCC = 18 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 1) Symbol Min Typ Max Unit tDT,D,1 Dead−Time, Vctrl = 0.65V w/ D config Rating 4.98 6.64 8.30 ms tDT,D,2 Dead−Time, Vctrl = 0.75V w/ D config 2.66 3.55 4.44 ms tDT,E,1 Dead−Time, Vctrl = 0.65V w/ E config 9.96 13.28 16.60 ms tDT,E,2 Dead−Time, Vctrl = 0.75V w/ E config 6.70 8.93 10.80 ms tDT,F,1 Dead−Time, Vctrl = 0.65V w/ F config 13.00 17.33 21.66 ms tDT,F,2 Dead−Time, Vctrl = 0.75V w/ F config 9.97 13.29 16.61 ms tDT,G,1 Dead−Time, Vctrl = 0.65V w/ G config 7.98 10.64 13.30 ms tDT,G,2 Dead−Time, Vctrl = 0.75V w/ G config 4.79 6.38 7.98 ms tDT,H,1 Dead−Time, Vctrl = 0.65V w/ H config 14.51 19.35 24.19 ms tDT,H,2 Dead−Time, Vctrl = 0.75V w/ H config 10.41 13.88 17.35 ms tDT,I,1 Dead−Time, Vctrl = 0.65V w/ I config 18.11 24.15 30.19 ms tDT,I,2 Dead−Time, Vctrl = 0.75V w/ I config 14.48 19.31 24.14 ms tDT,J,1 Dead−Time, Vctrl = 0.65V w/ J config 2.00 2.67 3.5 ms tDT,J,2 Dead−Time, Vctrl = 0.75V w/ J config 0.51 0.68 0.85 ms tDT,K,1 Dead−Time, Vctrl = 0.65V w/ K config 5.73 7.64 9.55 ms tDT,K,2 Dead−Time, Vctrl = 0.75V w/ K config 2.91 3.88 4.85 ms tDT,L,1 Dead−Time, Vctrl = 0.65V w/ L config 8.90 11.87 14.84 ms tDT,L,2 Dead−Time, Vctrl = 0.75V w/ L config 5.69 7.58 9.48 ms CrM to DCM threshold and Hysteresis Vctrl,th,A Vctrl threshold CrM to DCM mode w/ A config −10% 0.816 +10% V Vctrl,th,B Vctrl threshold CrM to DCM mode w/ B config 0.923 1.026 1.129 V Vctrl,th,C Vctrl threshold CrM to DCM mode w/ C config 1.16 1.29 1.43 V Vctrl,th,D Vctrl threshold CrM to DCM mode w/ D config −10% 1.132 +10% V Vctrl,th,E Vctrl threshold CrM to DCM mode w/ E config 1.398 1.553 1.708 V Vctrl,th,F Vctrl threshold CrM to DCM mode w/ F config −10% 2.079 +10% V Vctrl,th,G Vctrl threshold CrM to DCM mode w/ G config −10% 1.459 +10% V Vctrl,th,H Vctrl threshold CrM to DCM mode w/ H config −10% 2.079 +10% V Vctrl,th,I Vctrl threshold CrM to DCM mode w/ I config −10% 2.840 +10% V Vctrl,th,J Vctrl threshold CrM to DCM mode w/ J config −10% 0.816 +10% V Vctrl,th,K Vctrl threshold CrM to DCM mode w/ K config −10% 1.026 +10% V Vctrl,th,L Vctrl threshold CrM to DCM mode w/ L config −10% 1.296 +10% V − 100 − mV Vctrl,th,hyst SKIP Control Vctrl threshold DCM to CrM minus Vctrl threshold CrM to DCM , all config ([B**] & [D**] Versions) VSKIP−H Vctrl pin SKIP Level, Vcontrol rising 555 617 678 mV VSKIP−L Vctrl pin SKIP Level, Vcontrol falling 516 593 665 mV Vctrl pin SKIP Hysteresis − 30 − mV tR Output voltage rise−time @ CL = 1nF, 10−90% of output signal − 30 − ns tF Output voltage fall−time @ CL = 1nF, 10−90% of output signal − 20 − ns ROH Source resistance @ 200mV under High VCC − 10 − W ROL Sink resistance @200mV above Low VCC − 7 − W 8.0 − − V VSKIP−Hyst Gate Drive VDRV,low DRV pin level for VCC = VCC ,off +200mV (10−kΩ resistor between DRV and GND) 1. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit characterization has been performed. www.onsemi.com 5 NCP1622 Table 6. TYPICAL ELECTRICAL CHARACTERISTICS (Conditions: VCC = 18 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 1) Symbol VDRV,high Rating DRV pin level at VCC = 30 V (RL = 33 kΩ & CL = 1 nF) Min Typ Max Unit 10 12 14 V 2.44 2.50 2.56 V Regulation Block VREF Feedback Voltage Reference IEA Error Amplifier Current Capability,sinking and sourcing 15 20 26 mA GEA Error Amplifier Gain 110 200 290 mS Vctrl VCTRL pin Voltage (Vctrl ): − @ VFB = 2 V (OTA is sourcing 20 mA) − @ VFB = 3 V (OTA is sinking 20 mA) − − 4.5 0.5 − − Vctrl,min Vctrl,max V Vout,L / VREF Ratio (Vout Low Detect Threshold / VREF ) (guaranteed by design) − 95.5 − % Hout,L / VREF Ratio (Vout Low Detect Hysteresis / VREF ) (guaranteed by design) − 0.35 − % IBOOST VCTRL pin Source Current when (VOUT Low Detect) is activated 147 220 277 mA Current Sense Voltage Reference 450 500 550 mV Current Sense Overstress Voltage Reference Current Sense and Zero Current Detection Blocks VCS(th) VCS,OVS(th) 675 750 825 mV tLEB,OVS “Overstress” Leading edge Blanking Time (guaranteed by design) − 250 − ns tLEB,OCP “Over−Current Protection” Leading edge Blanking Time ( guaranteed by design) − 400 − ns Over−Current Protection Delay from VCS/ZCD >VCS(th) to DRV low (dVCS/ZCD / dt = 10 V/ms) − 40 200 ns tOCP VZCD(th)H Zero Current Detection, VCS/ZCD rising 8.0 40 62 mV VZCD(th)L Zero Current Detection, VCS/ZCD falling −68 −50 −25 mV VZCD(hyst) Hysteresis of the Zero Current Detection Comparator 46 84 − mV VCL(pos) CS/ZCD Positive Clamp @ ICS/ZCD = 5 mA (guaranteed by design) − 9.5 − V tZCD (VCS/ZCD < VZCD (th )L ) to (DRV high) − 60 200 ns tSYNC Minimum ZCD Pulse Width − 110 200 ns tWDG Watch Dog Timer 80 200 320 ms tWDG(OS) Watch Dog Timer in “OverStress” Situation 400 800 1200 ms IZCD(gnd) Source Current for CS/ZCD pin impedance Testing − 50 − mA IZCD(Vcc) Pull−up current source referenced to Vcc for open pin detection − 200 − nA Duty Cycle, VFB = 3 V ( When low clamp of Vctrl is reached) − − 0 % Static OVP DMIN On−Time Control (3 options for maximum tON value) ton,LL,ABC Maximum On Time, avg(Vcs ) = 0.9 V and Vctrl maximum (CrM) 22 25 28 ms ton,LL,JKL Maximum On Time, avg(Vcs ) = 0.9 V and Vctrl maximum (CrM) 25 30 35 ms ton,LL,DEF Maximum On Time, avg(Vcs ) = 0.9 V and Vctrl maximum (CrM) 11.4 12.5 13.6 ms ton,LL,GHI Maximum On Time, avg(Vcs ) = 0.9 V and Vctrl maximum (CrM) 7.3 8.3 9.3 ms ton,HL,ABC Maximum On Time, avg(Vcs ) = 2.8 V and Vctrl maximum (CrM) 7.49 8.33 9.16 ms ton,HL,JKL Maximum On Time, avg(Vcs ) = 2.8 V and Vctrl maximum (CrM) 8.0 10 12 ms ton,HL,DEF Maximum On Time, avg(Vcs ) = 2.8 V and Vctrl maximum (CrM) 3.75 4.17 4.59 ms ton,HL,GHI Maximum On Time, avg(Vcs ) = 2.8 V and Vctrl maximum (CrM) 2.49 2.77 3.05 ms Kton,LL−HL tON @LL over tON @HL ratio (all tON versions) − 3 − w/o ton,LL,min Minimum On Time, avg(Vcs ) = 0.9 V (not tested, guaranteed by design) − 300 − ns ton,HL,min Minimum On Time, avg(Vcs ) = 2.8 V (not tested, guaranteed by design) − 200 − ns 1. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit characterization has been performed. www.onsemi.com 6 NCP1622 Table 6. TYPICAL ELECTRICAL CHARACTERISTICS (Conditions: VCC = 18 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 1) Symbol Rating Min Typ Max Unit Ratio (Soft OVP Threshold, VFB rising) over VREF (or VREF2) (guaranteed by design) − 105 − % Ratio (Soft OVP Hysteresis) over VREF (or VREF2) (guaranteed by design) − 1.87 − % Ratio (Fast OVP Threshold, VFB rising) over VREF (or VREF2) (guaranteed by design) − 107 − % Ratio (Fast OVP Hysteresis) over VREF (or VREF2) (guaranteed by design) − 4.0 − % Feed−back Over and Under−Voltage Protections (OVP and UVP) RsoftOVP RsoftOVP(HYST) RfastOVP RfastOVP(HYST) VUVPH UVP Threshold, VFB increasing 477 530 583 mV VUVPL UVP Threshold, VFB decreasing 252 303 357 mV UVP Hysteresis 200 225 250 mV FB pin Bias Current @ VFB = VOV P and VFB = VUVP 50 200 450 nA VUVP(HYST) IB,FB Brown−Out Protection and Feed−Forward ( Vsns is an internal pin that replaces Vsense) VBOH Brown−Out Threshold Vmains increasing, VFB based ([C**] and [D**] versions) 754 819 894 mV VBOL Brown−Out Threshold, Vmains decreasing, avg(VCS) based ([C**] and [D**] versions) 659 737 801 mV Brown−Out Comparator Hysteresis ([C**] and [D**] versions) 75 100 − mV Brown−Out Blanking Time ([C**] and [D**] versions) 36 50 67 ms VBO(HYST) tBO(blank) IVCTRL(BO) 20 30 42 mA VHL VCTRL pin sink current during BO condition Comparator Threshold for Line Range Detection, avg(VCS ) rising 1.605 1.690 1.774 V VLL Comparator Threshold for Line Range Detection, avg(VCS ) falling 1.406 1.480 1.554 V VHL(hyst) Comparator Hysteresis for Line Range Detection 75 100 − mV tHL(blank) Blanking Time for Line Range Detection 13 25 43 ms Thermal Shutdown TLIMIT Thermal Shutdown Threshold 150 − − °C HTEMP Thermal Shutdown Hysteresis − 50 − °C Second Overvoltage Protection (OVP2) VOVP2H,HL OVP2 Threshold, VCS rising, KCS = 138 , @VREF2 = 2.5 V 3.048 3.175 3.302 V VOVP2L,HL OVP2 Threshold, VCS falling, KCS = 138, @VREF2 = 2.5 V 2.969 3.093 3.217 V VOVP2(HYST),HL OVP2 Comparator Hysteresis, KCS = 138, @VREF2 = 2.5 V 50 100 − mV tLEB,OVP2 OVP2 Leading Edge Blanking Time, VCS rising (guaranteed by design) − 1000 − ns tRST(OVP2) Reset Timer for OVP2 latch 400 800 1200 ms 1. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit characterization has been performed. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 7 NCP1622 Transconductance Error Amplifier OVLFLAG1 FB VREF OVP2 OFF VREGUL VCTRL MANAGMENT BONOK PFCOK STATICOVP FB MANAGMENT DRE VREF,DRE VREF,UVP UVP VREF,OVS SOFTOVP VREF,SOFT_OVP FASTOVP VREF,FAST_OVP OVERSTRESS DRV VCC CURRENT SENSE VREF VREF,XXXX OCP THERMAL SHUTDOWN VREF,OCP VDD CSint TSD UVP BONOK CSZCD BUFFER DRV DEMAG & LINE SENSE FAULT MANAGMENT ZCD OFF STATICOVP VSNS VREF,VCC UVLO OFF VREF,LLINE OVP2 SECOND OVP STATICOVP OCP OVERSTRESS PFCOK S OFF OVP2 LINE & BO MANAGMENT OVLFLAG1 STOP FASTOVP ZCD DT Q R VREF,BONOK BONOK LLINE VREGUL DRV ZCD LLINE OVERSTRESS PFCOK UVLO DRV CLK & DT MANAGMENT VCC CLK Internal Timing Ramp S Q R CLK DT SKIP VREGUL DT SOFTOVP SKIP Vton Processing Circuitry Figure 2. NCP1622 Block Diagram www.onsemi.com 8 All RS latches are reset dominat SKIPDEL Output Buffer NCP1622 DETAILED OPERATING DESCRIPTION Introduction NCP1622 is designed to optimize the efficiency of your PFC stage throughout the load range. In addition, it incorporates protection features for rugged operation. More generally, NCP1622 is ideal in systems where cost−effectiveness, reliability, low stand−by power and high efficiency are key requirements: • Valley Synchronized Frequency Fold−back: NCP1622 is designed to drive PFC boost stages in so−called Valley Synchronized Frequency Fold−back (VSFF). In this mode, the circuit classically operates in Critical conduction Mode (CrM) when Vctrl exceeds a programmable value. When the Vctrl is below this preset level, NCP1622 linearly reduces the frequency down to about 33 kHz before reaching the SKIP threshold voltage (SKIP Mode versions [B**] and [D**]). VSFF maximizes the efficiency at both nominal and light load. In particular, stand−by losses are reduced to a minimum. Similarly to FCCrM controllers, an internal circuitry allows near−unity power factor even when the switching frequency is reduced. • SKIP Mode (Versions [B**] and [D**]): to further optimize the efficiency, the circuit skips cycles at low load current when Vctrl reaches the SKIP threshold voltage. This is to avoid circuit operation when the power transfer is particularly inefficient at the cost of current distortion. This SKIP function is not present on versions [A**] and [C**]). • Low Start−up Current and large VCC range ([**A] & [**C] versions): The start−up consumption of the circuit is minimized to allow the use of high−impedance start−up resistors to pre−charge the VCC capacitor. Also, the minimum value of the UVLO hysteresis is 6 V to avoid the need for large VCC capacitors and help shorten the start−up time without the need for too dissipative start−up elements. The [**C] version is preferred in applications where the circuit is fed by an external power source (from an auxiliary power supply or from a downstream converter). Its maximum start−up level (11.25 V) is set low enough so that the circuit can be powered from a 12−V rail. After start−up, the high VCC maximum rating allows a large operating range from 9.5 V up to 30 V. • Fast Line / Load Transient Compensation (Dynamic Response Enhancer): Since PFC stages exhibit low loop bandwidth, abrupt changes in the load or input voltage (e.g. at start−up) may cause excessive over or under−shoot. This circuit limits possible deviations from the regulation level as follows: ♦ NCP1622 linearly decays the power delivery to zero when the output voltage exceeds 105% of its desired • • level (soft OVP). If this soft OVP is too smooth and the output continues to rise, the circuit immediately interrupts the power delivery when the output voltage is 107% above its desired level. ♦ NCP1622, dramatically speeds−up the regulation loop when the output voltage goes below 95.5% of its regulation level. This function is enabled only after the PFC stage has started−up to allow normal soft−start operation to occur. Safety Protections: Permanently monitoring the input and output voltages, the MOSFET current and the die temperature to protect the system from possible over−stress making the PFC stage extremely robust and reliable. In addition to the OVP protection, the following methods of protection are provided: ♦ Maximum Current Limit: The circuit senses the MOSFET current and turns off the power switch if the set current limit is exceeded. In addition, the circuit enters a low duty−cycle operation mode when the current reaches 150% of the current limit as a result of the inductor saturation or a short of the bypass diode. ♦ Under−Voltage Protection: This circuit turns off when it detects that the output voltage is below 12% of the voltage reference (typically). This feature protects the PFC stage if the ac line is too low or if there is a failure in the feedback network (e.g., bad connection). ♦ Brown−Out Detection: The circuit detects low ac line conditions and stops operation thus protecting the PFC stage from excessive stress. ♦ Thermal Shutdown: An internal thermal circuitry disables the gate drive when the junction temperature exceeds 150°C (typically). The circuit resumes operation once the temperature drops below approximately 100°C (50°C hysteresis). Output Stage Totem Pole: NCP1622 incorporates a −0.5 A / +0.8 A gate driver to efficiently drive most TO220 or TO247 power MOSFETs. NCP1622 Operation Modes As mentioned, NCP1622 PFC controller implements a Valley Synchronized Frequency Fold−back (VSFF) where: ♦ The circuit operates in classical Critical conduction Mode (CrM) when Vctrl exceeds a programmable value Vctrl,th,* . ♦ When Vctrl is below this Vctrl,th,* , the NCP1622 linearly reduces the operating frequency down to about 33 kHz ♦ When Vctrl reaches Vcrtl minimum value or the Vctrl SKIP mode threshold, the system works in low frequency burst mode. www.onsemi.com 9 NCP1622 High Current No delay è CrM Low Current The next cycle is delayed Timer delay Lower Current Longer dead−time Timer delay Figure 3. Valley Switching Operation in CrM and DCM Modes As illustrated in Figure 3, under high load conditions, the boost stage is operating in CrM but as the load is reduced, the controller enters controlled frequency discontinuous operation. To further reduce the losses, the MOSFET turns on is stretched until its drain−source voltage is at its valley. The end of the dead time is synchronized with the drain−source ringing. VALLEY SYNCHRONIZED FREQUENCY FOLDBACK (VSFF) a/ Valley Synchronized (VS) DRV Dead−Time (DT) Zero Current Detection DRV 200−us WATCHDOG Ramp for DT Control DT Vctrl VCTRL DEAD TIME GENERATOR END OF DEMAG SENSING DRV DEMAG SENSING DRV Clock Generation ZCD CS/ZCD ZCD TIMER Vcs int DRV CSZCD BUFFER CLK END OF DEAD TIME SYNCHRONIZATION DRV Figure 4. Valley Synchronized Turn−on Block Diagram or vice versa from the n valley to (n−1) cleanly as illustrated by the simulation results of Figure 5. When the Line voltage and inductor current are very low, or when the amplitude of the drain voltage gets too low (in the case of long dead times), the turn−on of the power MOSFET is no longer synchronized with the drain valley but will start exactly at the end of a programmed dead time looks to the ZCD TIMER block. Valley Synchronized is the first half of the VSFF system. Synchronizing the Turn−on with the drain voltage valley maximizes the efficiency at both nominal and light load conditions. In particular, the stand−by losses are reduced to a minimum. The synchronization of Power MOSFET Turn−on (rising edge of CLK signal) with drain voltage valley is depicted on Figure 4. This method avoids system stalls between valleys. Instead, the circuit acts so that the PFC controller transitions from the n valley to (n+1) valley www.onsemi.com 10 NCP1622 If no demagnetization is sensed the power MOSFET will be turned−on after a watchdog timing of 200−ms. 350 300 250 200 3rd Valley Drain Source Voltage (50 V/div) 4th Valley 150 100 50 −0 2. 54 VREF,DT 2. 52 2. 5 Ramp + Vffctl (20mV/div) 2. 48 2. 46 2. 44 2. 42 10 8 6 DRV (2 V/div) 4 2 2 1. 8 1. 6 1. 4 1. 2 1 0. 8 0. 6 0. 4 0. 2 0 −0. 2 Inductor Current (100 mA/div) 385. 69 385. 695 385. 7 385. 705 385. 71 Time (5 uSecs /div) / Figure 5. Clean Transition Without Hesitation Between Valleys b/ Frequency Foldback (FF) drain voltage, hence the name Valley Synchronized (VS). The lower the Vctrl value, the longer the dead−time. The Frequency Foldback (FF) system adjusts the on−time versus tDT (see Figure 6) and the output power in order to ensure that the instantaneous mains current is in phase with the mains instantaneous voltage (creating a PF=1). Frequency Foldback is the second half of the VSFF system. When Vctrl falls below an option−programmable Vctrl,th,* threshold, the NCP1622 enters DCM and linearly reduces the operating frequency down to about 33 kHz by adding a dead−time after the end of inductor demagnetization. The end of the dead−time is synchronized with the valley in the tON Iind t DEMAG Ipeak ,max 0 Tsw CLK DT t DT DRV time Figure 6. NCP1622 Clock, Dead Time and tON Waveforms www.onsemi.com 11 NCP1622 When the load is at its maximum (the maximum Vctrl value and inductor peak current limitation is not triggering), the controller runs in CrM mode and the frequency (@Vin =Vin,max ) has its minimum value. As we start decreasing the output power, the Vctrl voltage decreases, the switching frequency (@Vin =Vin,max ) increases and the controller stays in CrM mode until Vctrl reaches a threshold voltage named Vctrl,th,* . From this point, continuing to reduce the output power makes the controller to continue increase the dead time (TDT ) after the end of demagnetization resulting in a DCM conduction mode and a switching frequency decrease (Frequency Foldback). When the output power is reduced and we enter DCM mode, the switching frequency decreases down to a value given by the following equation, which is valid down to before entering SKIP mode. This minimum DCM frequency value is dominated by the dead time value, tON plus tDEMAG being negligible versus tDT that has reached is maximum value tDT,max . FSW (Hz) A D FSW, DCM, min + 1 1 [ (eq. 1) t DT,max ) t ON ) t DEMAG t DT,max In order to have, depending on customer application, a different limitation of the maximum switching frequency (@Vin=Vin,max), as well as different Vctrl thresholds for CrM to DCM boundary, different product versions are made available (see Table 2). Coding the second letter (L2) of the version code with letters A,B,C,D,E,F,G,H,I can be configured at the factory. The Figure 7 and Figure 8 represent curves generated by an analytical model processed by a MathCad spreadsheet. The differences between the different possible configurations (E for the second letter of product version code is the default configuration) are evident. Notice that Figure 9 shows output power versus Vctrl that depends only on tON,max and on inductor value (the higher the inductor value, the higher the Pout value). G B C E H F I Vctrl (V) Figure 7. Switching Frequency (@ Vin = Vin,max) versus Vctrl (No L Dependent) : Default = [*E*] www.onsemi.com 12 NCP1622 Iind,peak (A) C B A F E D I H G Vctrl (V) Figure 8. Maximum Inductor Peak Current (@ Vin = Vin,max) versus Vctrl (L Dependent) : Default = [*E*] Pout (W) TON,max=25us/3 A,B,C @ High LINE @ L=200uH D,E,F TON,max=12.5us/3 TON,max=8.33us/3 G,H,I Vctrl (V) Figure 9. Output Power Pout versus Vctrl and TON,max (L Dependent) : Default = [*E*] www.onsemi.com 13 NCP1622 CrM−DCM and DCM−CrM Transition Hysteresis NCP1622 On−time Modulation and VTON Processing Circuit Hesitation of the system to transition between the modes CrM and DCM may have a consequences on inductor current shape and distort the mains current, resulting in a bad PF value when the operating point is at the CrM−DCM boundary. To avoid such undesired behavior, a 40 mV hysteresis is added on Vctrl threshold. The Vctrl threshold for transitioning from CrM to DCM mode is named Vctrl,th, * (see Table 6) and the Vctrl threshold for transitioning from DCM to CrM mode is Vctrl,th ,* + 40 mV. Let’s analyze the ac line current absorbed by the PFC boost stage. The initial inductor current at the beginning of each switching cycle is always zero. The coil current ramps up when the MOSFET is on. The slope is (Vin/L) where L is the coil inductance. At the end of the on−time (t1 ), the inductor starts to demagnetize. The inductor current ramps down until it reaches zero. The duration of this phase is (t2 ). In some cases, the system enters then the dead−time (t3 ) that lasts until the next clock is generated. One can show that the ac line current is given by: NCP1622 Skip Mode (Active on Versions [B**] and [D**], Disabled on Versions [A**] and [C**]) I in + V in The circuit also skips cycles when Vctrl decreases towards VSKIP−L threshold. A comparator monitors the Vctrl voltage and inhibits the drive when Vctrl is lower than the SKIP Mode threshold VSKIP−L. Switching resumes when Vctrl exceeds VSKIP−H threshold. The skip mode capability is disabled whenever the PFC stage is not in nominal operation (as dictated by the PFCOK signal − see PFCOK Operation section). T + t1 ) t2 ) t3 Iind L1 DRV t1 (eq. 3) D1 Vout Cbulk Q1 Rsense time Iind (eq. 2) is the switching period and Vin is the ac line rectified voltage. In light of this equation, we immediately note that Iin is proportional to Vin if [t1.(t1+t2)/T] is a constant. Cin Ipeak,max 2T L Where Vin Vin t 1ǒt 1 ) t 2Ǔ t2 t3 time 0 T Figure 10. PFC Boost Converter and Inductor Current in DCM The NCP1622 operates in voltage mode. As portrayed by Figure 10 & Figure 11, the MOSFET on−time t1 is set by a dedicated circuitry monitoring Vctrl and dead−time tDT ensuring [t1.(t1+t2)/T] is constant and as a result making Iin proportional to Vin (PF=1) On−time t1 is also called ton and its maximum value ton,max is obtained when Vctrl is at maximum level. The internal circuitry makes ton,max at High Line condition (HLINE) to be 3 times the ton,max at Low Line condition (LLINE) (low−pass filtered internal CS−pin voltage is compared to VHL and VLL for deciding whether we are in HLINE or in LLINE). Two other values of ton,max are offered as options (see Figure 9). The input current is then proportional to the input voltage. Hence, the ac line current is properly shaped. One can note that this analysis is also valid in the CrM case. This condition is just a particular case of this functioning where (t3=0), which leads to (t1+t2=T) and (Vton=Vregul). That is why the NCP1622 automatically adapts to the conditions and transitions from DCM and CrM (and vice versa) without power factor degradation and without discontinuity in the power delivery. www.onsemi.com 14 NCP1622 I ch PWM Comparator Turns off Closed when MOSFET output low Vton C ramp Vton Ramp Voltage PWM output Figure 11. PWM Circuit and Timing Diagram NCP1622 embeds a “Dynamic Response Enhancer” circuitry (DRE) that contains under−shoots. An internal comparator monitors the FB pin voltage (VFB ) and when VFB is lower than 95.5% of its nominal value, it connects a 200 mA current source to speed−up the charge of the compensation network. Effectively this appears as a 10x increase in the loop gain. The circuit also detects overshoot and immediately reduces the power delivery when the output voltage exceeds 105% of its desired level. The error amplifier OTA and the OVP, UVP and DRE comparators share the same input information. Based on the typical value of their parameters and if (Vout,nom) is the output voltage nominal value (e.g., 390 V), we can deduce: • Output Regulation Level: Vout,nom • Output DRE Level: Vout,dre = 95.5% x Vout,nom • Output Soft OVP Level: Vout,sovp = 105% x Vout,nom • Output Fast OVP level: Vout,fovp = 107% x Vout,nom NCP1622 Regulation Block and Output Voltage Control A trans−conductance error amplifier (OTA) with access to the inverting input and output is provided. It features a typical trans−conductance gain of 200 mS and a maximum current capability of ±20 mA. The output voltage of the PFC stage is typically scaled down by a resistors divider and monitored by the inverting input (pin FB). Bias current is minimized (less than 500 nA) to allow the use of a high impedance feed−back network. However, it is high enough so that the pin remains in low state if the pin is not connected. The output of the error amplifier is brought to pin VCTRL for external loop compensation. Typically a type−2 network is applied between pin VCTRL and ground, to set the regulation bandwidth below about 20 Hz and to provide a decent phase boost. The swing of the error amplifier output is limited within an accurate range: • It is forced above a voltage drop (VF ) by some circuitry. • It is clamped not to exceed 4.0 V + the same VF voltage drop. Current Sense and Zero Current Detection (Patent Filed in 2012) The VF value is 0.5 V typically. NCP1622 is designed to monitor the current flowing through the power switch during On−time for detecting over current and overstress and to monitor the power MOSFET drain voltage during demagnetization time and dead time in order to generate the ZCD signal. Given the low bandwidth of the regulation loop, abrupt variations of the load, may result in excessive over or under−shoot. Over−shoot is limited by the Over−Voltage Protection connected to FB pin (Feedback). www.onsemi.com 15 NCP1622 DRAIN DRV ZCD Vcc DEMAG & LINE SENSE VSNS R cs1 CS/ZCD pin Vcsint C cs R cs2 CSZCD BUFFER OVERSTRESS OVS BLANKING OVERSTRESS TIMER VOVS,REF DRV DRV SOURCE OCP OCP BLANKING VOCP,REF DRV Figure 12. Current Sense, Zero Current Detection Blocks and Vin Sense Current Sense Current sense, zero current detection and Vin sense are using the CS/ZCD pin voltage as depicted in the electrical schematic of Figure 12. The power MOSFET current I is sensed during the TON phase by the resistor Rsense inserted between the MOSFET source and ground (see Figure 13). During TON phase Rcs1 and Rcs2 are almost in parallel and the signal Rsense .I is equal to the voltage on pin CS. D R cs1 Rcs1 CS R dson I CS D,S C cs C cs R cs2 Rcs2 S I R sense R sense Figure 13. Current Sensing during the TON Phase www.onsemi.com 16 NCP1622 By default, the Brown−out flag is set High (BONOK=1), meaning that Vin ,sensed thru CSZCD pin and Vsns (Vsns is a low−pass filtered scaled down Vin) internal signal (see Figure 1), when higher than internal reference voltage VBOH will set the brown−out flag to zero (BONOK=0) and allow the controller to start. After BONOK is set to zero, and switching activity starts, the Vin continues to be sensed thru CSZCD pin and when Vsns falls under Brown−out internal reference voltage VBOL for 50 ms, BONOK flag will be set to 1. After BONOK flag will be set to 1, drive is not disabled, instead, a 30 mA current source is applied to VCTRL pin to gradually reduce Vctrl . As a result, the circuit only stops pulsing when the STATICOVP function is activated (that is when Vctrl reaches the SKIP detection threshold). At that moment, the circuit stops switching. This method limits any risk of false triggering. For an application w/Vaux (not using the Drain), Brown−out options ([C**] and [D**]) are not be allowed and the UVP will act like a brown−in. The reason is that before controller starts switching, the Vout voltage is equal to Vmains,rms and sensed by FB pin and compared to UVP high internal reference voltage VUVPH. The input of the PFC stage has some impedance that leads to some sag of the input voltage when the input current is large. If the PFC stage suddenly stops while a high current is drawn from the mains, the abrupt decay of the current may make the input voltage rise and the circuit detect a correct line level. Instead, the gradual decrease of Vcontrol avoids a line current discontinuity and limits the risk of false triggering. Vsns internal voltage is also used to sense the line for feed−forward. A similar method is used: • The Vsns internal pin voltage is compared to a 1.801 V reference. • If Vsns exceeds 1.801 V, the circuit detects a high−line condition and the loop gain is divided by three (the internal PWM ramp slope is three times steeper) • Once this occurs, if Vsns remains below 1.392 V for 25 ms, the circuit detects a low−line situation (500 mV hysteresis). During the On−time and after a 200 ns blanking time, an OCP (Over Current Protection) signal is generated by an OCP comparator, comparing (VCS = VCS2 ) to a 500 mV internal reference. When RsenseIds_max = VCS = VCS2 = 500 mV we get: I ds_max + V ocp R sense (eq. 4) When VCS exceeds the 500 mV internal reference threshold, the OCP signal turns high to reset the PWM latch and forces the driver low. The 200 ns blanking time prevents the OCP comparator from tripping because of the switching spikes that occur when the MOSFET turns on. Zero Current Detection The CS pin is also designed to receive, during tDEMAG and tDT, a scaled down (divided by 138) power MOSFET drain voltage that will be used for Zero Current Detection. It may happen that the MOSFET turns on while a huge current flows through the inductor. As an example such a situation can occur at start−up when large in−rush currents charge the bulk capacitor to the line peak voltage. Traditionally, a bypass diode is generally placed between the input and output high−voltage rails to divert this inrush current. If this diode is accidently shorted, the demagnetization will be impossible and cycle after cycle the inductor current will increase so the MOSFET will also see a high current when it turns on. In both cases, the current can be large enough to trigger the OverStress (OVS) comparator. In this case, the “OverStress” signal goes high and disables the driver for an 800 ms delay. This long delay leads to a very low duty−ratio operation in case of “OverStress” fault in order to limit the risk of overheating. When no signal is received that triggers the ZCD comparator to indicate the end of inductor demagnetization, an internal 200 ms watchdog timer initiates the next drive pulse. At the end of this delay, the circuit senses the CS/ZCD pin impedance to detect a possible grounding of this pin and prevent operation. Brown−Out Detection (Versions [C**] and [D**]) For an application w/o Vaux (using the Drain) and using Brown−out options ([C**] and [D**]) the Brown−out feature will use the High and Low Brown−out levels. Brown−out options ([C**] and [D**]) must not be used on an application using Vaux as these options are not designed to work in this case. At startup, the circuit is in High−line state (“LLINE” Low”) and then Vsns will be used to determine the High−Line or Low−Line state. The line range detection circuit allows more optimal loop gain control for universal (wide input mains) applications. www.onsemi.com 17 NCP1622 CSint VSNS Timer 25 ms CS/ZCD VREF,LLINE DEMAG & LINE SENSE CSZCD BUFFER LLINE 1.801 V if LLINE = 1 1.392 V otherwise DRV Timer 50 ms BONOK VREF,BONOK 0.819 V if BONOK = 1 0.737 V otherwise Figure 14. Input Line Sense Monitoring Thermal Shut−Down (TSD) (100 mV hysteresis), and after a 1 ms leading edge blanking time, the OVP2 flag is latched and will stop the switching by resetting the main PWM latch. The OVP2 latch is reset each 800 ms. An internal thermal circuitry disables the circuit gate drive and keeps the power switch off when the junction temperature exceeds 150°C. The output stage is then enabled once the temperature drops below about 100°C (50°C hysteresis). The temperature shutdown remains active as long as the circuit is not reset, that is, as long as VCC is higher than a reset threshold. OFF Mode As previously mentioned, the circuit turns off when one of the following faults is detected: • Incorrect feeding of the circuit (“UVLO” high when VCC