NCP1632DR2G

Power Factor Controller, Interleaved, 2-Phase NCP1632 The NCP1632 integrates a dual MOSFET driver for interleaved PFC applications. Interleaving consists of paralleling two small stages in lieu of a bigger one, more difficult to design. This approach has several merits like the ease of implementation, the use of smaller components or a better distribution of the heating. Also, Interleaving extends the power range of Critical Conduction Mode that is an efficient and cost−effective technique (no need for low trr diodes). In addition, the NCP1632 drivers are 180° phase shifted for a significantly reduced current ripple. Housed in a SOIC16 package, the circuit incorporates all the features necessary for building robust and compact interleaved PFC stages, with a minimum of external components. General Features • Near−Unity Power Factor • Substantial 180° Phase Shift in All Conditions Including Transient • • • • • • • • • Phases Frequency Clamped Critical Conduction Mode (FCCrM) i.e., Fixed Frequency, Discontinuous Conduction Mode Operation with Critical Conduction Achievable in Most Stressful Conditions FCCrM Operation Optimizes the PFC Stage Efficiency Over the Load Range Out−of−phase Control for Low EMI and a Reduced rms Current in the Bulk Capacitor Frequency Fold−back at Low Power to Further Improve the Light Load Efficiency Accurate Zero Current Detection by Auxiliary Winding for Valley Turn On Fast Line / Load Transient Compensation High Drive Capability: −500 mA / +800 mA Signal to Indicate that the PFC is Ready for Operation (“pfcOK” Pin) VCC Range: from 10 V to 20 V Safety Features www.onsemi.com MARKING DIAGRAM NCP1632G AWLYWW SOIC−16 D SUFFIX CASE 751B A WL Y WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN ASSIGNMENT ZCD2 FB ZCD1 1 REF5V/pfcOK Rt DRV1 GND OSC Vcc Vcontrol FFOLD DRV2 BO Latch OVP / UVP CS (Top View) ORDERING INFORMATION Device Package Shipping† NCP1632DR2G SOIC−16 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. • Output Over and Under Voltage Protection • Brown−Out Detection with a 500−ms Delay to Help Meet Hold−up • • • • Time Specifications Soft−Start for Smooth Start−up Operation Programmable Adjustment of the Maximum Power Over Current Limitation Detection of Inrush Currents Typical Applications • Computer Power Supplies • LCD / Plasma Flat Panels • All Off Line Appliances Requiring Power Factor Correction © Semiconductor Components Industries, LLC, 2017 April, 2020 − Rev. 7 1 Publication Order Number: NCP1632/D NCP1632 VIN RBO1 RBO2 Dbypass VOUT pfcOK R OUT1 R OVP1 RZCD2 ZCD2 R OUT3 ROVP2 C FF in EMI Filter ROVP3 CIN C BO2 FB RT OVP RBO3 L2 VAUX2 R OUT2 Ac line VOUT ROSC COSC CCOMP2 RCOMP1 Rt RFOLD CFOLD CCOMP1 OSC Vcontrol FFOLD BO OVP/UVP 1 ZCD1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 RZCD1 L1 D1 pfcOK C pfcOK DRV1 VAUX2 D2 M1 GND VCC CVCC M2 DRV2 Latch CS CBULK ROCP OVPin RCS Figure 1. Typical Application Schematic Table 1. MAXIMUM RATINGS Symbol VCC(MAX) VMAX VControl(MAX) PD RqJ−A TJ Rating Pin Value Unit 12 −0.3, +20 V 1, 2, 3, 4, 6, 7, 8, 9, 10, 15, and 16 −0.3, +9.0 V 5 −0.3, VControl(clamp) (Note 2) V 550 145 mW °C/W −40 to +150 °C 150 °C −65 to +150 °C 300 °C 3 kV ESD Capability, Machine Model (Note 3) 200 V ESD Capability, Charged Device Model (Note 3) 1000 V Maximum Power Supply Voltage Continuous Maximum Input Voltage on Low Power Pins) (Note 1) VControl Pin Maximum Input Voltage Power Dissipation and Thermal Characteristics Maximum Power Dissipation @ TA = 70°C Thermal Resistance Junction−to−Air Operating Junction Temperature Range TJ(MAX) Maximum Junction Temperature TS(MAX) Storage Temperature Range TL(MAX) Lead Temperature (Soldering, 10s) ESD Capability, HBM model (Note 3) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. These maximum ratings (−0.3 V / 9.0 V) guarantee that the internal ESD Zener diode is not turned on. More positive and negative voltages can be applied to the ZCD1 pin if the ESD Zener diode current is limited to 5 mA maximum. Typically, as detailed in the Zero Current Detection section, an external resistor is to be placed between the ZCD1 pin and its driving voltage to limit the ZCD1 source and sink currents to 5 mA or less. See Figure 2 and application note AND9654 for more details. The same is valid for the ZCD2 pin. 2. “VControl(clamp)” is the pin5 clamp voltage. 3. This device(s) contains ESD protection and exceeds the following tests: Human Body Model 2000 V per JEDEC Standard JESD22−A114E Machine Model Method 200 V per JEDEC Standard JESD22−A115−A Charged Device Model Method 1000 V per JEDEC Standard JESD22−C101E 4. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. www.onsemi.com 2 NCP1632 RZCD1 IZCD1 ZCD1 pin VAUX1 GND ESD Zener Diode ZCD1 ZCD1 Circuitry Circuitry NCP1632 Figure 2. Limit the ZCD1 pin current (IZCD 1) between – 5 mA and 5 mA (the same is valid for the ZCD2 pin) www.onsemi.com 3 NCP1632 Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE (Conditions: VCC = 15 V, Vpin7 = 2 V, Vpin10 = 0 V, TJ from −40°C, to +125°C, unless otherwise specified) Characteristics Test Conditions Symbol Min Typ Max Unit VCC increasing VCC decreasing VCC decreasing VCC(on) VCC(off) VCC(hyst) VCC(reset) 11 9.4 1.5 4.0 12 10 2.0 6.0 13 10.4 − 7.5 VCC = 9.4 V ICC(start) − 50 100 Fsw = 130 kHz (Note 5) VCC = 15 V, Vpin10 = 5 V VCC = 15 V, pin 7 grounded VFB = 3 V ICC1 ICC(latch) ICC(off) ICC(SKIP) − – − − 3.5 0.4 0.4 − 7.0 0.8 0.8 2.1 Pin 6 open ICH 126 140 154 mA STARTUP AND SUPPLY CIRCUITS Supply Voltage Startup Threshold Minimum Operating Voltage Hysteresis VCC(on) – VCC(off) Internal Logic Reset Startup current Supply Current Device Enabled/No output load on pin6 Current that discharges VCC in latch mode Current that discharges VCC in OFF mode SKIP Mode Consumption V mA mA OSCILLATOR AND FREQUENCY FOLDBACK Charge Current Maximum Discharge Current Pin 6 open IDISCH 94.5 105 115.5 mA IFFOLD over ICS ratio ICS = 30 mA RFFOLD30 − 1 − - Pin 6 source current ICS = 30 mA IFFOLD30 28 30 32 mA VOSC(high) − 5 − V Oscillator Upper Threshold Oscillator Lower Threshold VFFOLD = 4.2 V, VFFOLD falling VFFOLD = 3.8 V, VFFOLD falling VFFOLD = 3.8 V, VFFOLD rising VFFOLD = 2.0 V, VFFOLD falling VFFOLD = 0.8 V, VFFOLD falling VOSC(low) 3.6 3.6 2.7 1.8 0.8 4.0 4.0 3.0 2.0 1.0 4.4 4.4 3.3 2.2 1.1 V Oscillator Swing (Note 6) VFFOLD = 4.2 V, VFFOLD falling VFFOLD = 3.8 V, VFFOLD falling VFFOLD = 3.8 V, VFFOLD rising VFFOLD = 2.0 V, VFFOLD falling VFFOLD = 0.8 V, VFFOLD falling VOSC(swing) 0.90 0.90 1.90 2.85 3.80 1.00 1.00 2.00 3.00 4.00 1.05 1.05 2.10 3.15 4.20 V Ipin9 = 100 mA Ipin9 = 10 mA VCS(TH100) VCS(TH10) −20 −10 0 0 20 10 mV TJ = 25°C TJ = −40°C to 125°C IILIM1 IILIM2 202 194 210 210 226 226 mA Iin−rush 11 14 17 mA RSNK1 RSRC1 RSNK2 RSRC2 – – – – 7 15 7 15 15 25 15 25 CURRENT SENSE Current Sense Voltage Offset Current Sense Protection Threshold Threshold for In−rush Current Detection GATE DRIVE (Note 8) Drive Resistance DRV1 Sink DRV1 Source DRV2 Sink DRV2 Source Ω Ipin14 = 100 mA Ipin14 = −100 mA Ipin11 = 100 mA Ipin11 = −100 mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz. 6. Not tested. Guaranteed by design. 7. Not tested. Guaranteed by design and characterization. 8. Guaranteed by design, the VCC pin can handle the double of the DRV peak source current, that is, 1 A typically. www.onsemi.com 4 NCP1632 Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE (Conditions: VCC = 15 V, Vpin7 = 2 V, Vpin10 = 0 V, TJ from −40°C, to +125°C, unless otherwise specified) Characteristics Test Conditions Symbol Min Typ Max VDRV1 = 10 V VDRV1 = 0 V VDRV2 = 10 V VDRV2 = 0 V ISNK1 ISRC1 ISNK2 ISRC2 − − − − 800 500 800 500 − − − − Rise Time DRV1 DRV2 CDRV1 = 1 nF, VDRV1 = 1 to 10 V CDRV2 = 1 nF, VDRV2 = 1 to 10 V tr1 tr2 − − 40 40 − − Fall Time DRV1 DRV2 CDRV1 = 1 nF, VDRV1 = 10 to 1 V CDRV2 = 1 nF, VDRV2 = 10 to 1 V tf1 tf2 – – 20 20 – – VREF 2.44 2.50 2.56 Unit GATE DRIVE (Note 8) Drive Current Capability (Note 6) DRV1 Sink DRV1 Source DRV2 Sink DRV2 Source mA ns ns REGULATION BLOCK Feedback Voltage Reference Error Amplifier Source Current Capability @ Vpin2 = 2.4 V IEA(SRC) Error Amplifier Sink Current Capability @ Vpin2 = 2.6 V IEA(SNK) Error Amplifier Gain −20 V mA +20 GEA 115 200 285 mS pfcOK high pfcOK low IControl(boost) 175 55 220 70 265 85 mA Vpin2 = 2.5 V IFB(bias) −500 500 nA @ Vpin2 = 2.4 V @ Vpin2 = 2.6 V VControl(clamp) VControl(MIN) VControl(range) − − 2.8 3.6 0.6 3 − − 3.5 V Ratio (Vout(low) Detect Threshold / VREF) (Note 6) FB falling Vout(low)/VREF 95.0 95.5 96.0 % Ratio (Vout(low) Detect Hysteresis / VREF) (Note 6) FB rising Hout(low)/VREF − − 0.5 % VFB = 3 V DMIN − − 0 % Vpin7 = 1.1 V, Ipin3 = 50 mA (Note 6) Vpin7 = 1.1 V, Ipin3 = 200 mA Vpin7 = 2.2 V, Ipin3 = 100 mA Vpin7 = 2.2 V, Ipin3 = 400 mA ton1 ton2 ton3 ton4 14.5 1.10 4.00 0.34 19.5 1.35 5.00 0.41 22.5 1.60 6.00 0.50 ms VBO = Vpin7 = 1.1 V, Ipin3 = 50 mA VBO = Vpin7 = 1.1 V, Ipin3 = 200 mA VBO = Vpin7 = 2.2 V, Ipin3 = 50 mA VBO = Vpin7 = 2.2 V, Ipin3 = 200 mA VRt1 VRt2 VRt3 VRt4 1.068 1.068 2.165 2.165 1.096 1.096 2.196 2.196 1.126 1.126 2.228 2.228 V Not tested Vton(MAX) Pin 5 Source Current when (Vout(low) Detect) is activated Pin2 Bias Current Pin 5 Voltage: SKIP MODE Duty Cycle RAMP CONTROL (valid for the two phases) Maximum DRV1 and DRV2 On−Time (FB pin grounded) Pin 3 voltage Maximum Vton Voltage Pin 3 Current Capability IRt(MAX) Pin 3 sourced current below which the controller is OFF IRt(off) 5 1 − 7 V − mA mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz. 6. Not tested. Guaranteed by design. 7. Not tested. Guaranteed by design and characterization. 8. Guaranteed by design, the VCC pin can handle the double of the DRV peak source current, that is, 1 A typically. www.onsemi.com 5 NCP1632 Table 2. TYPICAL ELECTRICAL CHARACTERISTICS TABLE (Conditions: VCC = 15 V, Vpin7 = 2 V, Vpin10 = 0 V, TJ from −40°C, to +125°C, unless otherwise specified) Characteristics Test Conditions Symbol Min (Note 6) IRt(range) 20 0.40 0.20 Typ Max Unit 1000 mA 0.60 0.30 V RAMP CONTROL (valid for the two phases) Pin 3 Current Range ZERO VOLTAGE DETECTION CIRCUIT (valid for ZCD1 and ZCD2) ZCD Threshold Voltage VZCD increasing VZCD falling VZCD(TH),H VZCD(TH),L ZCD Hysteresis VZCD decreasing VZCD(HYS) Ipin1 = 5.0 mA Ipin1 = −5.0 mA VZCD(high) VZCD(low) Input Clamp Voltage High State Low State 0.50 0.25 0.25 V V 9.0 −1.1 11 −0.65 13 −0.1 Internal Input Capacitance (Note 6) CZCD − 10 − pF ZCD Watchdog Delay tZCD 80 200 320 ms VBO(TH) 0.97 1.00 1.03 V IBO 6 7 8 mA Brown−Out Blanking Time (Note 6) tBO(BLANK) 380 500 620 ms Brown−Out Monitoring Window (Note 6) tBO(window) 38 50 62 ms VBO(clamp) − 965 − mV IBO(clamp) 100 − − mA VBO(HYS) 10 35 60 mV IBO(PNP) 100 − − mA VBO(PNP) 0.35 0.70 0.90 V VOVP 2.425 2.500 2.575 V Ratio (VOVP / VREF) (Note 6) VOVP/VREF 99.2 99.7 100.2 % Ratio UVP Threshold over VREF VUVP/VREF 8 12 16 % IOVP(bias) −500 − 500 nA VLatch 140 166 200 mV Vpin10 = 2.3 V ILatch(bias) −500 − 500 nA Pin 15 Voltage Low State Vpin7 = 0 V, Ipin15 = 250 mA VREF5V(low) − 60 120 mV Pin 15 Voltage High State Vpin7 = 0 V, Ipin15 = 5 mA VREF5V(high) 4.7 5.0 5.3 V IREF5V 5 10 − mA TSHDN 130 140 150 °C TSHDN(HYS) − 50 − °C BROWN−OUT DETECTION Brown−Out Comparator Threshold Brown−Out Current Source Pin 7 clamped voltage if VBO < VBO(TH) during tBO(BLANK) Ipin7 = −100 mA Current Capability of the BO Clamp Hysteresis VBO(TH) – VBO(clamp) Ipin7 = − 100 mA Current Capability of the BO pin Clamp PNP Transistor Pin BO voltage when clamped by the PNP Ipin7 = − 100 mA OVER AND UNDER VOLTAGE PROTECTIONS Over−Voltage Protection Threshold Pin 8 Bias Current Vpin8 = 2.5 V Vpin8 = 0.3 V LATCH INPUT Pin Latch Threshold for Shutdown Pin Latch Bias Current pfcOK / REF5V Current Capability THERMAL SHUTDOWN Thermal Shutdown Threshold (Note 6) Thermal Shutdown Hysteresis Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. DRV1 and DRV2 pulsating at half this frequency, that is, 65 kHz. 6. Not tested. Guaranteed by design. 7. Not tested. Guaranteed by design and characterization. 8. Guaranteed by design, the VCC pin can handle the double of the DRV peak source current, that is, 1 A typically. www.onsemi.com 6 NCP1632 Table 3. DETAILED PIN DESCRIPTION Pin number Name Function 1 ZCD2 This is the zero current detection pin for phase 2 of the interleaved PFC stage. It is designed to monitor the voltage of an auxiliary winding to detect the inductor core reset and the valley of the MOSFET drain source voltage 2 FB This pin receives the portion of the PFC stage output voltage for regulation. VFB is also monitored by the dynamic response enhancer (DRE) which drastically speeds−up the loop response when the output voltage drops below 95.5 % of the wished level. 3 RT The resistor placed between pin 3 and ground adjusts the maximum on−time in both phases, and hence the maximum power that can be delivered by the PFC stage. 4 OSC Oscillator pin. The oscillator sets the maximum switching frequency, particularly in medium− and light−load conditions when frequency foldback is engaged. 5 VCONTROL The error amplifier output is available on this pin for loop compensation. The capacitors and resistor connected between this pin and ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high Power Factor ratios. Pin5 is grounded when the circuit is off so that when it starts operation, the power increases gradually (soft−start). 6 FFOLD (Freq. Foldback) This pin sources a current proportional to the input current. Placing a resistor and a capacitor between the FFOLD pin and GND, we obtain the voltage representative of the line current magnitude necessary to control the frequency foldback characteristics. 7 BO (Brown−out Protection) Apply an averaged portion of the input voltage to detect brown−out conditions when VBO drops below 1 V. A 500−ms internal delay blanks short mains interruptions to help meet hold−up time requirements. When it detects a brown−out condition, the circuit stops pulsing and grounds the “pfcOK” pin to disable the downstream converter. Also an internal 7−mA current source is activated to offer a programmable hysteresis. The pin2 voltage is internally re−used for feed−forward. Ground pin 2 to disable the part. 8 OVP / UVP The circuit turns off when Vpin8 goes below VUVP (300 mV typically – UVP protection) and disables the drive when the pin voltage exceeds VOVP (2.5 V typically − OVP protection). 9 CS (current sense) The CS pin monitors a negative voltage proportional to the input current to limit the maximum current flowing in the phases. The NCP1632 also uses the CS information to prevent the PFC stage from starting operation in presence of large in−rush currents. 10 Latch Apply a voltage higher than VSTDWN (166 mV typically) to latch−off the circuit. The device is reset by unplugging the PFC stage (practically when the circuit detects a brown−out detection) or by forcing the circuit VCC below VCCRST (4 V typically). Operation can then resume when the line is applied back. 11 DRV2 This is the gate drive pin for phase 2 of the interleaved PFC stage. The high−current capability of the totem pole gate drive (+0.5/−0.8A) makes it suitable to effectively drive high gate charge power MOSFETs. 12 VCC This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 12 V and turns off when VCC goes below 10 V (typical values). After start−up, the operating range is 10.5 V up to 20 V. 13 GND Connect this pin to the pre−converter ground. 14 DRV1 This is the gate drive pin for phase 1 of the interleaved PFC stage. The high−current capability of the totem pole gate drive (+0.5/−0.8A) makes it suitable to effectively drive high gate charge power MOSFETs. 15 REF5V / pfcOK 16 ZCD1 The pin15 voltage is high (5 V typically) when the PFC stage is in a normal, steady state situation and low otherwise. This signal serves to “inform” the downstream converter that the PFC stage is ready and that hence, it can start operation. This is the zero current detection pin for phase 1 of the interleaved PFC stage. It is designed to monitor the voltage of an auxiliary winding to detect the inductor core reset and the valley of the MOSFET drain source voltage www.onsemi.com 7 NCP1632 pfcOK DRE COMP 0.955*Vref 150 mA Vref Internal Thermal Shutdown + 50 mA − Regul Iref TSD VDD Vcc VDD Stdwn FB Error Amplifier − V ref UVP Vcc_OK +/-20mA BO_NOK + Vcontrol V CC(on) / VCC(off) UVLO OFF Fault management SKIP OVLflag1 BO_NOK V OPAMP OFF 4R OCP V REGUL 3V V BO 5R OVP VOSC(low) SKIP CLK2 OFF Freq foldback BO Brown−out detection with 500−ms delay STOP Oscillator low threshold control DT Vton processing circuitry V OPAMP Vcc S Vpwm2 L R Output Buffer 2 DRV2 Output Buffer 1 DRV1 Q pwm2 STOP V BO Generation of the charge current for the Internal timing capacitors (max on−time setting for the twophases) Ich DRV2 Vton CLK1 Vpwm1 Vpwm1 On−time control for the two phases L R pwm1 STOP CLK1 VDMG2 Oscillator block with interleaving and frequency foldback CLK2 VZCD1 Zero current detection for phase 2 Q Vpwm2 In−rush ZCD2 Vcc S All the RS latches are RESET dominant OUTon2 VZCD1 V ZCD2 VZCD1 Zero current detection for phase 1 DT OFF Lstup Q R Current Sense Block (Building of I CS proportional to I in) UVP − OCP OVP − In−rush Ics > I in−rush Vcc < VccRST Ics CS Qzcd1 stdwn R Q Q zcd2 Lstdwn DRV1 − S + latch−off V STDWN Ics > IILIM1 − V OVP pfcOK / REF5V S OUTon1 + pfcOK Stup + V UVP VOSC(low) OFF OVLflag1 OVP OSC REF5V VDMG1 ZCD1 In−rush + Rt DRV1 DRV2 Figure 3. Block Diagram www.onsemi.com 8 GND NCP1632 DETAILED OPERATING DESCRIPTION Introduction The NCP1632 is an interleaving, 2−phase PFC controller. It is designed to operate in critical conduction mode (CrM) in heavy load conditions and in discontinuous conduction mode (DCM) with frequency foldback in light load for an optimized efficiency over the whole power range. In addition, the circuit incorporates protection features for a rugged operation. More generally, the NCP1632 functions make it the ideal candidate in systems where cost−effectiveness, reliability, low stand−by power, high−level efficiency over the load range and near−unity power factor are the key parameters: • Accurate and robust interleaving management: The NCP1632 modulates the oscillator swing as a function of the current cycle duration to control the delay between the two branches drive pulses. This ON proprietary method is a simple but robust and stable solution to interleave the two branches. The 180−degree phase shift is ensured in all situations (including transient phases) and whatever the operation mode is (CrM or DCM). • Frequency fold−back and skip−cycle capability for low power stand−by: The NCP1632 optimizes the efficiency of your PFC stage over the whole load range. In medium− and light−load conditions, the switching frequency can linearly decay as a function of the line current magnitude (FFOLD mode) down to about 30 kHz at very low power (depending on the OSC pin capacitor). To prevent any risk of regulation loss at no load and to further minimize the consumed power, the circuit skips cycles when the error amplifier output reaches its low clamp level. • Fast Line / Load Transient Compensation: by essence, PFC stages are slow systems. Thus, the output voltage of PFC stages may exhibit excessive over− and under−shoots because of abrupt load or input voltage variations (e.g. at start−up). The NCP1632 incorporates a fast line / load compensation to avoid such large output voltage variations. Practically, the circuit monitors the output voltage and: ♦ Disables the drive to stop delivering power as long as the output voltage exceeds the over voltage protection (OVP) level. ♦ Drastically speeds−up the regulation loop (Dynamic Response Enhancer) when the output voltage is below 95.5 % of its regulation level. This function is partly disabled during the startup phase to ensure a gradual increase of the power delivery (soft−start). • PFC OK: the circuit detects when the circuit is in normal situation or if on the contrary, it is in a start−up or fault condition. In the first case, the pfcOK pin is in • • high state and low otherwise. The pfcOK pin serves to control the downstream converter operation in response to the PFC state. Output Stage Totem Pole: the NCP1632 incorporates a −0.5 A / +0.8 A gate driver to efficiently drive most TO220 or TO247 power MOSFETs. Safety Protections: the NCP1632 permanently monitors the input and output voltages, the inductor current and the die temperature to protect the system from possible over−stresses and make the PFC stage extremely robust and reliable. In addition to the aforementioned OVP protection, one can list: ♦ Maximum Current Limit: the circuit permanently senses the input current for over current protection and in−rush currents detection, for preventing the excessive stress suffered by the MOSFETs if they turned on when large in−rush currents take place. ♦ Zero Current Detection: the NCP1632 prevents the MOSFET from closing until the inductor current is zero, to ensure discontinuous conduction mode operation in each branch. ♦ Under−Voltage Protection: the circuit turns off when it detects that the output voltage goes below 12% of the OVP level (typically). This feature protects the PFC stage from starting operation in case of too low ac line conditions or in case of a failure in the OVP monitoring network (e.g., bad connection). ♦ Brown−Out Detection: the circuit detects too low ac line conditions and stop operating in this case. This protection protects the PFC stage from the excessive stress that could damage it in such conditions. ♦ Thermal Shutdown: an internal thermal circuitry disables the circuit gate drive and then keeps the power switch off when the junction temperature exceeds 150°C typically. The circuit resumes operation once the temperature drops below about 100°C (50°C hysteresis). Interleaving An interleaved PFC converter consists of two paralleled PFC stages operated out−of−phase. Each individual stage is generally termed phase, channel or branch. If the input current is well balanced, each phase processes half the total power. The size and cost of each individual branch is hence accordingly minimized and losses are spitted between the two channels. Hence, hot spots are less likely to be encountered. Also, if the interleaving solution requires more components, they are smaller and often more standard. In addition, they can more easily fit applications with specific form−factors as required in thin flat panel TVs for instance. www.onsemi.com 9 NCP1632 Furthermore, if the two channels are properly operated out−of−phase, a large part of the switching−frequency ripple currents generated by each individual branch cancel when they add within the EMI filter and the bulk capacitors. As a result, EMI filtering is significantly eased and the bulk capacitor rms current is drastically reduced. Interleaving therefore extends the CrM power range by sharing the task between the two phases and by allowing for a reduced input current ripple and a minimized bulk capacitor rms current. Vin I(in ILtot This is why this approach which at first glance, may appear more costly than the traditional 1−phase solution can actually be extremely cost−effective and efficient for powers above 300 watts. And even less for applications like LCD and Plasma TV applications where the need for smaller components, although more numerous, helps meet the required low−profile form−factors. Branch 1 IIL 1 IID1 ) Vaux 1 Acline 2 3 4 5 6 EMI Filter 7 Cin 8 Branch 2 IIL 2 16 NCP1632 NCP1631 1 IIin line IID 2 15 14 13 12 11 IID( tot ) Vaux 2 Vcc Vout 10 Cbulk 9 Rsense LOAD Figure 4. Interleaved PFC Stage starts. The current ramps down until it reaches zero. The duration of this phase is (t2). The system enters then the dead−time (t3) that lasts until the next clock is generated. The ac line current is the averaged inductor current as the result of the EMI filter “polishing” action. Hence, the line current produced by one of the phase is: The NCP1632 manages the 180−degree phase shift between the two branches by modulating the oscillator swing as a function of the current cycle duration in the inductor of each individual phase. This ON proprietary technique ensures an accurate, stable and robust control of the delay between the two branches in all situations (including transient phases) and whatever the operation mode is (CrM or DCM). The NCP1632 is a voltage mode controller. As a result, the input current is optimally shared between the two branches if they have an inductor of same value. If the inductances differ, out−of−phase operation will not be affected. Simply, the branch embedding the lowest−value inductor, will process more power as: L Pbranch1 + branch2 Pbranch2 L branch1 Iin + V in t1(t 1 ) t 2) 2T L (eq. 2) Where (T = t1 + t2 + t3) is the switching period and Vin is the ac line rectified voltage. (eq. 1) Inductor typical deviation being below ±5%, the power between 2 branches should not differ from more than 10%. Provided its interleaving capability, the protections it features and the medium− to light−load efficiency enhancements it provides compared to traditional CrM circuits, the NCP1632 is more than recommendable for powers up to 600 W with universal mains and up to 1 kW in narrow mains applications. Figure 5. Current Cycle Within a Branch Eq. 2 shows that the input current is proportional to the ⎛ t1 (t1 + t2 ) ⎞ ⎢ ⎟ ⎢ ⎟ T ⎠ is a constant. input voltage if ⎝ This is what the NCP1632 does. Using the “Vton processing block” of Figure 5, the NCP1632 modulates t1 NCP1632 On−time Modulation The NCP1632 incorporates an on−time modulation circuitry to support both the critical and discontinuous conduction modes. Figure 5 portrays the inductor current absorbed in one phase of the interleaved PFC stage. The initial inductor current of each switching cycle is always zero. The inductor current ramps up when the MOSFET is on. The slope is (VIN /L) where L is the inductor value. At the end of the on−time (t1), the coil demagnetization phase ⎛ t1 (t1 + t2 ) ⎞ ⎢ ⎟ ⎢ ⎟ T ⎝ ⎠ remains a constant: so that Ct @ VREGUL t1(t 1 ) t2) + T It (eq. 3) Where Ct and It respectively, are the capacitor and charge current of the internal ramp used to control the on−time and www.onsemi.com 10 NCP1632 VREGUL is the signal derived from the regulation block which adjusts the on−time. This ON Semiconductor proprietary technique makes the NCP1632 able to support the Frequency Clamped Critical conduction mode of operation, that is, to operate in discontinuous− or in critical−conduction mode according to the conditions, without degradation of the power factor. Critical conduction mode is naturally obtained when the inductor current cycle is longer than the minimum period controlled by the oscillator. Discontinuous conduction mode is obtained in the opposite situation. In this case, the switching frequency is clamped. Hence, the averaged current absorbed by one of the phase of the PFC converter: Iin(phase1) + I in(phase2) + V in C t @ VREGUL @ 2L It Iin(rms) + (eq. 4) Vpin7 + 2 Ǹ2 Vin(rms) Rbo2 p R bo1 ) Rbo2 Hence, the input current is then proportional to the input voltage and the ac line current is properly shaped. This analysis is valid for DCM but also CrM which is just a particular case of this functioning where (t3 = 0). As a result, the NCP1632 automatically adapts to the conditions and jumps from DCM and CrM (and vice versa) without power factor degradation and without discontinuity in the power delivery. The total current absorbed by the two phases is then: Ton,max(ms) ^ 50 @ 10 *9 @ ǒ 2 Iin(rms) ^ Pin(avg) ^ (eq. 10) Ǔ @VV ǒ R 62 @ 10 *14 @ Rt @ 1 ) bo1 L R bo2 PWM comparator + to PWM latch − OA1 Vton SKIP − S3 C1 OC P 0.5* (I se nse − 210 m) S1 S2 −> V ton d u ring (t1+t2) −> 0 V d u ring t3 (d e a d −time) −> V ton *(t1+t2)/T in average 2 2 REGUL REGUL(max) Ǔ @VV 2 REGUL REGUL(max) (eq. 12) timing capacitor s aw −too th IN 1 Vpin7 R 62 @ 10 *14 @ Rt @ 1 ) bo1 L @ Vin(rms) R bo2 This leads to the following line rms current and average input power: R1 2 (eq. 11) (eq. 6) + Rt From this, we can deduce the input current and power expressions: 2 VREGUL (eq. 9) where Rbo1 and Rbo2 are the scaling down resistors for BO sensing (see brown−out section) In addition, It is programmed by the pin 3 resistor so that the maximum on−time obtained when VREGUL is max (1.66 V) is given by: (eq. 5) C t @ V REGUL @ V in L @ It (eq. 8) Feedforward: The Ct timing capacitors (one per phase) are internal and are well matched for an optimal current balancing between the two branches of the interleaved converter. As detailed in the brown−out section, the It current is internally processed to be proportional to the square of the voltage applied to the BO pin (pin 7). Since the BO pin is designed to receive a portion of the average input voltage, the It current is proportional to the square of the line magnitude which provides feedforward. In a typical application, the BO pin voltage is hence: ⎡ C ⋅V ⎤ k = ⎪ t REGUL ⎥ ⎣ 2 ⋅ L ⋅ It ⎦ ). Where k is a constant ( Iin(total) + (eq. 7) C t @ V REGUL 2 Pin(avg) + @ V in(rms) L @ It Given the regulation low bandwidth of PFC systems, (VCONTROL ) and then (VREGUL ) are slow varying signals. Hence, the line current absorbed by each phase is: Iin(phase1) + I in(phase2) + k @ Vin C t @ V REGUL @ V in(rms) L @ It OV P OF F VBOcomp (from BO block) pfcOK DT (high during dead−time) Figure 6. Vton Processing Circuit www.onsemi.com 11 In−rus h NCP1632 Regulation Block and Low Output Voltage Detection The swing of the error amplifier output is limited within an accurate range: • It is maintained above a lower value (VF – 0.6 V typically) by the “low clamp” circuitry. When this circuitry is activated, the power demand is minimum and the NCP1632 enters skip mode (the controller stops pulsating) until the clamp is no more active. • It is clamped not to exceed 3.0 V + the same VF voltage drop. A trans−conductance error amplifier with access to the inverting input and output is provided. It features a typical trans−conductance gain of 200 mS and a typical capability of ±20 mA. The output voltage of the PFC stage is typically scaled down by a resistors divider and monitored by the inverting input (feed−back pin – pin2). The bias current is minimized (less than 500 nA) to allow the use of a high impedance feed−back network. The output of the error amplifier is pinned out for external loop compensation (pin5). A type−2 compensator is generally applied between pin5 and ground, to set the regulation bandwidth in the range of 20 Hz, as need in PFC applications (refer to application note AND8407). Hence, Vpin5 features a 3 V voltage swing. Vpin5 is then offset down by (VF) and divided by three before it connects to the “Vton processing block” and the PWM section. Finally, the output of the regulation is a signal (“VREGUL” of the block diagram) that varies between 0 and 1.66 V. Dynamic Response Enhancer Vout low detect pfcOK 150 m A − FB REGUL + 0.955*Vref V 50 m A 1.66 V E rr o r Am p lifier − + Vref ±20 m A V control VF OFF 4R VREGUL 3V V VF CONTROL 5R VF Figure 7. Regulation Block 3 V + VF Figure 8. VREGUL versus VCONTROL Zero Current Detection Provided the low bandwidth of the regulation loop, sharp variations of the load, may result in excessive over and under−shoots. Over−shoots are limited by the Over−Voltage Protection (see OVP section). A dynamic Response Enhancer circuitry (DRE) is embedded to contain the under−shoots. Practically, an internal comparator monitors the feed−back signal (VFB ) and connects a 200 mA current source to speed−up the charge of the compensation network when VFB is lower than 95.5% of its nominal value. Finally, it is like if the comparator multiplied the error amplifier gain by about 10. One must note that a large part of the DRE current source (150 mA out of 200 mA) cannot be enabled until the converter output voltage has reached its target level (that is when the “pfcOK” signal of the block diagram, is high). This is because, at the beginning of operation, it is generally welcome that the compensation network charges slowly and gradually for a soft start−up. While the on time is constant, the core reset time varies with the instantaneous input voltage. The NCP1632 detects the demagnetization completion by sensing the inductor voltage. Sensing the voltage across the inductor allows an accurate zero current detection, more specifically, by detecting when the inductor voltage drops to zero. Monitoring the inductor voltage is not an economical solution. Instead, a smaller winding is taken off of the boost inductor. This winding (called the “zero current detection” or ZCD winding) gives a scaled version of the inductor voltage that is easily usable by the controller. Furthermore, this ZCD winding is coupled so that it exhibits a negative voltage during the MOSFET conduction time (flyback configuration) as portrayed by Figure 9. In that way, the ZCD voltage (“VAUX”) falls and starts to ring around zero volts when the inductor current drops to www.onsemi.com 12 NCP1632 zero. The NCP1632 detects this falling edge and prevents any new current cycle until it is detected. Figure 9 shows how it is implemented. For each phase, a ZCD comparator detects when the voltage of the ZCD winding exceeds its upper threshold (0.5 V typically). When this is the case, the coil is in demagnetization phase and the latch LZCD is set. This latch is reset when the next driver pulse occurs. Hence the output of this latch (QZCD) is high during the whole off−time (demagnetization time + any possible dead time). The output of the comparator is also inverted to form a signal which is AND’d with the QZCD output so that the AND gate output (VZCD) turns high when the VAUX voltage goes below zero (below the 0.25 V lower threshold of the ZCD comparator to be more specific). As a result, the ZCD circuitry detects the VAUX falling edge. It is worth noting that as portrayed by Figure 10, VAUX is also representative of the MOSFET drain−source voltage (“VDS”). More specifically, when VAUX is below zero, VDS is minimal (below the input voltage VIN). That is why VZCD is used to enable the driver so that the MOSFET turns on when its drain−source voltage is low. Valley switching reduces the losses and interference. Rzcd2 1 Rzcd1 ZCD2 16 ZCD1 Vin AND1 VDMG1 Negative and positive clamp Negative and positive clamp + − 0.5 V S LZCD S QZCD R CLK1 (from phase management block) 200−ms delay S OFF (from Fault management VDMG2 block) + − 0.5 V Vzcd1 SET1 Qzcd1 Q PWM latch PH1 Q S R Q Qzcd2 CLK2 (from phase management block) Q L1 DRV1 14 M1 R output buffe r 1 In−rush reset signal (from PH1 PWM comparator) DT R Vzcd2 Vcc D1 D2 Vout Vin L2 SET2 PWM latch PH2 S R output buffe r 2 Vcc Q DRV2 11 M2 Cbulk Cbulk In−rush reset signal (from PH2 PWM comparator) Figure 9. Zero Current Detection At startup or after an inactive period (because of a protection that has tripped for instance), there is no energy in the ZCD winding and therefore no voltage signal to activate the ZCD comparator. This means that the driver will never turn on. To avoid this, an internal watchdog timer is integrated into the controller. If the driver remains low for more than 200 ms (typical), the timer sets the LZCD latch as the ZCD winding signal would do. Obviously, this 200 ms delay acts as a minimum off−time if there is no demagnetization winding voltage is detected. To prevent negative voltages on the ZCD pins (ZCD1 for phase 1 and ZCD2 for phase 2), these pins are internally clamped to about 0 V when the voltage applied by the corresponding ZCD winding is negative. Similarly, the ZCD pins are clamped to VZCD(high) (10 V typical), when the ZCD voltage rises too high. Because of these clamps, a resistor (RZCD1 and RZCD2 of Figure 9) is necessary to limit the current from the ZCD winding to the ZCD pin. The clamps are designed to respectively source and sink 5 mA. It is hence recommended to dimension RZCD1 and RZCD2 to limit the ZCD1 and ZCD2 pins current below 5 mA. www.onsemi.com 13 NCP1632 Figure 10. Zero Current Detection Timing Diagram (VAUX is the Voltage Provided by the ZCD Winding) Current Sense Figure 11, a current sense resistor (RCS ) is practically inserted in the return path to generate a negative voltage (VCS ) proportional to Iin . The NCP1632 is designed to monitor a negative voltage proportional to the input current, i.e., the current drawn by the two interleaved branches (Iin ). As portrayed by Ac Line Vin VAUX2 Iin VAUX1 EMI filter ICS C IN L1 DRV1 Iin−rush DRV2 DRV1 ROCP RCS M1 CBULK (QZCD1 and QZCD2 are from the ZCD block) QZCD2 QZCD1 Negative clamp M2 In−rush CS 9 D2 D1 DRV2 ICS ICS ICS L2 OCP IILIM1 Current Mirror VOUT Iin Figure 11. Current Sense Block The NCP1632 uses VCS to detect when Iin exceeds its maximum permissible level. To do so, as sketched by Figure 11, the circuit incorporates an operational amplifier that sources the current necessary to maintain the CS pin www.onsemi.com 14 NCP1632 voltage near zero. By inserting a resistor ROCP between the CS pin and RCS , we adjust the current that is sourced by the CS pin (ICS ) as follows: * ǒR CS @ I inǓ ) ǒROCP @ ICSǓ ^ 0 (eq. 13) over−stressed and finally damaged. That is why, the NCP1632 permanently monitors the input current and delays the MOSFET start of switching until (Iin) has vanished. This is the function of the ICS comparison to the Iin−rush threshold (14 mA typical). When ICS exceeds Iin−rush, the comparator output (“In−rush”) is high and prevents the PWM latches from setting (see block diagram). Hence, the two drivers (DRV1 and DRV2) cannot turn high and the MOSFETs stay off. This is to guarantee that the MOSFETs remain open as long as if the input current exceeds 10% of the maximum current limit. Again, this feature protects the MOSFETs from the possible excessive stress it could suffer from if it was allowed to turn on while a huge current flowed through the coil as it can be the case at start−up or during an over−load transient. The propagation delay (ICS < Iin−rush ) to (drive outputs high) is in the range of few ms. However when the circuit starts to operate, the NCP1632 disables this protection to avoid that the current produced by one phase and sensed by the circuit prevents the other branch from operating. Practically, some logic grounds the In−rush protection output when it detects the presence of “normal current cycles”. This logic simply consists of the OR combination of the Drive and demagnetization signals as sketched by Figure 11. Which leads to: ICS + RCS I R OCP in (eq. 14) In other words, the CS pin sources a current (ICS) which is proportional to the input current. Two functions use ICS: the over current protection and the in−rush current detection. Over−Current Protection (OCP) If ICS exceeds IILIM1 (210 mA typical), an over−current is detected and the on−time is decreased proportionally to the difference between the sensed current Iin and the 210 mA OCP threshold. The on−time reduction is done by injecting a current Ineg in the negative input of the “VTON processing circuit” OPAMP. (See Figure 6) Ineg + I CS * I ILIM1 2 (eq. 15) This current is injected each time the OCP signal is high. The maximum coil current is: Iin(max) + R OCP I RCS ILIM1 Over−Voltage Protection (eq. 16) While PFC circuits often use one single pin for both the Over−Voltage Protection (OVP) and the feed−back, the NCP1632 dedicates one specific pin for the under−voltage and over−voltage protections. The NCP1632 configuration allows the implementation of two separate feed−back networks (see Figure 13): 1. One for regulation applied to pin 2. 2. Another one for the OVP function (pin 8). In−rush Current Detection When the PFC stage is plugged to the mains, the bulk capacitor is abruptly charged to the line voltage. The charge current (named in−rush current) can be extremely huge particularly if no in−rush limiting circuitry is implemented. The power switches should not turn on during this severe transient. If not, they may be Vout (bulk voltage) Vout (bulk voltage) Rout1 FB 1 2 3 Rout3 Rout2 OVP FB 15 14 4 13 5 12 6 11 7 10 8 Rout1 16 Rovp1 Rout2 Rovp2 OVP 9 1 2 16 3 14 4 13 5 12 6 11 7 10 8 Figure 12. Configuration with One Feed−back Network for Both OVP and Regulation Figure 13. Configuration with Two Separate Feed−back Networks www.onsemi.com 15 15 9 NCP1632 Oscillator Section – Phase Management The double feed−back configuration (Figure 13) offers some up−graded safety level as it protects the PFC stage even if there is a failure of one of the two feed−back arrangements. In this case: The bulk regulation voltage (“Vout(nom)”) is: Vout(nom) + R out1 ) R out2 @ V ref R out2 The oscillator generates the clock signal that dictates the maximum switching frequency (fosc) of the interleaved PFC stage. In other words, each of the two interleaved branches cannot operate above half the oscillator frequency (fosc/2). The oscillator frequency (fosc) is adjusted by the capacitor applied to OSC pin (pin 4). Typically, a 220 pF capacitor approximately leads to a 260 kHz oscillator operating frequency, i.e., to a 130 kHz clamp frequency for each branch. As shown by Figure 14, a current source ICH (140 mA typically) charges the OSC pin capacitor until its voltage exceeds VOSC(high) (5 V typically). At that moment, the oscillator enters a discharge phase for which IDISCH (105 mA typ.) discharges the OSC pin capacitor. This sequence lasts until VOSC goes below the oscillator low threshold VOSCL and a new charging phase starts*. An internal signal (“SYNC” of Figure 19) is high during the discharge phase. A divider by two uses the SYNC information to manage the phases of the interleaved PFC: the first SYNC pulse sets “phase 1”, the second one, “phase 2”, the third one phase 1 again… etc. According to the selected phase, SYNC sets the relevant “Clock generator latch” that will generate the clock signal (“CLK1” for phase 1, “CLK2” for phase 2) when SYNC drops to zero. Actually, the drivers cannot turn on at this very moment if the inductor demagnetization is not complete. In this case, the clock signal is maintained high and the discharge time is prolonged although VOSC is below VOSCL , until when the core being reset, the drive pin turns high. The prolonged OSC discharge ensures a substantial 180−degree phase shift in CrM, out−of−phase operation being in essence, guaranteed in DCM. In the two conditions (CrM or DCM), the interleaved operation is stable and robust. (eq. 17) The OVP level (“Vout(ovp)”) is: Vout(ovp) + R ovp1 ) R ovp2 Rovp2 @ V ref (eq. 18) Where Vref is the internal reference voltage (2.5 V typically) Now, if wished, one single feed−back arrangement is possible as portrayed by Figure 12. The regulation and OVP blocks having the same reference voltage (Vref), the resistance ratio Rout2 over Rout3 adjusts the OVP threshold. More specifically, The bulk regulation voltage (“Vout(nom)”) is: Vout(nom) + R out1 ) R out2 ) R out3 @ V ref R out2 ) R out3 (eq. 19) The OVP level (“Vout(ovp)”) is: Vout(ovp) + R out1 ) R out2 ) R out3 @ V ref R out2 (eq. 20) The ratio OVP level over regulation level is: Vout(ovp) Vout(nom) +1) Rout3 Rout2 (eq. 21) For instance, (Vout(nom) = 105% ⋅ Vout(nom)) leads to: (Rout3 = 5% ⋅ Rout2). When the circuit detects that the output voltage exceeds the OVP level, it maintains the power switch open to stop the power delivery. *As detailed in the following sections, VOSCL is VOSC(low) − 4 V typically – by default to set the frequency clamp level used in heavy−load conditions. VOSCL is varied between 1 and 3 V in FFOLD mode (frequency foldback mode) in response the FFOLD pin voltage. www.onsemi.com 16 NCP1632 DRV1 SYNCbar R CLK1 Generation latch ICH SYNC 5V OSC S S OSC latch COSC R Q_ph1 Phase1 Q CLK1 Q SYNCbar DRV2 divider by two R CLK2 Generation latch Phase2 IDISCH S Q_ph1 CLK2 Q SYNCbar 4V VOSCL ICS (from CS block) FFOLD mode FFOLD 1V 3V 1 V and 3 V clamps Control of the oscillator low threshold (VOSCL) + 4V/3V HFC mode FFOLD mode − Figure 14. FFOLD Mode Management transitions between CrM and DCM within the input voltage sinusoid. In Figure 14 a) configuration, a single oscillator sets a frequency clamp. For instance, COSC = 220 pF forces 120 kHz to be the maximum frequency within each branch (the FFOLD mode reduces this level in light load conditions). Such a clamp value is likely to force DCM operation in part of the input voltage sinusoid. To be able to force full CrM operation over a large working range, we would need to reduce COSC to a very low value (if not, the clamp frequency can be lower than the switching one leading to DCM operation near the line zero crossing in particular). Still however, the oscillator must keep able to keep synchronized to the current cycle for proper out−of−phase control. This requires the oscillator swing to not to exceed its 1 V to 5 V range even in heavy load conditions when the switching frequency in each individual branch generally drops below 100 kHz. This is generally not possible with a single small capacitor on the OSC pin. If a capacitor COSC is applied to the OSC pin, the oscillator frequency is provided by: fosc ^ 60 @ 10 *6 C OSC ) (10 @ 10 *12) (eq. 22) And the switching frequency of each individual branch is clamped to the following fclamp : fclamp + f osc 30 @ 10 *6 ^ 2 C OSC ) (10 @ 10 *12) (eq. 23) Recommended Configuration As detailed above, the circuit automatically transitions between CrM and DCM depending on the current cycle duration being longer or shorter than the clamp frequency set by the oscillator. However, these transitions can lead to small discontinuities of the line current. To avoid them, the circuit should be operated in CrM without frequency−clamp interference when the line current is high and in deep DCM when it is below a programmed level. Deep DCM means that the switching frequency is low enough to ensure a significant dead−time and prevent www.onsemi.com 17 NCP1632 OSC pin OSC pin ROSC COSC (e.g., 82 pF) ROSC (e.g., 5.1 kW) COSC (e.g., 68 pF) (e.g., 5.1 kW) COSC (e.g., 220 pF) OSC pin CFF (e.g., 270 pF) a.) Basic configuration CFF (e.g., 330 pF) a.) Option 1 a.) Option 2 Figure 15. External Components Driving the OSC Pin • CFF sets the frequency in light load where the Instead, the schematic of either Figure 14 b) or Figure 14 c) is to be used where: • COSC (which value is much less than the second capacitance CFF) sets the high−frequency operation necessary for operating in CrM • ROSC limits the influence of the CFF capacitor as long as the oscillator swing remains below (ROSC.IOSC) where IOSC is the charge or discharge current depending on the sequence. The voltage across COSC being limited by ROSC (to about 1 V with 5.1 kW), the second much−higher−value capacitor (CFF) is engaged when heavy−load CrM operation imposes a larger oscillator swing. frequency foldback can force deep DCM operation (deep DCM means operation with a large dead−time to be far from the zone where the circuit can transition from CrM to DCM and vice versa). As previously mentioned, CFF also ensures that the oscillator voltage can stay above 1 V in deep CrM conditions. Finally, Figure 14 b) and c) configurations provide some kind of variable−capacitance oscillator. For instance, Option b) provides the following typical characteristics: 1 vramp 1 vramp 7.00 7.00 5V 5.00 5V 5.00 Tbranch ^33 . ms 1 3V plot1 vramp in volts 4V 3.00 3.00 Tbranch ^136 . ms 1.00 1.00 −1.00 −1.00 396u 398u 400u time in seconds 402u 404u 392u 300 kHz frequency clamp in HFC mode (VFFOLD > 4 V) 1 396u 400u time in seconds 404u 408u 73 kHz frequency clamp when entering FFOLD mode (VFFOLD = 3 V) vramp 7.00 5V 5.00 plot1 vramp in volts plot1 vramp in volts 1 3.00 1 1V 1.00 Tbranch ^36 ms − 1.00 360u 380u 400u time in seconds 420u 440u 28 kHz minimum frequency clamp (deepest DCM @ VFFOLD = 1 V) Figure 16. Clamp Frequency in Each Individual Branch with the Configuration of Figure 14 b) www.onsemi.com 18 NCP1632 Figure 17 illustrates the oscillator operation at a low FFOLD voltage. 3 1 IL1 VDS1 2 7 7.00 VDS2 IL2 6 5 5V 5.00 VOSC 8 3.00 9 1.00 VFFOLD forces the OSC valley VFFOLD is in the range of 1.1 V 4 −1.00 DCM rMflag (high in DCM) FFOLD / HFC Flag/C(high in FFOLD mode) 9.50m 9.54m 9.58m time in seconds 9.62m 9.66m Figure 17. Operation at a Low VFFOLD Value (VFFOLD = 1.1 V) HFC vs FFOLD Modes efficient than the discontinuous conduction mode in heavy load conditions. The transitions between the HFC and FFOLD modes and the frequency foldback characteristics are controlled by the FFOLD pin. The NCP1632 optimizes the PFC stage efficiency over the whole load range by entering the frequency foldback (FFOLD) mode when the line current magnitude is lower than a programmed level (see next section). More specifically, the circuit operates in: • Frequency foldback (FFOLD) mode when the line current magnitude is lower than a programmed level. In this mode, the circuit frequency clamp level is reduced as a function of the FFOLD pin voltage in order to reduce the frequency in medium− and light−load operation. The frequency can decrease down to about 30 kHz at very low power (depending on the OSC pin capacitor) • High frequency clamp (HFC) mode when the line current is high. In this mode, the clamp level of the switching frequency is set high so that the PFC stage mostly runs in critical conduction mode which is more Frequency Foldback (FFOLD) Management As detailed in the “current sense” section, the NCP1632 CS pin sources a current proportional to the input current (ICS of Figure 14). ICS is internally copied and sourced out of the FFOLD pin. This current is changed into a dc voltage by means of an external (R//C) network applied to the FFOLD pin. The obtained VFFOLD voltage is proportional to the line average current. As illustrated by Figure 18, the PFC stage enters the frequency foldback mode (FFOLD mode) when VFFOLD goes below 3.0 V, and recovers high−frequency clamp mode (HFC mode) when the FFOLD voltage exceeds 4 V. www.onsemi.com 19 NCP1632 V IN Ac line I IN EMI Filter VOUT PFC Stage C IN R SENSE IIN I CS Current Mirror R CS Low−pass filter to build a signal proportional to the average input current ICS I CS CS ICS 9 (ICS is proportional to the total input current) Negative clamp Oscillator low threshold control FFOLD 6 + 4V/3V HFC mode FFOLD mode − Figure 18. Frequency Foldback Control In HFC mode, the oscillator lower threshold (VOSCL ) is fixed and equal to VOSC(low) (4 V typically). In FFOLD mode, VOSCL is modulated by the FFOLD pin voltage as follows: • VOSCL = VFFOLD if VFFOLD is between 1 and 3 V • VOSCL = 1 V if VFFOLD is below 1 V • VOSCL = 3 V if VFFOLD exceeds 3 V As an example, the FFOLD external resistor can be selected so that (VFFOLD = 3 V) when the line current threshold is equal to 20% of the maximum current. In a 90 to 270 V rms application, above criterion leads the PFC stage to enter FFOLD mode at: • 20% load at 90 V rms • 60% load at 270 V rms The PFC stage will recover HFC mode (VFFOLD = 4 V) at: • 27% load at 90 V rms • 81% load at 270 V rms Above values assume a ripple−free VFFOLD voltage. The power thresholds for transition can be shift and the hysteresis reduced by the VFFOLD ripple. At the transition between the two modes, the oscillator low threshold is 3 V. In the example of Figure 15, this leads the branch clamp frequency to be 73 kHz when entering and just before leaving the FFOLD mode. Figure 19 shows a “natural” transition FFOLD to HFC mode. www.onsemi.com 20 NCP1632 VDS1 IL1 7 6 7.00 IL2 VDS2 5 2 VOSC 5V 5.00 4 3V 1 3.00 VFFOLD exceeds the 4 V threshold 1.00 DCM operation CrM operation −1.00 FFOLD / HFC Flag (high in FFOLD mode) DCM /CrMflag (high in DCM) 8.44m 8.48m 8.52m time in seconds 8.56m 8.60m 3 Figure 19. “Natural” Transition FFOLD to HFC Mode when VFFOLD exceeds 4 V HFC−mode Recovery of operation, the PFC stage may run in DCM and may not be able to provide the full power. To solve this, the NCP1632 forces HFC operation whenever the DRE comparator trips* and remains in HFC mode until the output voltage recovers its regulation level (that is when OVLFlag1 of Figure 22 turns low). At that moment, the conduction mode is normally selected as a function of the FFOLD pin voltage. See Figure 20. The FFOLD pin sources a current proportional to the input current. Placing a resistor and a capacitor between the FFOLD and GND pins, we obtain the voltage representative of the line current magnitude necessary to control the frequency foldback characteristics. The NCP1632 naturally leaves the FFOLD mode operation when the sensed input current being large enough, the FFOLD pin voltage (VFFOLD ) exceeds 4 V. Such a FFOLD to HFC transition is shown by Figure 19. *The dynamic response enhancer (DRE) comparator trips when the output voltage drops below 95.5% of its regulation level. DRE Skip Mode of Operation The circuit enters skip mode when the regulation block output (VCONTROL ) drops to its 0.6 V lower clamp level. At very light load and low line conditions, on−times can be short enough no to enter the low−consumption skip mode. To prevent such an inefficient continuous operation from occurring, the NCP1632 forces a minimum on−time which corresponds to 10% the maximum on−time. This does not mean that the PFC stage will enter skip mode when the load is less than 10% of the full load (or even much more considering the necessary headroom in the max on−time setting when selecting Rt ). Since, the NCP1632 reduces the switching frequency in light load (FFOLD mode), this minimum on−time corresponds to HFC mode S Q 5 Q 2 R6 100k R OVLFlag1 3 (high when VFB < VREF) Figure 20. Easing HFC−mode Recovery Now, the FFOLD pin is heavily filtered and this time constant may cause long VFFOLD settling phases. If while in very light−load conditions, the load abruptly rises, the FFOLD pin time constant may dramatically delay the HFC−mode recovery. As a result, during the FFOLD mode www.onsemi.com 21 NCP1632 much lower power levels, typically, in the range of 2% of the full power. Excessive die temperature detected by the thermal shutdown. ♦ Under−Voltage Protection (“UVP” high) ♦ Brown−out situation (“BONOK” high) ♦ Latching−off of the circuit by an external signal applied to pin 10 and exceeding 166 mV (“STDWN” of the block diagram turns high). ♦ Too low the current sourced by the Rt pin (“Rt(open)”) During the PFC stage start−up, that is, until the output voltage reaches its regulation level. The start−up phase is detected by the latch “LSTUP” of the block diagram. “LSTUP” is in high state when the circuit enters or recovers operation after one of above major faults and resets when the error amplifier stops charging its output capacitor, that is, when the output voltage of the PFC stage has reached its desired regulation level. At that moment, “STUP” falls down to indicate the end of the start−up phase. ♦ Low Clamp • Figure 21. VCONTROL Low Clamp The circuit consumption is minimized (below 1 mA) for a skipping period of time. PfcOK / REF5V Signal The NCP1632 can communicate with the downstream converter. The signal “pfcOK/REF5V” is high (5 V) when the PFC stage is in nominal operation and low otherwise. More specifically, “pfcOK/REF5V” is low: • Whenever a major fault condition is detected which turns off the circuit, i.e.: ♦ Incorrect feeding of the circuit (“UVLO” high). The UVLO signal turns high when VCC drops below VCC(OFF) (10 V typically) and remains high until VCC exceeds VCC(ON) (12 V typically). Finally, “pfcOK/REF5V” is high when the PFC output voltage is properly and safely regulated. “pfcOK/REF5V” should be used to allow operation of the downstream converter. Brown−Out Protection The brown−out pin is designed to receive a portion of the input voltage (VIN ). As VIN is a rectified sinusoid, a capacitor must be applied to the BO pin so that VBO is proportional to the average value of VIN . Feed−Forward Feed−forward circuitry Circuitry Current Mirror Rt I BO Vbo (BO pin voltage) Rt Vbo IBO 2 charges the timing I BO charges the timing capacitor for both phases of capacitor for both phases the interleaved PFC I BO V in Ac line EMI Filter R bo1 C in R cs Cbo R BO Vbo 1V BO−COMP VBO−COMP (high when VBO < 1 V) Tdelay S2 S bo2 L BO Vdd This PNP transistor maintains the BO pin below the BO threshold when the circuit is not fed enough to control the state of the BO block BO_NOK 980 mV Q 500−ms delay 50−ms delay R reset reset reset 7 μA Circuitry for brown−out Circuitry for detection brown−out detection S1 Figure 22. Brown−out Block www.onsemi.com 22 NCP1632 • The line upper BO threshold is: The BO pin voltage is used by two functions (refer to Figure 22): • Feedforward. Generation of an internal current proportional to the input voltage average value (IRt). VBO is buffered and made available on the Rt pin (pin 3). Hence, placing a resistor between pin 3 and ground, enables to adjust a current proportional to the average input voltage. This current (IRt) is internally copied and squared to form the charge current for the internal timing capacitor of each phase. Since this current is proportional to the square of the line magnitude, the conduction time is made inversely proportional to the line magnitude. This feed−forward feature makes the transfer function and the power delivery independent of the ac line level. Only the regulation output (VREGUL) controls the power amount. Note that if the IRt current is too low (below 7 mA typically), the controller goes in OFF mode to avoid damaging the MOSFETs with too long conduction time. In particular, this addresses the case when the Rt pin is open. • Brown−out protection. A 7 mA current source lowers the BO pin voltage when a brown−out condition is detected. This is for hysteresis purpose as required by this function. In traditional applications, the monitored voltage can be very different depending on the phase: ♦ Before operation, the PFC stage is off and the input bridge acts as a peak detector (refer to Figure 23). As a consequence, the input voltage is approximately flat and nearly equates the ac line v (t ) = (Vin,rms )boH = • ♦ π the ratio upper over lower threshold is: (Vin,rms )boH (Vin,rms )boL = ⎞ 2 ⎛ Rbo1 ⋅ Rbo 2 ⋅ IBO ⎟ ⋅ ⎢1 + π ⎢⎝ (Rbo1 + Rbo 2 )⋅VBO(th ) ⎟⎠ As in general Rbo1 is large compared to Rbo2, the precedent equation can simplify as follows: (Vin,rms )boH (Vin,rms )boL ≅ ⎛ 2 ⎢ Rbo 2 ⋅ IBO ⋅ 1+ π ⎢ VBO (th ) ⎝ ⎞ ⎟ ⎟ ⎠ Details of operation of the circuitry for brown−out detection In nominal operation, the voltage applied to pin 7 must be higher than the 1 V internal voltage reference. In this case, the output of the comparator BO−COMP (VBO−COMP) is low (see Figure 22). Conversely, if VBO goes below 1 V, VBO−COMP turns high and a 980 mV voltage source is connected to the BO pin to maintain the pin level near 1 V. The high state of VBO−COMP is used to detect a brown−out condition. However, the brown−out detection is not immediate. First, as soon as a high level occurs, this information is stored by a latch (LBO of Figure 22) and a 500 ms delay is activated. No BO fault can be detected until this time has elapsed. The main goal of the 500 ms lag is to help meet the hold−up requirements. In case of a short mains interruption, no fault is detected and hence, the “pfcOK” signal remains high and does not disable the downstream converter. In addition, the BO pin voltage being kept at 980 mV, there is almost no extra delay between the line recovery and the occurrence of the steady state VBO voltage, which otherwise would exist because of the large capacitor typically placed between pin7 and ground to filter the input voltage ripple. As a result, the NCP1632 effectively “blanks” any mains interruption that is shorter than 380 ms (minimum guaranteed value of the 500 ms timer). At the end of this 500 ms blanking delay, another timer is activated that sets a 50 ms window during which a fault can be detected. This is the role of the second 500 ms timer of Figure 22: • If the output of OPAMP is high at the end of the first delay (500 ms blanking time) and before the second 50 ms delay time is elapsed, a brown−out fault is detected (BO_NOK is high). 2 ⋅V ⋅ ⎞ ⎟⎟ ⎠ where VBO(th) is the BO comparator threshold (1 V typically) and IBO , the 7 mA current source. The line lower threshold is: Hence Rbo 2 Rbo1 + Rbo 2 2 2 ⋅ Vin,rms ⎛ R ⋅R ⋅I ⎢⎢VBO (th ) + bo1 bo 2 BO Rbo1 + Rbo 2 ⎝ bo 2 . After the PFC stage has started operation, the input voltage becomes a rectified sinusoid and the voltage applied to pin7 is: VBO = ⋅ (Vin,rms )boL = 2π 2 ⋅ RboR1 + Rbo2 ⋅VBO(th ) in,rms amplitude: in , where Vin,rms is the rms voltage of the line. Hence, the voltage applied to the BO pin (pin 7) is: VBO = 2 ⋅Vin,rms ⋅ Rbo1 + Rbo 2 Rbo 2 2 1 Rbo 2 Rbo1 + Rbo 2 , i.e., about 64% of the previous value. Therefore, the same line magnitude leads to a VBO voltage which is 36% lower when the PFC is working than when it is off. That is why a large hysteresis (in the range of 50% of the upper threshold) is required. Other applications may require a different hysteresis amount. That is why the hysteresis is made programmable and dependent on the internal 7 mA current source. More specifically, re−using the components of Figure 22: www.onsemi.com 23 NCP1632 • If the output of OPAMP remains low for the duration reset, the 980 mV clamp is removed (S2 is off) and IBO , the 7 mA current source, is enabled to lower the pin7 voltage for hysteresis purpose (as explained above). A pnp transistor ensures that the BO pin voltage remains below the 1 V threshold until VCC reaches VCC(on). This is to guarantee that the circuit starts operation in the right state, that is, “BONOK” high. When VCC exceeds VCC(on), the pnp transistor turns off and the circuit enables the 7 mA current source. The 7 mA current source remains on until the BO pin voltage exceeds the 1 V BO threshold. of the second delay, no fault is detected. In any case, the LBO latch and the two delays are reset at the end of the second delay. When the “BO_NOK” signal is high, the driver is disabled, the “Vcontrol” pin is grounded to recover operation with a soft−start when the fault has gone and the “pfcOK” voltage turns low to disable the downstream converter. In addition, the 500 ms and 50 ms timers are Figure 23. Typical Input Voltage of a PFC Stage Thermal Shutdown (TSD) Output Drive Section An internal thermal circuitry disables the circuit gate drive and then keeps the power switch off when the junction temperature exceeds 140°C typically. The output stage is then enabled once the temperature drops below about 80°C (60°C hysteresis). The temperature shutdown keeps active as long as the circuit is not reset, that is, as long as VCC keeps higher than VCCRESET. The reset action forces the TSD threshold to be the upper one (140°C). This ensures that any cold start−up will be done with the right TSD level. The circuit embeds two drivers to control the two interleaved branches. Each output stage contains a totem pole optimized to minimize the cross conduction current during high frequency operation. The gate drive is kept in a sinking mode whenever the Under−Voltage Lockout (UVLO) is active or more generally whenever the circuit is off. Its high current capability (−500 mA/+800 mA) allows it to effectively drive high gate charge power MOSFET. Under−Voltage Lockout Section The circuit features an accurate internal reference voltage (VREF). VREF is optimized to be ± 2.4% accurate over the temperature range (the typical value is 2.5 V). VREF is the voltage reference used for the regulation and the over−voltage protection. The circuit also incorporates a precise current reference (IREF) that allows the Over−Current Limitation to feature a ± 6% accuracy over the temperature range. Reference Section The NCP1632 incorporates an Under−Voltage Lockout block to prevent the circuit from operating when the power supply is not high enough to ensure a proper operation. An UVLO comparator monitors the pin 12 voltage (VCC) to allow the NCP1632 operation when VCC exceeds 12 V typically. The comparator incorporates some hysteresis (2.0 V typically) to prevent erratic operation as the VCC crosses the threshold. When VCC goes below the UVLO comparator lower threshold, the circuit turns off. The circuit off state consumption is very low: < 50 mA. This low consumption enables to use resistors to charge the VCC capacitor during the start−up without the penalty of a too high dissipation. Fault Mode The following block details the function. www.onsemi.com 24 NCP1632 Internal Thermal Shutdown Vref Vcc VDD Regul TSD Iref Stdwn UVP Vcc_OK BO_NOK UVLO 12 V / 10 V Rt(open) Q R 30−μs blanking time S IRt_Low (Ipin3 < 7 μA) OFF Fault management Figure 24. Fault Management Block • • • • • The circuit detects a fault if the Rt pin is open. Practically, if the pin sources less than 7 mA, the “IRt_Low” signal sets a latch that turns off the circuit if its output (Rt(open)) is high. A 30 ms blanking time avoids parasitic fault detections. The latch is reset when the circuit is in UVLO state (too low VCC levels for proper operation). When any of the following faults is detected: • brown−out (“BO_NOK”) Under−Voltage Protection (“UVP”) Latch−off condition (“Stdwn”) Die over−temperature (“TSD”) Too low the current sourced by the Rt pin (“Rt(open)”) “UVLO” (improper Vcc level for operation) The circuit turns off. It recovers operation when the fault disappears. www.onsemi.com 25 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16 CASE 751B−05 ISSUE K DATE 29 DEC 2006 SCALE 1:1 −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR COLLECTOR BASE EMITTER NO CONNECTION EMITTER BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE CATHODE ANODE NO CONNECTION CATHODE CATHODE NO CONNECTION ANODE CATHODE STYLE 3: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. COLLECTOR, DYE #1 BASE, #1 EMITTER, #1 COLLECTOR, #1 COLLECTOR, #2 BASE, #2 EMITTER, #2 COLLECTOR, #2 COLLECTOR, #3 BASE, #3 EMITTER, #3 COLLECTOR, #3 COLLECTOR, #4 BASE, #4 EMITTER, #4 COLLECTOR, #4 STYLE 4: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. STYLE 5: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. DRAIN, DYE #1 DRAIN, #1 DRAIN, #2 DRAIN, #2 DRAIN, #3 DRAIN, #3 DRAIN, #4 DRAIN, #4 GATE, #4 SOURCE, #4 GATE, #3 SOURCE, #3 GATE, #2 SOURCE, #2 GATE, #1 SOURCE, #1 STYLE 6: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE CATHODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE ANODE STYLE 7: PIN 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. SOURCE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE P‐CH SOURCE P‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) GATE N‐CH COMMON DRAIN (OUTPUT) COMMON DRAIN (OUTPUT) SOURCE N‐CH COLLECTOR, DYE #1 COLLECTOR, #1 COLLECTOR, #2 COLLECTOR, #2 COLLECTOR, #3 COLLECTOR, #3 COLLECTOR, #4 COLLECTOR, #4 BASE, #4 EMITTER, #4 BASE, #3 EMITTER, #3 BASE, #2 EMITTER, #2 BASE, #1 EMITTER, #1 SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98ASB42566B SOIC−16 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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