LDO Regulator, 300mA,
Low Dropout Voltage, Ultra
Low Noise, High PSRR with
Power Good
NCP164
The NCP164 is a 300 mA LDO, next generation of high PSRR,
ultra−low noise and low dropout regulators with Power Good open
collector output. Designed to meet the requirements of RF and
sensitive analog circuits, the NCP164 device provides ultra−low noise,
high PSRR and low quiescent current. The device also offer excellent
load/line transients. The NCP164 is designed to work with a 1 mF input
and a 1 mF output ceramic capacitor. It is available in industry standard
TSOP−5 and WDFN6 0.65P, 2 mm x 2 mm.
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MARKING
DIAGRAMS
5
TSOP−5
CASE 483
5
1
XXXAYWG
G
1
Features
•
•
•
•
•
•
•
•
•
•
•
•
Operating Input Voltage Range: 1.6 V to 5.5 V
Available in Fixed Voltage Option: 1.2 V to 5 V
Adjustable Version Reference Voltage: 1.1 V
±2% Accuracy Over Load and Temperature
Ultra Low Quiescent Current Typ. 30 mA
Standby Current: Typ. 0.1 mA
Very Low Dropout: 110 mV at 300 mA for 3.3 V Variant
Ultra High PSRR: Typ. 85 dB at 10 mA, f = 1 kHz
Ultra Low Noise: 9 mVRMS (Fixed Version)
Stable with a 1 mF Small Case Size Ceramic Capacitors
Available in – TSOP−5 3 mm x 1.5 mm x 1 mm CASE 483
♦ WDFN6 2 mm x 2 mm x 0.75 mm CASE 511BR
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
•
•
•
•
WDFN6 2x2, 0.65P
CASE 511BR
XXX
A
L
M
Y
W
G
XXMG
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Month Code
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTONS
OUT 1
ADJ/SNS 2
6 IN
GND
PG 3
Communication Systems
In−Vehicle Networking
Telematics, Infotainment and Clusters
General Purpose Automotive
5 GND
4 EN
WDFN6 2x2 mm
(Top View)
ORDERING INFORMATION
VIN
IN
See detailed ordering and shipping information on page 8 of
this data sheet.
OUT
NCP164
CIN
1 mF
Ceramic
EN
ON
GND
COUT
1 mF
Ceramic
PG
OFF
Figure 1. Typical Application Schematic
© Semiconductor Components Industries, LLC, 2020
January, 2021 − Rev. 1
1
Publication Order Number:
NCP164/D
NCP164
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
TSOP−5
Pin No.
WDFN6
Pin
Name
1
6
IN
5
1
OUT
3
4
EN
Chip enable: Applying VEN < 0.2 V disables the regulator, Pulling VEN > 0.7 V enables the LDO
4/−
3
PG
Power Good, open collector. Use 10 kW to 100 kW pull−up resistor connected to output or input
voltage
2
5
GND
Common ground connection
−/4
2
ADJ
Adjustable output feedback pin (for adjustable version only)
−
2
SNS
Sense feedback pin. Must be connected to OUT pin on PCB (for fixed versions only)
−
−
N/C
Not connected, pin can be tied to ground plane for better power dissipation
−
EPAD
EPAD
Description
Input voltage supply pin
Regulated output voltage. The output should be bypassed with small 1 mF ceramic capacitor
Expose pad should be tied to ground plane for better power dissipation
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VIN
−0.3 to 6
V
VOUT
−0.3 to VIN+0.3, max. 6
V
Chip Enable Input
VCE
−0.3 to 6
V
Power Good Voltage
VPG
−0.3 to 6
V
Power Good Current
IPG
30
mA
Output Short Circuit Duration
tSC
unlimited
s
Maximum Junction Temperature
TJ
150
°C
TSTG
−55 to 150
°C
ESD Capability, Human Body Model (Note 2)
ESDHBM
2000
V
ESD Capability, Charged Device Model (Note 2)
ESDCDM
1000
V
Input Voltage (Note 1)
Output Voltage
Storage Temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Charged Device Model tested per EIA/JESD22−C101, Field Induced Charge Model
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2
NCP164
Table 3. THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
RqJA
158
°C/W
Thermal Resistance, Junction−to−Case (top)
RqJC(top)
155
°C/W
Thermal Resistance, Junction−to−Case (bottom) (Note 4)
RqJC(bot)
102
°C/W
Thermal Resistance, Junction−to−Board
RqJB
197
°C/W
Characterization Parameter, Junction−to−Top
YJT
40
°C/W
YJB
82
°C/W
RqJA
51
°C/W
Thermal Resistance, Junction−to−Case (top)
RqJC(top)
142
°C/W
Thermal Resistance, Junction−to−Case (bottom) (Note 4)
RqJC(bot)
2.0
°C/W
THERMAL CHARACTERISTICS, TSOP−5 PACKAGE
Thermal Resistance, Junction−to−Ambient (Note 3)
Characterization Parameter, Junction−to−Board
THERMAL CHARACTERISTICS, WDFN6−2X2, 0.65 PITCH PACKAGE
Thermal Resistance, Junction−to−Ambient (Note 3)
Thermal Resistance, Junction−to−Board
RqJB
117
°C/W
Characterization Parameter, Junction−to−Top
YJT
1.9
°C/W
Characterization Parameter, Junction−to−Board
YJB
7.7
°C/W
3. The junction−to−ambient thermal resistance under natural convection is obtained in a simulation on a high−K board, following the JEDEC51.7
guidelines with assumptions as above, in an environment described in JESD51−2a.
4. The junction−to−case (bottom) thermal resistance is obtained by simulating a cold plate test on the IC exposed pad. Test description can
be found in the ANSI SEMI standard G30−88.
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3
NCP164
Table 4. ELECTRICAL CHARACTERISTICS (−40°C ≤ TJ ≤ 150°C; VIN = VOUT(NOM) + 0.5 V; IOUT = 1 mA, CIN = COUT
= 1 mF, VEN = VIN, unless otherwise noted. Typical values are at TJ = +25°C (Note 5))
Parameter
Test Conditions
Symbol
Min
VIN
1.6
5.5
V
VIN = VOUT(NOM) + 0.5 V to 5.0 V,
0.1 mA ≤ IOUT ≤ 300 mA
VOUT
−2
+2
%
VIN = 1.6 V to 5.0 V,
0.1 mA ≤ IOUT ≤ 300 mA
VADJ
1.078
1.122
V
VOUT(NOM) + 0.5 V ≤ VIN ≤ 5.0 V
LineReg
IOUT = 1 mA to 300 mA
LoadReg
2
VDO
170
295
VOUT(NOM) = 1.8 V
155
255
VOUT(NOM) = 2.5 V
125
200
VOUT(NOM) = 2.8 V
115
185
VOUT(NOM) = 3.0 V
113
177
VOUT(NOM) = 3.3 V
110
170
VOUT(NOM) = 4.5 V
95
135
Operating Input Voltage
Output Voltage Accuracy
Reference Voltage (Adjustable Ver.
ADJ pin connected to OUT)
Line Regulation
Load Regulation
Dropout Voltage (Note 6)
TSOP−5, WDFN6
IOUT = 300 mA
VOUT(NOM) = 1.5 V
Typ
1.1
Max
0.5
mV/V
mV
mV
mA
Output Current Limit
VOUT = 90% VOUT(NOM)
ICL
Short Circuit Current
VOUT = 0 V
ISC
Quiescent Current
IOUT = 0 mA
IQ
30
40
mA
Shutdown Current
VEN ≤ 0.4 V
IDIS
0.01
1.5
mA
EN Input Voltage “H”
VENH
EN Input Voltage “L”
VENL
VEN = 5.0 V
IEN
0.2
Output Voltage Raising
VPGUP
95
Output Voltage Falling
VPGDW
90
IPG = 5 mA, Open drain
VPGLO
EN Pin Threshold Voltage
EN Pull Down Current
Power Good Threshold Voltage
Power Good Output Voltage Low
Turn−On Time (Note 7)
Power Supply Rejection Ratio
(Note 7)
Output Voltage Noise (Fixed Ver.)
Thermal Shutdown Threshold
(Note 7)
Active output discharge resistance
COUT = 1 mF, From assertion of VEN
to VOUT = 95% VOUT(NOM)
VOUT(NOM) = 3.3 V,
IOUT = 10 mA
f = 100 Hz
f = 10 Hz to 100 kHz
PSRR
350
Unit
560
580
V
0.7
0.2
mA
%
0.3
V
120
ms
83
dB
f = 1 kHz
85
f = 10 kHz
80
f = 100 kHz
61
IOUT = 10 mA
0.6
VN
9
mVRMS
Temperature rising
TSDH
165
°C
Temperature hysteresis
THYST
15
°C
VEN < 0.2 V, Version A only
RDIS
260
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization.
Production tested at TJ = TA = 25°C.
6. Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible. Dropout
voltage is characterized when VOUT falls 3% below VOUT(NOM).
7. Guaranteed by design and characterization.
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4
NCP164
1.220
1.830
1.215
1.825
1.210
1.820
Output Voltage (V)
Output Voltage (V)
TYPICAL CHARACTERISTICS
1.205
1.200
1.195
VIN = 1.7 V
IOUT = 1 mA
COUT = 1 mF
1.190
1.185
1.180
−40 −20
0
20
40
60
80
1.815
1.810
1.805
1.795
1.790
−40 −20
100 120 140
40
60
80
100 120 140
Figure 2. Output Voltage vs. Temperature −
VOUT = 1.2 V
Figure 3. Output Voltage vs. Temperature −
VOUT = 1.8 V
Voltage Dropout (mV)
3.320
3.315
3.310
3.305
VIN = 3.8 V
IOUT = 1 mA
COUT = 1 mF
3.300
3.295
−40 −20
0
20
40
60
80
100 120 140
350
325
300
275
250
225
200
175
150
125
100
−40 −20
VOUT = 1.2 V
IOUT = 0.3 A
COUT = 1 mF
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
Figure 4. Output Voltage vs. Temperature −
VOUT = 3.3 V
Figure 5. Dropout Voltage vs. Temperature −
VOUT = 1.2 V
270
250
230
210
Voltage Dropout (mV)
Output Voltage (V)
20
Temperature (°C)
3.325
Voltage Dropout (mV)
0
Temperature (°C)
3.330
3.290
VIN = 2.3 V
IOUT = 1 mA
COUT = 1 mF
1.800
190
170
150
130
VOUT = 1.8 V
IOUT = 0.3 A
COUT = 1 mF
110
90
70
−40 −20
0
20
40
60
80
100 120 140
170
160
150
140
130
120
110
100
90
80
70
−40 −20
VOUT = 3.3 V
IOUT = 0.3 A
COUT = 1 mF
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
Figure 6. Dropout Voltage vs. Temperature −
VOUT = 1.8 V
Figure 7. Dropout Voltage vs. Temperature −
VOUT = 3.3 V
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5
NCP164
40
38
36
34
32
30
28
26
24
22
20
−40 −20
140
VOUT = 1.8 V
IOUT = 10 mA
COUT = 1 mF
135
Turn−on Time (ms)
Quiescent Current (mA)
TYPICAL CHARACTERISTICS (continued)
VOUT = nom.
IOUT = 0 mA
COUT = 1 mF
0
20
40
60
80
130
125
120
115
110
105
100
−40 −20
100 120 140
0
Temperature (°C)
570
0.60
Enable Thresholds (V)
Current Limit (mA)
0.65
560
550
540
VOUT = nom.
COUT = 1 mF
510
500
−40 −20
0
20
40
60
80
80
100 120 140
0.55
0.50
Output ON
0.45
0.40
0.35
Output OFF
0.30
0.25
−40 −20
100 120 140
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
Figure 10. Current Limit vs. Temperature
Figure 11. Enable Thresholds vs Temperature
300
96,0
290
95,0
VOUT raising to nominal
94,0
Active Discharge (W)
Power Good Thresholds (%)
60
Figure 9. Turn−on Time vs. Temperature
580
520
40
Temperature (°C)
Figure 8. Quiescent Current va Temperature
530
20
93,0
92,0
91,0
90,0
VOUT falling from nominal
89,0
88,0
−40 −20
0
20
40
60
80
280
270
260
250
240
EN = low
COUT = 1 mF
230
220
−40 −20
100 120 140
Temperature (°C)
0
20
40
60
80
100 120 140
Temperature (°C)
Figure 12. Power Good Threshold vs.
Temperature
Figure 13. Active Discharge Resistance vs.
Temperature
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6
NCP164
100
90
80
70
60
50
40
30
20
10
0
0.01
- IOUT = 10 mA
- IOUT = 100 mA
- IOUT = 200 mA
VIN = 3.2 V
VOUT = 2.8 V
TA = 25°C
COUT = 1 mF
0,1
1
10
100
1000
10000
Noise Spectral Density
(nV/sqrt(Hz))
PSRR (dB)
TYPICAL CHARACTERISTICS (continued)
- IOUT = 10 mA
- IOUT = 100 mA
- IOUT = 200 mA
1000
100
10
VIN = 3.3 V
VOUT = 2.8 V
TA = 25°C
COUT = 1 mF
1
0.01
10000
0.1
1
Frequency (kHz)
10
100
1000
10000
Frequency (kHz)
Figure 14. Power Supply Rejection Ration
for VOUT = 2.8 V, COUT = 1 mF
Figure 15. Output Voltage Noise Spectral Density
for VOUT = 2.8 V, COUT = 1 mF
APPLICATIONS INFORMATION
saturation voltage. External pull−up resistor can be
connected to any voltage up to 5.0 V (please see Absolute
Maximum Ratings table).
The NCP164 is the member of new family of high output
current and low dropout regulators which delivers low
quiescent and ground current consumption, good noise and
power supply ripple rejection ratio performance. The
NCP164 incorporates EN pin and power good output for
simple controlling by MCU or logic. Standard features
include current limiting, soft−start feature and thermal
protection.
Power Dissipation and Heat Sinking
The maximum power dissipation supported by the device
is dependent upon board design and layout. Mounting pad
configuration on the PCB, the board material, and the
ambient temperature affect the rate of junction temperature
rise for the part. For reliable operation junction temperature
should be limited to +125°C, however device is capable to
work up to junction temperature +150°C. The maximum
power dissipation the NCP164 can handle is given by:
Input Decoupling (CIN)
It is recommended to connect at least 1 mF ceramic X5R
or X7R capacitor between IN and GND pin of the device.
This capacitor will provide a low impedance path for any
unwanted AC signals or noise superimposed onto constant
input voltage. The good input capacitor will limit the
influence of input trace inductances and source resistance
during sudden load current changes. Higher capacitance and
lower ESR capacitors will improve the overall line transient
response.
P D(MAX) +
ƪTJ(MAX) * TAƫ
(eq. 1)
R qJA
The power dissipated by the NCP164 for given
application conditions can be calculated from the following
equations:
P D [ V IN(I GND(I OUT)) ) I OUT (V IN * V OUT)
Output Decoupling (COUT)
(eq. 2)
or
The NCP164 does not require a minimum Equivalent
Series Resistance (ESR) for the output capacitor. The device
is designed to be stable with standard ceramics capacitors
with values of 1 mF or greater. The X5R and X7R types have
the lowest capacitance variations over temperature thus they
are recommended.
V IN(MAX) [
P D(MAX) ) ǒV OUT
I OUT ) I GND
I OUTǓ
(eq. 3)
Hints
VIN and GND printed circuit board traces should be as
wide as possible. When the impedance of these traces is
high, there is a chance to pick up noise or cause the regulator
to malfunction. Place external components, especially the
output capacitor, as close as possible to the NCP164, and
make traces as short as possible.
Power Good Output Connection
The NCP164 include Power Good functionality for better
interfacing to MCU system. Power Good output is open
collector type, capable to sink up to 10 mA. Recommended
operating current is between 10 mA and 1 mA to obtain low
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7
NCP164
Adjustable Version
where VFIX is voltage of original fixed version (from
1.2 V up to 5 V) or adjustable version (1.1 V). Do not operate
the device at output voltage about 5.2 V, as device can be
damaged.
In order to avoid influence of current flowing into SNS pin
to output voltage accuracy (SNS current varies with voltage
option and temperature, typical value is 300 nA) it is
recommended to use values of R1 and R2 below 500 kW.
Not only adjustable version, but also any fixed version can
be used to create adjustable voltage, where original fixed
voltage becomes reference voltage for resistor divider and
feedback loop. Output voltage can be equal or higher than
original fixed option, while possible range is from 1.1 V up
to 5 V. Figure 16 shows how to add external resistors to
increase output voltage above fixed value.
Output voltage is then given by equation
V OUT + V FIX
(1 ) R1ńR2)
(eq. 4)
VIN
CIN
IN
NCP164
ADJ or FIX version
SNS
EN
GND
1 mF
Ceramic
VOUT
OUT
ON
R1
COUT
10 mF
Ceramic
R2
OFF
Figure 16. Adjustable Variant Application
Please note that output noise is amplified by VOUT / VFIX
ratio. For example, if original 1.2 V fixed variant is used to
create 3.6 V output voltage, output noise is increased 3.6 /
1.2 = 3 times and real value will be 3 × 9 mVrms = 27ĂmVrms.
For noise sensitive applications it is recommended to use as
high fixed variant as possible – for example in case above it
is better to use 3.3 V fixed variant to create 3.6 V output
voltage, as output noise will be amplified only 3.6 / 3.3 =
1.09 × (9.8 mVrms).
ORDERING INFORMATION
Device Part No.
Voltage Variant
Marking
Package Option
Package
NCP164ASN180T1G
1.8 V
AJ
N/A
TSOP5
(Pb−Free)
3000 / Tape & Reel
NCP164ASN280T1G
2.8 V
AK
N/A
TSOP5
(Pb−Free)
3000 / Tape & Reel
NCP164ASN330T1G
3.3 V
AL
N/A
TSOP5
(Pb−Free)
3000 / Tape & Reel
NCP164ASNADJT1G
ADJ
A6
N/A
TSOP5
(Pb−Free)
3000 / Tape & Reel
NCP164AMT120TAG
1.2 V
CA
Non−Wettable
WDFN6 2 x 2
(Pb−Free)
3000 / Tape & Reel
NCP164AMT180TAG
1.8 V
CJ
Non−Wettable
WDFN6 2 x 2
(Pb−Free)
3000 / Tape & Reel
NCP164AMT280TAG
2.8 V
CK
Non−Wettable
WDFN6 2 x 2
(Pb−Free)
3000 / Tape & Reel
NCP164AMT330TAG
3.3 V
CL
Non−Wettable
WDFN6 2 x 2
(Pb−Free)
3000 / Tape & Reel
NCP164AMTADJTAG
ADJ
C2
Non−Wettable
WDFN6 2 x 2
(Pb−Free)
3000 / Tape & Reel
Shipping †
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
NOTE 5
2X
DATE 12 AUG 2020
0.20 C A B
0.10 T
M
2X
0.20 T
5
B
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
C
SIDE VIEW
SEATING
PLANE
END VIEW
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.95
0.037
MILLIMETERS
MIN
MAX
2.85
3.15
1.35
1.65
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
1.9
0.074
5
5
XXXAYWG
G
1
1
Analog
2.4
0.094
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
1.0
0.039
XXX MG
G
Discrete/Logic
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN6 2x2, 0.65P
CASE 511BR
ISSUE C
DATE 01 DEC 2021
GENERIC
MARKING DIAGRAM*
1
XX M
XX = Specific Device Code
M = Date Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON55829E
WDFN6 2X2, 0.65P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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