DATA SHEET
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Power Factor Controller for
Compact and Robust,
Continuous Conduction
Mode Pre-Converters
8
1
SO−8
D SUFFIX
CASE 751
NCP1654
MARKING DIAGRAM
The NCP1654 is a controller for Continuous Conduction Mode
(CCM) Power Factor Correction step−up pre−converters. It controls
the power switch conduction time (PWM) in a fixed frequency mode
and in dependence on the instantaneous coil current.
Housed in a SO8 package, the circuit minimizes the number of
external components and drastically simplifies the PFC
implementation. It also integrates high safety protection features that
make the NCP1654 a driver for robust and compact PFC stages like an
effective input power runaway clamping circuitry.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
IEC61000−3−2 Compliant
Average Current Continuous Conduction Mode
Fast Transient Response
Very Few External Components
Very Low Startup Currents (< 75 mA)
Very Low Shutdown Currents (< 400 mA)
Low Operating Consumption
±1.5 A Totem Pole Gate Drive
Accurate Fully Integrated 65/133/200 kHz Oscillator
Latching PWM for cycle−by−cycle Duty−Cycle Control
Internally Trimmed Internal Reference
Undervoltage Lockout with Hysteresis
Soft−Start for Smoothly Startup Operation
Shutdown Function
Pin to Pin Compatible with Industry Standard
This is a Pb−Free Device
54Bxx
ALYW
G
1
xx
A
L
Y
W
G
= 65, 133 or 200
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
Ground 1
8 Driver
VM 2
7 VCC
CS 3
6 Feedback
Brown−Out 4
5 Vcontrol
(Top View)
ORDERING INFORMATION
Safety Features
•
•
•
•
•
•
•
8
Inrush Currents Detection
Overvoltage Protection
Undervoltage Detection for Open Loop Detection or Shutdown
Brown−Out Detection
Soft−Start
Accurate Overcurrent Limitation
Overpower Limitation
Device
Package
Shipping†
NCP1654BD65R2G
SO−8
(Pb−Free)
2500 /
Tape & Reel
NCP1654BD133R2G
SO−8
(Pb−Free)
2500 /
Tape & Reel
NCP1654BD200R2G
SO−8
(Pb−Free)
2500 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Typical Applications
• Flat TVs, PC Desktops
• AC Adapters
• White Goods, other Off−line SMPS
© Semiconductor Components Industries, LLC, 2016
August, 2021 − Rev. 7
1
Publication Order Number:
NCP1654/D
NCP1654
MAXIMUM RATINGS TABLE
Symbol
Pin
Rating
DRV
8
Output Drive Capability − Source
Output Drive Capability − Sink
VCC
7
Power Supply Voltage, VCC pin, continuous voltage
7
Transient Power Supply Voltage, duration < 10 ms, IVCC < 10 mA
Vin
2, 3, 4, 5, 6
Input Voltage
Power Dissipation and Thermal Characteristics
D suffix, Plastic Package, Case 751
Maximum Power Dissipation @ TA = 70°C
Thermal Resistance Junction−to−Air
PD(SO)
RqJA(SO)
TJ
Operating Junction Temperature Range
TJmax
Maximum Junction Temperature
TSmax
Storage Temperature Range
TLmax
Lead Temperature (Soldering, 10 s)
Value
Unit
−1.5
+1.5
A
−0.3, +20
V
+25
V
−0.3, +10
V
450
178
mW
°C/W
−40 to +125
°C
150
°C
−65 to +150
°C
300
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) 2000 V per JEDEC standard JESD22, Method A114E
Machine Model (MM) 200 V (except pin#7 which complies 150 V) per JEDEC standard JESD22, Method A115A.
2. This device contains Latch−up Protection and exceeds ±100 mA per JEDEC Standard JESD78.
TYPICAL ELECTRICAL CHARACTERISTICS TABLE (VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 3)
Rating
Symbol
Min
Typ
Max
Unit
GATE DRIVE SECTION
ROH
Source Resistance @ Isource = 100 mA
−
9.0
20
W
ROL
Sink Resistance @ Isink = −100 mA
−
6.6
18
W
Tr
Gate Drive Voltage Rise Time from 1.5 V to 13.5 V (CL = 2.2 nF)
−
60
−
ns
Tf
Gate Drive Voltage Fall Time from 13.5 V to 1.5 V (CL = 2.2 nF)
−
40
−
ns
2.425
2.5
2.575
V
−
±28
−
mA
REGULATION BLOCK
VREF
Voltage Reference
IEA
Error Amplifier Current Capability
GEA
Error Amplifier Gain
100
200
300
mS
Pin 6 Bias Current @ VFB = VREF
−500
−
500
nA
Pin5 Voltage
Maximum Control Voltage @ VFB = 2 V
Minimum Control Voltage @ VFB = 3 V
DVcontrol = Vcontrol(max) − Vcontrol(min)
−
−
2.7
3.6
0.6
3.0
−
−
3.3
VOUTL / VREF
Ratio (VOUT Low Detect Thresold / VREF)
94
95
96
%
HOUTL / VREF
Ratio (VOUT Low Detect Hysteresis / VREF)
−
0.5
−
%
190
228
260
mA
−
10
−
mV
185
200
215
mA
−
200
−
mVA
186
62
222
75
308
110
mA
−
0−97
−
%
IBpin6
Vcontrol
Vcontrol(max)
Vcontrol(min)
DVcontrol
IBOOST
Pin 5 Source Current when (VOUT Low Detect) is activated
V
CURRENT SENSE BLOCK
VS
IS(OCP)
Current Sense Pin Offset Voltage, (ICS = 100 mA)
Overcurrent Protection Threshold
POWER LIMITATION BLOCK
ICS x VBO
Overpower Limitation Threshold
ICS(OPL1)
ICS(OPL2)
Overpower Current Threshold (VBO = 0.9 V, VM = 3 V)
Overpower Current Threshold (VBO = 2.67 V, VM = 3 V)
PWM BLOCK
Dcycle
Duty Cycle Range
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NCP1654
TYPICAL ELECTRICAL CHARACTERISTICS TABLE (VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 3)
Symbol
Rating
Min
Typ
Max
58
120
180
65
133
200
72
146
220
Unit
OSCILLATOR / RAMP GENERATOR BLOCK
Switching Frequency
65 kHz
133 kHz
200 kHz
fsw
kHz
BROWN−OUT DETECTION BLOCK
VBOH
Brown−Out Voltage Threshold (rising)
1.22
1.30
1.38
V
VBOL
Brown−Out Voltage Threshold (falling)
0.65
0.7
0.75
V
IIB
Pin 4 Input Bias Current @ VBO = 1 V
−500
−
500
nA
−
1.9
−
mA
1.5
1.5
−
−
4.7
4.7
28.1
84.4
8.8
9.8
−
−
103
105
107
%
−
500
−
ns
CURRENT MODULATION BLOCK
IM1
IM2
Multiplier Output Current (Vcontrol = Vcontrol(max), VBO = 0.9 V, ICS = 25 mA)
Multiplier Output Current (Vcontrol = Vcontrol(max), VBO = 0.9 V, ICS = 75 mA)
(@ 0 125°C)
(@ −40 125°C)
Multiplier Output Current (Vcontrol = Vcontrol(min) + 0.2 V, VBO = 0.9 V, ICS = 25 mA
Multiplier Output Current (Vcontrol = Vcontrol(min) + 0.2 V, VBO = 0.9 V, ICS = 75 mA
IM3
IM4
OVERVOLTAGE PROTECTION
VOVP / VREF
Ratio (Overvoltage Threshold / VREF)
TOVP
Propagation Delay (VFB – 107% VREF) to Drive Low
UNDERVOLTAGE PROTECTION / SHUTDOWN
VUVP(on)/VREF
UVP Activate Threshold Ratio (TJ = 0°C to +105°C)
4
8
12
%
VUVP(off)/VREF
UVP Deactivate Threshold Ratio (TJ = 0°C to +105°C)
6
12
18
%
UVP Lockout Hysteresis
−
4
−
%
Propagation Delay (VFB < 8% VREF) to Drive Low
−
500
−
ns
VUVP(H)
TUVP
THERMAL SHUTDOWN
TSD
Thermal Shutdown Threshold
150
−
−
°C
HSD
Thermal Shutdown Hysteresis
−
30
−
°C
VCC UNDERVOLTAGE LOCKOUT SECTION
VCC(on)
Start−Up Threshold (Undervoltage Lockout Threshold, VCC rising)
9.6
10.5
11.4
V
VCC(off)
Disable Voltage after Turn−On (Undervoltage Lockout Threshold, VCC falling)
8.25
9.0
9.75
V
VCC(H)
Undervoltage Lockout Hysteresis
1.0
1.5
−
V
−
−
−
−
−
3.7
4.7
300
75
5.0
6.0
400
mA
mA
mA
mA
DEVICE CONSUMPTION
Power Supply Current:
Start−Up (@ VCC = 9.4 V)
Operating (@ VCC = 15 V, no load, no switching)
Operating (@ VCC = 15 V, no load, switching)
Shutdown Mode (@ VCC = 15 V and VFB = 0 V)
ISTUP
ICC1
ICC2
ISTDN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit
characterization has been performed.
NOTE:
IM +
I cs
4
V BO
ǒVcontrol * Vcontrol(min)Ǔ
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NCP1654
DETAILED PIN DESCRIPTIONS
Pin
Symbol
Name
Function
1
GND
Ground
2
Vin
Multiplier
Voltage
3
CS
Current Sense
Input
This pin sources a current ICS which is proportional to the inductor current IL. The sense
current ICS is for overcurrent protection (OCP), overpower limitation (OPL) and PFC duty
cycle modulation. When ICS goes above 200 mA, OCP is activated and the Drive Output is
disabled.
4
VBO
Brown−Out / In
Connect a resistor network among the rectified input voltage, BO pin, and ground. And
connect a capacitor between BO pin and ground. BO pin detects a voltage signal
proportional to the average input voltage.
When VBO goes below VBOL, the circuit that detects too low input voltage conditions
(brown−out), turns off the output driver and keeps it in low state until VBO exceeds VBOH.
This signal which is proportional to the RMS input voltage Vac is also for overpower limitation
(OPL) and PFC duty cycle modulation.
5
Vcontrol
Control Voltage
/ Soft−Start
The voltage of this pin Vcontrol directly controls the input impedance. This pin is connected to
external type−2 compensation components to limit the Vcontrol bandwidth typically below 20
Hz to achieve near unity power factor.
The device provides no output when Vcontrol < Vcontrol(min). When it starts operation, the
power increases slowly (soft−start).
6
VFB
Feed−Back /
Shutdown
7
VCC
Supply Voltage
8
DRV
Drive Output
−
This pin provides a voltage VM for the PFC duty cycle modulation. The input impedance of
the PFC circuits is proportional to the resistor RM externally connected to this pin. The device
operates in average current mode if an external capacitor CM is connected to the pin.
Otherwise, it operates in peak current mode.
This pin receives a feedback signal VFB that is proportional to the PFC circuits output
voltage. This information is used for both the output regulation, the overvoltage protection
(OVP), and output undervoltage protection (UVP) to protect the system from damage at
feedback abnormal situation.
When VFB goes above 105% VREF, OVP is activated and the Drive Output is disabled.
When VFB goes below 8% VREF, the device enters a low−consumption shutdown mode.
This pin is the positive supply of the IC. The circuit typically starts to operate when VCC
exceeds 10.5 V and turns off when VCC goes below 9 V. After start−up, the operating range
is 9 V up to 20 V.
The high current capability of the totem pole gate drive (±1.5 A) makes it suitable to
effectively drive high gate charge power MOSFET.
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NCP1654
IN
EMI
Filter
AC
Input
Iin Vin
+
L
IL
Cfilter
Cbulk
Output
Voltage
(VOUT)
+
−
IL
RSENSE
OVP
+
105% Vref
UVP
+
RboU
RfbU
BO
Vdd
OPL
8% Vref with 4% Vref
Hysteresis
Vdd
UVLO
200 mA
Soft
Start
Undervoltage
Lock−Out
S
FB
6
Reference
Block
Q
R
Vref
RfbL
95% Vref
+
Vref
+
Vcontrol
Off
Vout Low Detect
OTA
Iref
Vcc
7
+
Output
Buffer
Vcontrol(min)
CP
Vdd
±28 mA
5
RZ
Bias Block
UVP BO
CZ
8
1
GND
Thermal
Shutdown
BO
BO
+
CBO
VboH / VboL
VboH = 1.3 V, VboL = 0.7 V
Vdd
Ics
CS
Vdd
Current Mirror
Ics
RCS
+
Vramp
Ics
Ics > 200 mA
Vref/10%
Vref
Vm
+
Division
OPL
+ Iref
Vbo
C
1
Ics*Vbo > 200 mVA
3
PWM
LatcR
S
h
R
OL OVP
Vref
Vdd
Q
Fault
4
RboL
OL
S1
2
65/133/200 kHz
Oscillator
Im = (Ics*Vbo) / (4*(Vcontrol − Vcontrol(min))
OCP
Figure 1. Functional Block Diagram
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5
DRV
RM
CM
NCP1654
TYPICAL CHARACTERISTICS
2.60
8
2.55
ROH
6
VREF (V)
ROH & ROL, GATE DRIVE RESISTANCE (W)
10
4
ROL
−25
0
25
50
75
100
2.40
−50
125
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 2. Gate Drive Resistance vs.
Temperature
Figure 3. Reference Voltage vs. Temperature
32
−20
30
−22
28
−24
26
−26
24
−28
22
−30
20
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
IEA_sink (A)
IEA_source (A)
2.45
2
0
−50
2.50
−25
0
25
50
75
100
−32
−50
125
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 4. Source Current Capability of the
Error Amplifier vs. Temperature
Figure 5. Sink Current Capability of the Error
Amplifier vs. Temperature
300
150
100
IBpin6 (nA)
GEA (mS)
250
200
50
0
−50
150
−100
100
−50
−25
0
25
50
75
100
−150
−50
125
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Error Amplifier Gain vs. Temperature
Figure 7. Feedback Pin Current vs.
Temperature (@Vfb = VREF)
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125
NCP1654
4.0
3.3
3.9
3.2
3.8
DVCONTROL (V)
VCONTROL(max) (V)
TYPICAL CHARACTERISTICS
3.7
3.6
3.5
3.3
−50
−25
0
25
50
75
100
2.9
2.7
−50
125
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 8. Vcontrol Maximum Voltage vs.
Temperature
Figure 9. Vcontrol Maximum Swing (DVCONTROL)
vs. Temperature
95.1
260
95.0
250
94.9
240
94.8
IBoost (mA)
VoutL / VREF (%)
3.0
2.8
3.4
94.7
94.6
230
220
210
94.5
200
94.4
94.3
−50
−25
0
25
50
75
100
190
−50
125
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 10. Ratio (VOUT Low Detect Threshold /
VREF) vs. Temperature
Figure 11. Pin 5 Source Current when (VOUT
Low Detect) is Activated vs. Temperature
215
306
210
286
205
266
ICS(OPL1) (mA)
IS(OCP) (mA)
3.1
200
195
190
125
246
226
206
185
−50
−25
0
25
50
75
100
186
−50
125
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Over−Current Protection Threshold
vs. Temperature
Figure 13. Over−Power Current Threshold
(@VBO = 0.9 V & Vm = 3 V) vs. Temperature
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NCP1654
TYPICAL CHARACTERISTICS
100
MAXIMUM DUTY CYCLE (%)
110
ICS(OPL2) (mA)
100
90
80
70
−25
0
25
50
75
100
98
97
96
95
−50
125
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 14. Over−Power Current Threshold
(@VBO = 2.67 V & Vm = 3 V) vs. Temperature
Figure 15. Maximum Duty Cycle vs.
Temperature
140
70
138
68
136
fSW (kHz)
72
66
64
132
130
60
128
−25
0
25
50
75
100
126
−50
125
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 16. Switching Frequency vs.
Temperature (65 kHz Version)
Figure 17. Switching Frequency vs.
Temperature (133 kHz Version)
210
205
200
195
190
185
180
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 18. Switching Frequency vs.
Temperature (200 kHz Version)
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125
134
62
58
−50
−25
TJ, JUNCTION TEMPERATURE (°C)
fSW (kHz)
fSW (kHz)
60
−50
99
125
125
NCP1654
TYPICAL CHARACTERISTICS
0.75
1.40
VBOL (L)
VBOH (V)
1.35
1.30
0.70
1.25
1.20
−50
−25
0
25
50
75
100
0.65
−50
125
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 19. Brown−Out Voltage Threshold
(Rising) vs. Temperature
Figure 20. Brown−Out Voltage Threshold
(Falling) vs. Temperature
125
2.66
6.5
2.64
5.5
VOVP (V)
Im2 (mA)
0
TJ, JUNCTION TEMPERATURE (°C)
7.5
4.5
2.62
2.60
3.5
2.5
−50
−25
0
25
50
75
100
2.58
−50
125
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. Multiplier Output Current (Vcontrol =
VCONTROL(max), Vbo = 0.9 V, ICS = 75 mA) vs.
Temperature
Figure 22. Over Voltage Threshold vs.
Temperature
VUVP(on) / VREF and VUVP(off) / VREF (%)
107
106
VOVP / VREF (%)
−25
105
104
103
−50
−25
0
25
50
75
100
125
16
14
12
10
8
6
4
2
0
−50
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 24. UVP Activate and Deactivate
Threshold Ratio vs. Temperature
Figure 23. Ratio (Over Voltage Threshold /
VREF) vs. Temperature
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125
125
NCP1654
TYPICAL CHARACTERISTICS
9.7
11.4
11.2
9.5
9.3
10.8
VCC(off) (V)
VCC(on) (V)
11.0
10.6
10.4
10.2
8.9
8.7
10.0
8.5
9.8
9.6
−50
−25
0
25
50
75
100
8.3
−50
125
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 25. VCC Start−Up Threshold (VCC
Rising) vs. Temperature
Figure 26. VCC Disable Voltage after Turn−On
(VCC Falling) vs. Temperature
2.0
50
1.8
40
1.6
30
1.4
20
10
1.2
1.0
−50
−25
0
25
50
75
100
0
−50
125
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 27. VCC UVLO Hysteresis vs.
Temperature
Figure 28. Supply Current in Startup Mode vs.
Temperature
4
OPERATING CURRENT (mA)
400
350
ISTDN (mA)
−25
TJ, JUNCTION TEMPERATURE (°C)
ISTUP (mA)
VCC(H) (V)
9.1
300
250
200
−50
−25
0
25
50
75
100
3
2
ICC1, No Load, No Switching
1
0
−50
125
ICC2, No Load, Switching
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 29. Supply Current in Shutdown Mode
vs. Temperature
Figure 30. Operating Supply Current vs.
Temperature
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125
NCP1654
Detailed Operating Description
Introduction
The NCP1654 is a PFC driver designed to operate in fixed
frequency, continuous conduction mode. The fixed
frequency operation eases the compliance with EMI
standard and the limitation of the possible radiated noise that
may pollute surrounding systems. In addition, continuous
conduction operation reduces the application di/dt and their
resulting interference. More generally, the NCP1654 is an
ideal candidate in systems where cost−effectiveness,
reliability and high power factor are the key parameters. It
incorporates all the necessary features to build a compact
and rugged PFC stage:
• Compactness and Flexibility: housed in a SO8
package, the NCP1654 requires a minimum of external
components. In particular, the circuit scheme simplifies
the PFC stage design and eliminates the need for any
input voltage sensing. In addition, the circuit offers
some functions like the Brown−Out or the true power
limiting that enable the optimizations of the PFC
design,
• Low Consumption and Shutdown Capability: the
NCP1654 is optimized to exhibit consumption as small
as possible in all operation modes. The consumed
current is particularly reduced during the start−up phase
and in shutdown mode so that the PFC stage power
losses are extremely minimized when the circuit is
disabled. This feature helps meet the more stringent
stand−by low power specifications. Just ground the
Feed−back pin to force the NCP1654 in shutdown
mode,
• Safety Protections: the NCP1654 permanently monitors
the output voltage, the coil current and the die
temperature to protect the system from possible
over−stresses. Integrated protections (Overvoltage
protection, coil current limitation, thermal shutdown...)
make the PFC stage extremely robust and reliable:
− Maximum Current Limit: the circuit permanently
senses the coil current and immediately turns off the
power switch if it is higher than the set current limit.
The NCP1654 also prevents any turn on of the power
switch as long as the coil current is not below its
maximum permissible level. This feature protects the
MOSFET from possible excessive stress that could
result from the switching of a current higher than the
one the power switch is dimensioned for. In
particular, this scheme effectively protects the PFC
stage during the start−up phase when large in−rush
currents charge the output capacitor.
− Undervoltage Protection for Open Loop Protection or
Shut−down: the circuit detects when the feed−back
•
voltage goes below than about 8% of the regulation
level. In this case, the circuit turns off and its
consumption drops to a very low value. This feature
protects the PFC stage from starting operation in case
of low AC line conditions or in case of a failure in the
feed−back network (i.e. bad connection).
− Fast Transient Response: given the low bandwidth of
the regulation block, the output voltage of PFC stages
may exhibit excessive over or under−shoots because
of abrupt load or input voltage variations (e.g. at start
up). If the output voltage is too far from the
regulation level:
Overvoltage Protection: NCP1654 turns off the
power switch as soon as Vout exceeds the OVP
threshold (105% of the regulation level). Hence
a cost & size effective bulk capacitor of lower
voltage rating is suitable for this application,
Dynamic Response Enhancer: NCP1654
drastically speeds up the regulation loop by its
internal 200ĂmA enhanced current source when the
output voltage is below 95% of its regulation level.
− Brown−Out Detection: the circuit detects low AC line
conditions and disables the PFC stage in this case.
This protection mainly protects the power switch
from the excessive stress that could damage it in such
conditions,
− Over−Power Limitation: the NCP1654 computes the
maximum permissible current in dependence of the
average input voltage measured by the brown−out
block. It is the second OCP with a threshold that is
line dependent. When the circuit detects an excessive
power transfer, it resets the driver output
immediately,
− Thermal Shutdown: an internal thermal circuitry
disables the circuit gate drive and then keeps the
power switch off when the junction temperature
exceeds 150°C typically. The circuit resumes
operation once the temperature drops below about
120°C (30°C hysteresis),
− Soft Start: Vcontrol is pulled low brown−out detection
activates, or Undervoltage protection activates, and
no drive is provided.
At start up, the “200 mA enhanced current source” is
disabled. So there is only 28 mA to charge the
compensation components, and makes Vcontrol raise
gradually. This is to obtain a slow increasing duty
cycle and hence reduce the voltage and current stress
on the MOSFET. Hence it provides a soft−start
feature.
Output Stage Totem Pole: the NCP1654 incorporates
a ±1.5A gate driver to efficiently drive TO220 or
TO247 power MOSFETs.
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11
NCP1654
PRINCIPLE OF NCP1654 SCHEME
The input filter capacitor Cfilter and the front−ended EMI
filter absorbs the high−frequency component of inductor
current IL. It makes the input current Iin a low−frequency
signal only of the inductor current.
CCM PFC Boost
A CCM PFC boost converter is shown in Figure 31. The
input voltage is a rectified 50 ro 60 Hz sinusoidal signal. The
MOSFET is switching at a high frequency (typically
65/133/200 kHz in NCP1654) so that the inductor current IL
basically consists of high and low−frequency components.
Filter capacitor Cfilter is an essential and very small value
capacitor in order to eliminate the high−frequency
component of the inductor IL. This filter capacitor cannot be
too bulky because it can pollute the power factor by
distorting the rectified sinusoidal input voltage.
L
Iin
IL
I in + I L*50
where
Iin is the input AC current.
IL is the inductor current.
IL−50 supposes a 50 Hz operation. The suffix 50 means it
is with a 50 Hz bandwidth of the original IL.
From (Equation 1) and (Equation 2), the input impedance
Zin is formulated.
Vout
Vin
Z in +
Output
+
Voltage
Cbulk
Cfilter
V in
T * t 1 V out
+
I in
T
I L*50
(eq. 3)
where Zin is input impedance.
Power factor is corrected when the input impedance Zin in
(Equation 3) is constant or varies slowly in the 50 or 60 Hz
bandwidth.
RSENSE
Figure 31. CCM PFC Boost Converter
VM
PFC Methodology
Ich
The NCP1654 uses a proprietary PFC methodology
particularly designed for CCM operation. The PFC
methodology is described in this section.
IL
(eq. 2)
+
0
Cramp
1
Iin
Vref
+
PFC Modulation
R Q
Vramp
S
Clock
Vref
t1
t2
Vramp
Time
VM
VM without
Filtering
T
Clock
Figure 32. Inductor Current in CCM
Latch Set
As shown in Figure 32, the inductor current IL in a
switching period T includes a charging phase for duration t1
and a discharging phase for duration t2. The voltage
conversion ratio is obtained in (Equation 1).
Latch Reset
Output
t ) t2
V out
+ 1
+ T
t2
V in
T * t1
V in +
T * t1
V out
T
Inductor
Current
(eq. 1)
Figure 33. PFC Duty Modulation and Timing Diagram
where
Vout is the output voltage of PFC stage,
Vin is the rectified input voltage,
T is the switching period,
t1 is the MOSFET on time, and
t2 is the MOSFET off time.
The PFC modulation and timing diagram is shown in
Figure 33. The MOSFET on time t1 is generated by the
intersection of reference voltage VREF and ramp voltage
Vramp. A relationship in (Equation 4) is obtained.
V ramp + V m )
where
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12
I cht 1
+ V REF
C ramp
(eq. 4)
NCP1654
Vramp is the internal ramp voltage, the positive input of the
PFC modulation comparator,
Vm is the multiplier voltage appearing on Vm pin,
Ich is the internal charging current,
Cramp is the internal ramp capacitor, and
VREF is the internal reference voltage, the negative input of
the PFC modulation comparator.
Ich, Cramp, and VREF also act as the ramp signal of
switching frequency. Hence the charging current Ich is
specially designed as in (Equation 5). The multiplier voltage
Vm is therefore expressed in terms of t1 in (Equation 6).
I ch +
C rampV REF
T
Vm +
C rampV REF
T * t1
V m + V REF *
+ V REF
T
T
C ramp
2
CM
Figure 35. External Connection on the Multiplier
Voltage Pin
The multiplier voltage Vm is generated according to
(Equation 8).
Vm +
R MI csV bo
4(V control * V CONTROL(min))
(eq. 8)
Where,
RM is the external multiplier resistor connected to Vm pin,
which is constant.
Vbo is the input voltage signal appearing on the BO pin,
which is proportional to the rms input voltage,
Ics is the sense current proportional to the inductor current
IL as described in (Equation 11).
Vcontrol is the control voltage signal, the output voltage of
Operational Trans−conductance Amplifier (OTA), as
described in (Equation 12).
RM directly limits the maximum input power capability
and hence its value affects the NCP1654 to operate in either
“follower boost mode” or “constant output voltage mode”.
(eq. 6)
V m V out
V REF I L*50
Im
PFC Duty
Modulation
From (Equation 3) and (Equation 6), the input impedance
Zin is re−formulated in (Equation 7).
Z in +
Vm
RM
(eq. 5)
t1
R MI csV bo
4(V control * V CONTROL(min))
(eq. 7)
Because VREF and Vout are roughly constant versus time,
the multiplier voltage Vm is designed to be proportional to
the IL−50 in order to have a constant Zin for PFC purpose. It
is illustrated in Figure 34.
Vin
Vin
+
Iin
Time
IL
RboU
Time
VM
Vbo
4
RboL
Time
CBO
+
BO
VboH / VboL
VboH = 1.3 V, VboL = 0.7 V
Figure 34. Multiplier Voltage Timing Diagram
It can be seen in the timing diagram in Figure 33 that Vm
originally consists of a switching frequency ripple coming
from the inductor current IL. The duty ratio can be
inaccurately generated due to this ripple. This modulation is
the so−called “peak current mode”. Hence, an external
capacitor CM connected to the multiplier voltage Vm pin is
essential to bypass the high−frequency component of Vm.
The modulation becomes the so−called “average current
mode” with a better accuracy for PFC.
Figure 36. External Connection on the Brown Out Pin
Refer to Figure 36,
2 Ǹ2
V bo + K BO(V in) + K BO @ p V ac
K BO +
R boL
R boU ) R boL
(eq. 9)
(eq. 10)
where
Vbo is the voltage on BO pin.
KBO is the decay ratio of Vin to Vbo.
is the average voltage signal of Vin, the voltage
appearing on Cfilter.
Vac is the RMS input voltage.
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13
NCP1654
RboL is low side resistor of the dividing resistors between Vin
and BO pin.
RboU is upper side resistor of the dividing resistors between
Vin and BO pin.
Refer to Figure 37, sense current Ics is proportional to the
inductor current IL as described in (Equation 11). IL consists
of the high−frequency component (that depends on di/dt or
inductor L) and low−frequency component (that is IL−50).
IL
ICS
I cs +
CS
+
RCS
VCS
−
RSENSE
R SENSE
IL
R CS
(eq. 11)
where
RSENSE is the sense resistor to sense IL.
RCS is the offset resistor between CS pin and RSENSE.
+
NCP1654
Gnd
IL
Figure 37. Current Sensing
Vin
Vout
+
RfbU
Vfb
6
RfbL
Vcontrol
CP
+
VREF
±20 mA
+
OTA
VCONTROL(min)
5
RZ
CZ
To Vm Pin
Figure 38. Vcontrol Low−Pass Filtering
Refer to Figure 38, the Operational Trans−conductance
Amplifier (OTA) senses Vout via the feedback resistor
dividers, RfbU and RfbL. The OTA constructs a control
voltage, Vcontrol, depending on the output power and hence
Vout. The operating range of Vcontrol is from VCONTROL(min)
to VCONTROL(max). The signal used for PFC duty
modulation is after decreasing a offset voltage,
VCONTROL(min), i.e. Vcontrol−VCONTROL(min).
This control current Icontrol is a roughly constant current
that comes from the PFC output voltage Vout that is a slowly
varying signal. The bandwidth of Icontrol can be additionally
limited by inserting the external type−2 compensation
components (that are RZ, CZ, and CP as shown in Figure 38).
It is recommended to limit fcontrol, that is the bandwidth of
Vcontrol (or Icontrol), below 20 Hz typically to achieve power
factor correction purpose.
The transformer of Vout to Vcontrol is as described in
(Equation 12) if CZ is >> CP. GEA is the error amplifier gain.
V control
R @ G EAR Z
1 ) sR ZC Z
+ fbL
@
V out
R fbL ) R fbU sR ZC Z(1 ) sR ZC P)
From (Equation 7) − (Equation 11), the input impedance
Zin is re−formulated in (Equation 13).
Z in +
Ǹ2 R R
(eq. 13)
M SENSEV outV acK BOI L
2pR CS @ (V control * V CONTROL(min)) @ V REFI L*50
When IL is equal to IL−50, (Equation 13) is re−formulated
in (Equation 14)
Z in +
Ǹ2 R R
M SENSEV outV acK BO
2pR CS @ (V control * V CONTROL(min)) @ V REF
(eq. 14)
The multiplier capacitor CM is the one to filter the
high−frequency component of the multiplier voltage Vm.
The high−frequency component is basically coming from
the inductor current IL. On the other hand, the filter capacitor
Cfilter similarly removes the high−frequency component of
inductor current IL. If the capacitors CM and Cfilter match
with each other in terms of filtering capability, IL becomes
IL−50. Input impedance Zin is roughly constant over the
bandwidth of 50 or 60 Hz and power factor is corrected.
(eq. 12)
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14
NCP1654
Input and output power (Pin and Pout) are derived in (Equation 15) when the circuit efficiency η is obtained or assumed. The
variable Vac stands for the rms input voltage.
P in +
T
2pR CS @ (V control * V CONTROL(min)) @ V REF @ V ac
V ac 2
+
Ǹ2 R R
Z in
V K
(V control * V CONTROL(min))V ac
V out
P out + h P in + h
T
(eq. 15)
M SENSE out BO
2pR CS @ (V control * V CONTROL(min)) @ V REF @ V ac
Ǹ2 R R
M SENSEV outK BO
(eq. 16)
(V control * V CONTROL(min))V ac
V out
Follower Boost
VCONTROL(max). Re−formulate (Equation 16) to become
(Equation 17) and (Equation 18) by replace Vcontrol by
VCONTROL(max). If Vcontrol is constant based on
(Equation 15), for a constant load or power demand the
output voltage Vout of the converter is proportional to the
rms input voltage Vac. It means the output voltage Vout
becomes lower when the rms input voltage Vac becomes
lower. On the other hand, the output voltage Vout becomes
lower when the load or power demand becomes higher.
The “Follower Boost” is an operation mode where the
pre−converter output voltage stabilizes at a level that varies
linearly versus the ac line amplitude. This technique aims at
reducing the gap between the output and input voltages to
optimize the boost efficiency and minimize the cost of the
PFC stage (refer to MC33260 data sheet for more details at
http://www.onsemi.com).
The NCP1654 operates in follower boost mode when
Vcontrol is constant, i.e. Vcontrol raises to its maximum value
P out + h
+h
2pR CS @ (V CONTROL(max) * V CONTROL(min)) @ V REF @ V ac
Ǹ2 R R
M SENSEV outK BO
(eq. 17)
2pR CS @ DV CONTROL @ V REF @ V ac
Ǹ2 R R
V K
M SENSE out BO
V out + h
2pR CS @ DV CONTROL @ V REF V ac
@
Ǹ2 R R
P out
K
(eq. 18)
M SENSE BO
the output voltage Vout will always be higher than the input
voltage Vin even though Vout is reduced in follower boost
operation. As a result, the on time t1 is reduced. Reduction
of on time makes the loss of the inductor and power
MOSFET smaller. Hence, it allows cheaper cost in the
inductor and power MOSFET or allows the circuit
components to operate at a lower stress condition in most of
the time.
where
VCONTROL(max) is the maximum control voltage.
DVCONTROL is the gap between VCONTROL(max) and
VCONTROL(min).
It is illustrated in Figure 39.
Vout (Traditional Boost)
Reference Section
Vout (Follower Boost)
The internal reference voltage (VREF) is trimmed to be
±2% accurate over the temperature range (the typical value
is 2.5 V). VREF is the reference used for the regulation. VREF
also serves to build the thresholds of the fast transient
response, Overvoltage (OVP), brown out (BO), and
Undervoltage protections (UVP).
Vin
Time
Pout
Time
Output Feedback
The output voltage Vout of the PFC circuits is sensed at Vfb
pin via the resistor divider (RfbL and RfbU) as shown in
Figure 38. Vout is regulated as described in (Equation 19).
Figure 39. Follower Boost Characteristics
Follower Boost Benefits
The follower boost circuit offers and opportunity to
reduce the output voltage Vout whenever the rms input
voltage Vac is lower or the power demand Pout is higher.
Because of the step−up characteristics of boost converter,
V out + V REF
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15
R fbU ) R fbL
R fbL
(eq. 19)
NCP1654
Fast Transient Response
The feedback signal Vfb represents the output voltage Vout
and will be used in the output voltage regulation,
Overvoltage protection (OVP), fast transient response, and
Undervoltage protection (UVP)
Given the low bandwidth of the regulation block, the
output voltage of PFC stages may exhibit excessive over or
under−shoots because of abrupt load or input voltage
variations (such as start−up duration). As shown in
Figure 40, if the output voltage is out of regulation,
NCP1654 has 2 functions to maintain the output voltage
regulation.
Output Voltage Regulation
NCP1654 uses a high gain Operational Trans−
conductance Amplifier (OTA) as error amplifier. Refer to
Figure 38, the output of OTA Vcontrol operating range is
from VCONTROL(min) to VCONTROL(max).
Vout
+
Vdd
OVP
RfbU
Vfb
6
CFB
RfbL
Vcontrol
105%
VREF
95%
VREF
VREF
200 mA
+
+
+
Vout Low Detect
±20 mA
OTA
5
Figure 40. OVP and Fast Transient Response
• Overvoltage Protection: When Vfb is higher than 105%
VCONTROL PIN CURRENT (mA)
•
below 95% of its regulation level. Under normal
condition, the maximum sink and source of output
current capability of OTA is around 28 mA. Thanks to
the “Vout low detect” block, when the Vfb is below 95%
VREF, an extra 200 mA current source will raise Vcontrol
rapidly. Hence prevent the PFC output from dropping
too low and improve the transient response
performance. The relationship between current flowing
in/out Vcontrol pin and Vfb is as shown in Figure 41.
It is recommended to add a typical 100 pF capacitor CFB
decoupling capacitor next to feedback pin to prevent from
noise impact.
of VREF (i.e. Vout > 105% of nominal output voltage),
the Driver output of the device goes low for protection.
The circuit automatically resumes operation when Vfb
becomes lower than 105% of VREF. If the nominal Vout
is set at 390 V, then the maximum output voltage is
105% of 390 V = 410 V. Hence a cost & size effective
bulk capacitor of lower voltage rating is suitable for
this application,
Dynamic response enhancer: NCP1654 drastically
speeds up the regulation loop by its internal 200 mA
enhanced current source when the output voltage is
50
200 mA raises
Vcontrol rapidly
when Vfb is below
95% VREF
0
−50
−100
No DRV when
Vfb is above
105% VREF
−150
−200
−250
2
2.2
2.4
2.6
2.8
3
Vfb
Figure 41. Vfb vs. Current Flowing in/out from Vcontrol Pin
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16
NCP1654
Soft Start
The block diagram and timing diagram of soft start
function are as shown in Figure 42 and Figure 43. The device
provides no output (or no duty ratio) when the Vcontrol is
lower than VCONTROL(min). Vcontrol is pulled low when:
• Brown−out, or
• Undervoltage Protection
When the IC recovers from one of the following
conditions; Undervoltage Lockout, Brown−out or
Undervoltage Protection, the 200 mA current source block
keeps off. Hence only the Operating Trans−conductance
Amplifier (OTA) raises the Vcontrol. And Vcontrol rises
slowly. This is to obtain a slow increasing duty cycle and
hence reduce the voltage and current stress on the MOSFET.
A soft−start operation is obtained.
BO
Off
Vdd
UVLO
Bias
S
Q
R
Q
Vfb
6
Vcontrol
5
95%
VREF
VREF
+
+
Vdd
200 mA
Vout Low Detect
±20 mA
OTA
BO
Figure 42. Soft Start Block Diagram
UVLO, BO, or UVP
UVP
Period I
Period II
Vdd
Vdd Rising
Vfb
95% VREF
Vout Low Detect
Set
Reset
Q
Figure 43. Soft Start Timing Diagram
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17
UVLO
NCP1654
Undervoltage Protection (UVP) for Open Loop
Protection or Shutdown
Over−Current Protection (OCP)
Over−Current Protection is reached when Ics is larger than
IS(OCP) (200 mA typical). The offset voltage of the CS pin is
typical 10 mV and it is neglected in the calculation. Hence,
the maximum OCP inductor current threshold IL(OCP) is
obtained in (Equation 20).
ISTDN
Shutdown
Operating
I L(OCP) +
ICC2
12% VREF
Figure 44. Undervoltage Protection
+
R CS
@ 200 mA (eq. 20)
R SENSE
Input Voltage Sense
As shown in Figure 44, when Vfb is less than 8% of VREF,
the device is shut down and consumes less than 400 mA. The
device automatically starts operation when the output
voltage goes above 12% of VREF. In normal situation of
boost converter configuration, the output voltage Vout is
always greater than the input voltage Vin and the feedback
signal Vfb is always greater than 8% and 12% of VREF to
enable NCP1654 to operate.
This Undervoltage Protection function has 2 purposes.
• Open Loop Protection − Protect the power stage from
damage at feedback loop abnormal, such as Vfb is
shorted to ground or the feedback resistor RfbU is open.
• Shutdown mode − Disables the PFC stage and forces a
low consumption mode. This feature helps to meet
stringent stand−by specifications. Power Factor being
not necessary in stand−by, the PFC stage is generally
inhibited to save the pre−converter losses. To further
improve the stand−by performance, the PFC controller
should consume minimum current in this mode.
The device senses the rms input voltage Vac by the sensing
scheme in Figure 45. Vbo senses the average rectified input
voltage Vin via the resistor divider. An external capacitor
CBO is to maintain the Vbo the average value of Vin. Vbo is
used for Brown−Out Protection, PFC duty modulation and
over−power limitation (OPL).
Brown−Out Protection
The device uses the Vbo signal to protect the PFC stage
from operating as the input voltage is lower than expected.
Re−formulate (Equation 9) to get (Equation 21). Refer to
Figure 45, Vin is different before and after the device
operating.
• Before the device operates, Vin is equal to the peak
value of rms input voltage, Vac. Hence Vbo is as
described in (Equation 21).
V bo +
R boL
R boL
Ǹ2 V (eq. 21)
(V ) +
ac
R boL ) R boU in
R boL ) R boU
• After device operates, Vin is the rectified sinusoidal
Current Sense
input voltage. Thanks to CBO, Vbo is the average of
rectified input voltage. Hence Vbo decays to 2/p of the
peak value of rms input voltage Vac as described in
(Equation 22).
The device senses the inductor current IL by the current
sense scheme in Figure 37. The device maintains the voltage
at CS pin to be zero voltage (i.e., Vcs ≈ 0 V) so that
(Equation 11),
I cs +
R SENSE
When over−current protection threshold is reached, the
Drive Output of the device goes low. The device
automatically resumes operation when the inductor current
goes below the threshold.
Vfb
8% VREF
R CSI S(OCP)
R SENSE
IL ,
R CS
V bo +
can be formulated.
This scheme has the advantage of the minimum number
of components for current sensing. The sense current Ics
represents the inductor current IL and will be used in the PFC
duty modulation to generate the multiplier voltage Vm,
Over−Power Limitation (OPL), and Over−Current
Protection. (Equation 11) would insist in the fact that it
provides the flexibility in the RSENSE choice and that it
allows to detect in−rush currents.
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18
R boL
2 Ǹ2
V ac
R boL ) R boU p
(eq. 22)
NCP1654
Before Device Operates
Vac
Vin
+
IN
After Device Operates
+
−
RboU
Vbo
4
CBO
RboL
+
BO
VboH / VboL
VboH = 1.3 V, VboL = 0.7 V
Figure 45. Brown−Out Protection
Overpower Limitation (OPL)
Hence a larger hysteresis of the brown out comparator is
needed, which is 0.7 V typical in this device. When Vbo goes
below than VBOL (0.7 V typical), the device turns off the
Drive output and keeps it off till Vbo exceeds VBOH (1.3 V
typical). When the device awakes after an off−state
(Undervoltage lockout or shutdown), the default threshold
is VBOH.
This is a second OCP with a threshold that is line
dependent. Sense current Ics represents the inductor current
IL and hence represents the input current approximately.
Input voltage signal Vbo represents the rms input voltage.
The product (Ics ⋅ Vbo) represents an approximated input
power (IL ⋅ Vac). It is illustrated in Figure 46.
Vin
+
RSENSE
RCS
IL
I CS + I L
CS
ICS
R SENSE
R CS
OPL
Current Mirror
3
4
>200 mVA?
Vbo
Figure 46. Over−Power Limitation
When the product (Ics ⋅ Vbo) is greater than a permissible
level 200 mVA, the device turns off the drive output so that
the input power is limited. The OPL is automatically
deactivated when the product (Ics ⋅ Vbo) is lower than the
200 mVA level. This 200 mVA level corresponds to the
approximated input power (IL ⋅ Vac) to be smaller than the
particular expression in (Equation 23).
I csV bo t 200 mVA
ǒ
Ǔǒ
R
I L SENSE @
R CS
I L @ V ac t
2 Ǹ2 K BO
@ V ac
p
Ǔ
Bias the Controller
It is recommended to add a typical 1 nF to 100 nF
decoupling capacitor next to the Vcc pin for proper
operation. When the NCP1654 operates in follower boost
mode, the PFC output voltage is not always regulated at a
particular level under all application range of input voltage
and load power. It is not recommended to make a
low−voltage bias supply voltage by adding an auxiliary
winding on the PFC boost inductor. Alternatively, it is
recommended to get the Vcc biasing supply from the
2nd−stage power conversion stage.
(eq. 23)
t 200 mVA
R CS @ p
@ 50 Ǹ2 mVA
R SENSE @ K BO
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19
NCP1654
Vcc Undervoltage LockOut (UVLO)
The device incorporates an Undervoltage Lockout block
to prevent the circuit from operating when Vcc is too low in
order to ensure a proper operation. An UVLO comparator
monitors Vcc pin voltage to allow the NCP1654 to operate
when Vcc exceeds 10.5 V typically. The comparator
incorporates some hysteresis (1.5 V) to prevent erratic
operation as the Vcc crosses the threshold. When Vcc goes
below the UVLO comparator lower threshold (9 V
typically), the circuit turns off. It is illustrated in Figure 47.
After startup, the operating range is between 9 V and 20 V.
ON
State
OFF
VCC
6 mA
ICC
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