NCP1852AFCCT1G

NCP1852, NCP1852A Fully Integrated Li-Ion Switching Battery Charger with Power Path Management and USB On-The-Go Support The NCP1852 is a fully programmable single cell Lithium−ion switching battery charger optimized for charging from a USB compliant input supply and AC adaptor power source. The device integrates a synchronous PWM controller, power MOSFETs, and the entire charge cycle monitoring including safety features under software supervision. An optional battery FET can be placed between the system and the battery in order to isolate and supply the system. The NCP1852 junction temperature and battery temperature are monitored during charge cycle, and both current and voltage can be modified accordingly through I2C setting. The charger activity and status are reported through a dedicated pin to the system. The input pin is protected against overvoltages. The NCP1852 also provides USB OTG support by boosting the battery voltage as well as providing overvoltage protected power supply for USB transceiver. Features • • • • • • • • • • • • • • • • • 1.8 A Buck Converter with Integrated Pass Devices Input Current Limiting to Comply to USB Standard Automatic Charge Current for AC Adaptor Charging High Accuracy Voltage and Current Regulation Input Overvoltage Protection up to +28 V / −20 V Factory Mode 500 mA Boosted Supply for USB OTG Peripherals Reverse Leakage Protection Prevents Battery Discharge Protected USB Transceiver Supply Switch Dynamic Power Path with Optional Battery FET Battery Temperature Sensing for Safe Operation (JEITA) Silicon Temperature Supervision for Optimized Charge Cycle Safety Timers Flag Output for Charge Status and Interrupts I2C Control Bus up to 3.4 MHz Small Footprint 2.2 x 2.55 mm CSP Package These Devices are Pb−Free and are RoHS Compliant http://onsemi.com MARKING DIAGRAM 25 BUMP FLIP−CHIP CASE 499BN XXXX AYWW G XXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G or G = Pb−Free Package *Pb−Free indicator, “G” or microdot “ G”, may or may not be present. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 30 of this data sheet. Applications • • • • Smart Phone Handheld Devices Tablets PDAs © Semiconductor Components Industries, LLC, 2013 March, 2013 − Rev. 5 1 Publication Order Number: NCP1852/D NCP1852, NCP1852A CIN 1 mF NCP1852 CORE CCORE 2.2 mF USB PHY CBOOT SENSP SENSN WEAK FET CAP CCAP 4.7 mF VBUS D+ D− ID GND SW IN CTRS 0.1 mF TRANS BAT NTC ILIM1 ILIM2 OTG AGND PGND FLAG SCL SDA SPM LX 2.2 mH RSNS 68 mW COUT 10 mF CBOOT 10 nF QBAT(*) + *Optional Battery FET. Figure 1. Typical Application Circuit PIN CONNECTIONS 1 2 3 4 5 A IN IN SPM SDA SCL B CAP CAP OTG ILIM2 FLAG C SW SW AGND ILIM1 NTC D PGND PGND SENSP SENSN FET E CBOOT TRANS CORE WEAK BAT (Top View) Figure 2. Package Outline CSP http://onsemi.com 2 SYSTEM NCP1852, NCP1852A Table 1. PIN FUNCTION DESCRIPTION Pin Name Type Description A1 IN POWER A2 IN POWER A3 SPM DIGITAL INPUT System Power Monitor input. A4 SDA DIGITAL BIDIRECTIONAL I2C data line A5 SCL DIGITAL INPUT I2C clock line B1 CAP POWER B2 CAP POWER B3 OTG DIGITAL INPUT Enables OTG boost mode. OTG = 0, the boost is powered OFF OTG = 1 turns boost converter ON B4 ILIM2 DIGITAL INPUT Automatic charge current / Input current limiter level selection (can be defeated by I2C). B5 FLAG OPEN DRAIN OUTPUT Charging state active low. This is an open drain pin that can either drive a status LED or connect to interrupt pin of the system. C1 SW ANALOG OUTPUT C2 SW ANALOG OUTPUT C3 AGND ANALOG GROUND C4 ILIM1 DIGITAL INPUT Input current limiter level selection (can be defeated by I2C). C5 NTC ANALOG INPUT Input for the battery NTC (10 KW / B = 3900) or (4.7 KW / B = 3900) If not used, this pin must be tied to GND to configure the NCP1852 and warn that NTC is not used. D1 PGND POWER GND D2 PGND POWER GND D3 SENSP ANALOG INPUT Current sense input. This pin is the positive current sense input. It should be connected to the RSENSE resistor positive terminal. D4 SENSN ANALOG INPUT Current sense input. This pin is the negative current sense input. It should be connected to the RSENSE resistor negative terminal. This pin is also voltage sense input of the voltage regulation loop when the FET is present and open. D5 FET ANALOG OUTPUT E1 CBOOT ANALOG IN/OUT E2 TRANS ANALOG OUTPUT Output supply to USB transceiver. This pin can source a maximum of 50 mA to the external USB PHY or any other IC that needs +5 V USB. This pin is Overvoltage protected and will never be higher than 5.5 V. This pin should be bypassed by a 100 nF ceramic capacitor. E3 CORE ANALOG OUTPUT 5 V reference voltage of the IC. This pin should be bypassed by a 2.2 mF capacitor. No load must be connected to this pin. E4 WEAK ANALOG OUTPUT Weak battery charging current source input. E5 BAT ANALOG INPUT Battery Charger Input. These two pins must be decoupled by at least 1 mF capacitor and connected together. CAP pin is the intermediate power supply input for all internal circuitry. Bypass with at least 4.7 mF capacitor. Must be tied together. Connection from power MOSFET to the Inductor. These pins must be connected together. Analog ground / reference. This pin should be connected to the ground plane and must be connected together. Power ground. These pins should be connected to the ground plane and must be connected together. Battery FET driver output. When not used, this pin must be directly tied to ground. Floating Bootstrap connection. A 10 nF capacitor must be connected between CBOOT and SW. Battery connection http://onsemi.com 3 NCP1852, NCP1852A Table 2. MAXIMUM RATINGS Rating Symbol Value Unit VIN −20 to +28 V CAP (Note 1) VCAP −0.3 to +28 V Power balls: SW (Note 1) VSW −0.3 to +24 V VCBOOT −0.3 to VSW +7.0 V VCTRL −0.3 to +7.0 V Digital Input: SCL, SDA, SPM, OTG, ILIM1 and ILIM2 (Note 1) Input Voltage Input Current VDG IDG −0.3 to +7.0 V 20 V mA Storage Temperature Range TSTG −65 to +150 °C TJ −40 to +TSD °C MSL Level 1 IN (Note 1) CBOOT (Note 1) Sense/Control balls: SENSP, SENSN, VBAT, FET, TRANS, CORE, NTC, FLAG and WEAK. (Note 1) Maximum Junction Temperature (Note 4) Moisture Sensitivity (Note 5) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 3. OPERATING CONDITIONS Symbol Max Unit VIN Operational Power Supply 3 VINOV V VDG Digital input voltage level 0 5.5 V +85 °C 10 mA TA ISINK CIN Parameter Conditions Ambient Temperature Range Min −40 Typ 25 FLAG sink current 1 mF Decoupling Switcher capacitor 4.7 mF Decoupling core supply capacitor 2.2 mF Decoupling system capacitor 10 mF Switcher Inductor 2.2 mH RSNS Current sense resistor 68 mW RqJA Thermal Resistance Junction to Air 60 °C/W CCAP CCORE COUT LX TJ Decoupling input capacitor (Notes 4 and 6) Junction Temperature Range −40 25 +125 1. According to JEDEC standard JESD22−A108. 2. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114 for all pins. Machine Model (MM) ±200 V per JEDEC standard: JESD22−A115 for all pins. 3. Latch up Current Maximum Rating: ±100 mA or per ±10 mA JEDEC standard: JESD78 class II. 4. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation. See Electrical Characteristics. 5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020. 6. The RqJA is dependent on the PCB heat dissipation. Board used to drive this data was a 2s2p JEDEC PCB standard. http://onsemi.com 4 °C NCP1852, NCP1852A Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for VIN between 3.6 V to 7 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and VIN = 5 V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit Valid input detection threshold VIN rising 3.55 3.6 3.65 V VIN falling 2.95 3.0 3.05 V VIN falling 4.3 4.4 4.5 V Hysteresis 50 100 150 mV VIN rising 5.55 5.65 5.75 V Hysteresis 25 75 125 mV INPUT VOLTAGE VINDET VBUSUV USB under voltage detection VBUSOV USB over voltage detection VINOV Valid input high threshold VIN rising 7.1 7.2 7.3 V Hysteresis 200 300 400 mV IINLIM set to 100 mA 70 85 100 mA IINLIM set to 500 mA 425 460 500 mA IINLIM set to 900 mA 800 850 900 mA IINLIM set to 1500 mA 1.4 1.45 1.5 A INPUT CURRENT LIMITING IINLIM Input current limit VIN = 5 V INPUT SUPPLY CURRENT IQ_SW VBUS supply current IOFF No load, Charger active state 15 mA Charger not active, NTC disable 500 mA CHARGER DETECTION VCHGDET Charger detection threshold voltage VIN – VSENSN, VIN rising 40 100 150 mV VIN – VSENSN, VIN falling 20 30 50 mV REVERVE BLOCKING CURRENT ILEAK VBAT leakage current Battery leakage, VBAT = 4.2 V VIN = 0 V, SDA = SCL = 0 V 5 RRBFET Input RBFET On resistance (Q1) Charger active state, Measured between IN and CAP, VIN = 5 V − Programmable by I2C 3.3 80 mA 160 mW 4.5 V BATTERY AND SYSTEM VOLTAGE REGULATION VCHG Output voltage range Default value Voltage regulation accuracy Constant voltage mode, TA = 25°C 3.6 V −0.5 0.5 % −1 1 % I2C Programmable granularity 25 mV BATTERY VOLTAGE THRESHOLD VSAFE Safe charge threshold voltage VBAT rising 2.1 2.15 2.2 V VPRE Conditioning charge threshold voltage VBAT rising 2.75 2.8 2.85 V VFET End of weak charge threshold voltage 3.6 V 2 % VBAT rising Voltage range Default value Accuracy I2C Programmable granularity VRECHG Recharge threshold voltage 3.1 Relative to VCHG setting register http://onsemi.com 5 3.4 −2 100 mV 97 % NCP1852, NCP1852A Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for VIN between 3.6 V to 7 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and VIN = 5 V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit BATTERY VOLTAGE THRESHOLD VBUCKOV Overvoltage threshold voltage VBAT rising, relative to VCHG setting register, measured on SENSN or SENSP, QBAT close or no QBAT 115 % QBAT open. 5 V CHARGE CURRENT REGULATION ICHG Charge current range Programmable by I2C 400 Default value 950 Charge current accuracy 1000 −50 I2C Programmable granularity 1800 mA 1050 mA 50 mA 100 mA IPRE Pre−charge current VBAT < VPRE 80 100 120 mA ISAFE Safe charge current VBAT < VSAFE 8 10 12 mA IWEAK Weak battery charge current mA BATFET present, VSAFE < VBAT < VFET IWEAK[1:0] = 01 80 100 120 IWEAK[1:0] = 10 180 200 220 IWEAK[1:0] = 11 270 300 330 VBAT ≥ VRECHG Current range 100 CHARGE TERMINATION IEOC Charge current termination Default value Accuracy, IEOC < 200 mA I2C 275 mA 150 −25 Programmable granularity 25 25 FLAG VFOL FLAG output low voltage IFLAG = 10 mA 0.5 V IFLEAK Off−state leakage VFLAG = 5 V 1 mA TFLGON Interrupt request pulse duration Single event 250 ms 150 200 DIGITAL INPUT (VDG) VIH High−level input voltage VIL Low−level input voltage 1.2 RDG Pull down resistor IDLEAKK Input current VDG = 0 V −0.5 CAP pin supply voltage I2C registers available 2.5 V 0.4 500 V kW 0.5 mA I2C VSYSUV VI2CINT High level at SCL/SCA line VI2CIL SCL, SDA low input voltage VI2CIH SCL, SDA high input voltage V 1.7 5 V 0.4 V 0.8* VI2CI V NT VI2COL FSCL SCL, SDA low output voltage I2C ISINK = 3 mA clock frequency 0.3 V 3.4 MHz 150 °C JUNCTION THERMAL MANAGEMENT TSD TH2 Thermal shutdown Hot temp threshold 2 Rising 125 140 Falling 115 °C Relative to TSD −7 °C http://onsemi.com 6 NCP1852, NCP1852A Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for VIN between 3.6 V to 7 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and VIN = 5 V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit JUNCTION THERMAL MANAGEMENT TH1 Hot temp threshold 1 Relative to TSD −11 °C TWARN Thermal warning Relative to TSD −15 °C BATTERY THERMAL MANAGEMENT VNTCRMV Battery removed threshold voltage VNTC Rising 2.3 VCOLD Battery cold temperature corresponding voltage threshold Voltage range 1.425 Default 1.7 Voltage range 375 Default 500 VHOT Battery hot temperature corresponding voltage threshold VCOLD and VHOT voltage granularity VWARM 2.325 1.725 525 2.35 V 1.95 V 1.75 V 900 mV 550 mV 75 mV Battery warm temperature corresponding voltage threshold BATWARM = 0 VHOT+ 0.15 V BATWARM = 1 VHOT+ 0.225 V Battery chilly temperature corresponding voltage threshold BATCHILLY = 0 VCOLD− 0.15 V BATCHILLY = 1 VCOLD− 0.225 V VNTCDIS NTC disable corresponding voltage threshold VNTC Falling VREG RNTCPU VCHILLY 50 75 100 mV Internal voltage reference 2.35 2.4 2.45 V Internal resistor pull up 9.8 10 10.2 kW − 3 − MHz +10 % BUCK CONVERTER FSWCHG Switching Frequency Switching Frequency Accuracy −10 TDTYC Max Duty Cycle Average 99.5 % IPKMAX Maximum peak inductor current 2 A RONLS Low side Buck MOSFET RDSON (Q3) Measured between PGND and SW, VIN = 5 V − 80 200 mW RONHS High side Buck MOSFET RDSON(Q2) Measured between CAP and SW, VIN = 5 V − 130 250 mW 5 5.5 V PROTECTED TRANSCEIVER SUPPLY VTRANS Voltage on TRANS pin ITRMAX TRANS current capability ITROCP Short circuit protection VIN ≥ 5 V 50 mA 150 mA TIMING TWD Watchdog timer 32 s TUSB USB timer 2048 s http://onsemi.com 7 NCP1852, NCP1852A Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for VIN between 3.6 V to 7 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and VIN = 5 V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit Charge timer Safe−charge or pre−charge or weak−safe or weak−charge state. 3 h Full−charge state 2 h TIMING TCHG1 TCHG2 TWU Wake−up timer TST Charger state timer TVRCHR 64 s From Weak Charge to Full Charge State 32 s All others state 16 ms VBAT rising 15 ms VBAT falling 127 ms Minimum transition time from states to states. Deglitch time for end of charge voltage detection TINDET Deglitch time for input voltage detection VIN rising 15 ms TDGS1 Deglitch time for signal crossing IEOC, VPRE, VSAFE, VCHGDET, VINEXT thresholds. Rising and falling edge 15 ms TDGS2 Deglitch time for signal crossing VFET, VBUSUV, VBUSOV thresholds. Rising and falling edge 1 ms BOOST CONVERTER AND OTG MODE VIBSTL VIBSTH Boost minimum input operating range Boost start−up 3.1 3.2 3.3 V Boost running 2.9 3 3.1 V 4.4 4.5 4.6 V 5.1 5.15 V 3 % Boost maximum input operating range VOBST Boost Output Voltage DC value measured on CAP pin, no load 5.00 VOBSTAC Boost Output Voltage accuracy Measured on CAP pin Including line and load regulation −3 IBSTMX Output current capability FSWBST Switching Frequency 500 Switching Frequency Accuracy IBPKM Maximum peak inductor current VOBSTOL Boost overload TOBSTOL VOBSTOV −10 MHz 10 2 Boost running, voltage on IN pin 4.3 Maximum capacitance on IN pin during start−up ROBSTOL mA 1.5 Minimum load resistance on IN pin during start−up Overvoltage protection A 4.5 V 10 mF NCP1852 170 W NCP1852A 50 VIN rising 5.55 5.65 5.75 V Hysteresis 25 75 125 mV http://onsemi.com 8 4.4 % NCP1852, NCP1852A BLOCK DIAGRAM CAP VCAP IN CBOOT Q1 Charge Pump VCORE Drv Q2 VCAP 5V reference CORE VREG VCORE Current, Voltage, and Clock Reference PWM generator IINREG ICHG VTJ VCHG Drv SW VCORE TRANS Q3 Drv VTJ TSD + − + + − V BATOV + − V RECHG + TH2 − + TH1 − + TWARN ILIM2 PGND + IEOC − I BAT VBAT SENSP ICHG Amp ILIM1 SAFE I2C & DIGITAL CONTROLER OTG VIN VINDET AGND VBAT + −V + − + − + − − + VBUSUV + − VBUSOV + − V INOV VCHGDET − + − + + − + − + RMOVED VCOLD VCHILLY SENSN WEAK − V FET + − V PRE + − V − + − BAT BATFET detection & Drive VREG RNTCPU FET NTC SPM VWARM VHOT VNTCDIS FLAG SCL SDA Figure 3. Block Diagram http://onsemi.com 9 NCP1852, NCP1852A TYPICAL APPLICATION CIRCUITS CIN NCP1852 1.0 mF CBOOT CAP CCAP VBUS D+ D− ID GND SW IN LX 2.2 mH RSNS 68 mW CSYS CBOOT 10 mF 10 nF SYSTEM SENSP SENSN 4.7 mF WEAK CCORE CORE FET TRANS NTC ILIM1 ILIM2 OTG AGND FLAG 2.2 mF QBAT(*) BAT CTRS + 0.1 mF USB PHY SCL SDA SPM PGND Figure 4. USB Charger with Battery External MOSFET NCP1852 1.0 mF CBOOT CCAP CCAP CAP 2.2 mF CBOOT 10 nF SYSTEM SENSP RSNS 68 mW WEAK CSYS FET CORE CCORE + 2.2 mF BAT CTRS USB PHY LX SENSN 4.7 mF VBUS D+ D− ID GND SW IN CIN NTC TRANS 0.1 mF ILIM1 ILIM2 OTG AGND FLAG PGND SPM SCL SDA Figure 5. USB Charger without Battery External MOSFET http://onsemi.com 10 10 mF NCP1852, NCP1852A TYPICAL CHARACTERISTICS Figure 6. VBUS Insertion Figure 7. Charger Mode Efficiency Figure 8. Automatic Charge Current Figure 9. Dynamic Power Path Figure 10. Boost Mode: Power−up Figure 11. Over Voltage Protection http://onsemi.com 11 NCP1852, NCP1852A CHARGE MODE OPERATION The NCP1852 is fully programmable through I2C interface (see Registers Map section for more details). All registers can be programmed by the system controller at any time during the charge process. The charge current (ICHG), charge voltage (VCHG), and input current (IINLIM) are controlled by a dynamic voltage and current scaling for disturbance reduction. Is typically 10 ms for each step. NCP1852 also provides USB OTG support by boosting the battery voltage as well as an over voltage protected power supply for USB transceiver. Overview The NCP1852 is a fully programmable single cell Lithium−ion switching battery charger optimized for charging from a USB compliant input supply. The device integrates a synchronous PWM controller; power MOSFETs, and monitoring the entire charge cycle including safety features under software supervision. An optional battery FET can be placed between the system and the battery in order to isolate and supply the system in case of weak battery. The NCP1852 junction temperature and battery temperature are monitored during charge cycle and current and voltage can be modified accordingly through I2C setting. The charger activity and status are reported through a dedicated pin to the system. The input pin is protected against overvoltages. Charge Profile In case of application without QFET (see Figure 5), the NCP1852 provides 4 main charging phases as described below. Unexpected behaviour or limitations that can modify the charge sequence are described further (see Charging Process section). VBAT IBAT VCHG VRECHG ICHG IPRE VPRE IEOC ISAFE VSAFE Safe Charge Pre Charge Constant Current Constant Voltage End of Charge Figure 12. Typical Charging Profile of NCP1852 current. The battery stays in preconditioning until the VBAT voltage is lower than VPRE threshold. Constant Current (full charge): In the constant current phase (full charge state), the DC−DC convertor is enabled and an ICHG current is delivered to the load. As battery voltage could be sufficient, the system may be awake and sink an amount of current. In this case the charger output load is composed of the battery and the system. Thus ICHG current delivered by the NCP1852 is shared between the battery and the system: ICHG = ISYS + IBAT. Safe Charge: With a disconnected battery or completely empty battery, the charge process is in safe charge state, the charge current is set to ISAFE in order to charge up the system’s capacitors or the battery. When the battery voltage reaches VSAFE threshold, the battery enters in pre−conditioning. Pre Conditioning (pre−charge): In preconditioning (pre charge state), the DC−DC convertor is enabled and an IPRE current is delivered to the battery. This current is much lower than the full charge http://onsemi.com 12 NCP1852, NCP1852A System awake VBAT VCHG VRECHG ICHG VBAT IBAT IBAT IPRE ISYS VPRE IEOC ISAFE VSAFE Safe Charge Pre Charge Constant Current Constant Voltage End of Charge Figure 13. Typical Charging Profile of NCP1852 with System Awake ICHG current is programmable using I2C interface (register IBAT_SET − bits ICHG[3:0]). Constant Voltage (full charge): The constant voltage phase is also a part of the full charge state. When the battery voltage is close to its maximum (VCHG), the charge circuit will transition from a constant current to a constant voltage mode where the charge current will slowly decrease (taper off). The battery is now voltage controlled. VCHG voltage is programmable using I2C interface (register VBAT_SET− bits CTRL_VBAT[5:0]). End of Charge: The charge is completed (end of charge state) when the battery is above the VRECHG threshold and the charge current below the IEOC level. The battery is considered fully charged and the battery charge is halted. Charging is resumed in the constant current phase when the battery voltage drops below the VRECHG threshold. IEOC current is programmable using I2C interface (register IBAT_SET− bits IEOC[2:0]). In order to prevent battery discharge and overvoltage protection, Q1 (reverse voltage protection) and Q2 (high side N−MOSFET of the DC−DC converter) are mounted in a back−to−back common drain structure while Q3 is the low side N MOSFET of the DC−DC converter. Q2 gate driver circuitry required an external bootstrap capacitor connected between CBOOT pin and SW pin. An internal current sense monitors and limits the maximum allowable current in the inductor to IPEAK value. Charger Detection, Start−up Sequence and System Off The start−up sequence begins upon an adaptor valid voltage plug in detection: VIN > VINDET and VIN − VBAT > VCHGDET (off state). Then, the internal circuitry is powered up and the presence of NTC and BATFET are reported (register STATUS – bit BATFET and NTC). When the power−up sequence is done, the charge cycle is automatically launched. At any time and any state, the user can hold the charge process and transit to fault state by setting CHG_EN to ‘0’ (register CTRL1) in the I2C register. Furthermore, during fault state, NTC block can be disabled for power saving (bit NTC_EN register CTRL1) The I2C registers are accessible without valid voltage on VIN if VCAP > VSYSUV (i.e. if VBAT is higher than VSYSUV + voltage drop across Q2 body diode). At any time, the user can reset all register stack (register CTRL1 – bit REG_RST). Power Stage Control NCP1852 provides a fully−integrated 3 MHz step−down DC−DC converter for high efficiency. For an optimized charge control, 3 feedback signals control the PWM duty cycle. These 3 loops are: maximum input current (IINLIM), maximum charge current (ICHG) and, maximum charge voltage (VCHG). The switcher is regulated by the first loop that reaches its corresponding threshold. Typically during charge current phase (VPRE < VBAT < VRECHG), the measured input current and output voltage are below the programmed limit and asking for more power. But in the same time, the measured output current is at the programmed limit and thus regulates the DC−DC converter. Weak Battery Support An optional battery FET (QBAT) can be placed between the application and the battery. In this way, the battery can be isolated from the application and so−called weak battery operation is supported. http://onsemi.com 13 NCP1852, NCP1852A lower than VFET and host system in shutdown mode (SPM = 0). The DCDC converter from VIN to SW is enabled and set to VCHG while the battery FET QBAT is opened. The system is now powered by the DC−DC. The internal current source to the battery is disabled. In weak wait state, the state machine verifies if the battery temperature is OK thanks to the NTC sensor. If NTC OK or if NTC is not present (NTC pin tied to 0), this state is left for weak safe state. In case of no battery, the NCP1852 stay in weak wait state (the system is powered by DC−DC). Weak safe The voltage at VBAT, is below the VSAFE threshold. In weak safe state, the battery is charged with a linear current source at a current of ISAFE. The DC−DC converter is enabled and set to VCHG while the battery FET QBAT is opened. In case the ILIM pin is not made high or the input current limit defeated by I2C before timer expiration, the state is left for the safe charge state after a certain amount of time (see Wake up Timer section). Otherwise, the state machine will transition to the weak charge state once the battery is above VSAFE. Weak charge The voltage at VBAT, is above the VSAFE threshold. The DC−DC converter is enabled and set to VCHG. The battery is initially charged at a charge current of IWEAK supplied by a linear current source from WEAK pin (i.e. DC−DC converter) to BAT pin. IWEAK value is programmable (register MISC_SET bits IWEAK). The weak charge timer (see Wake up Timer section) is no longer running. When the battery is above the VFET threshold (programmable), the state machine transitions to the full charge state thus BATFET QBAT is closed. Typically, when the battery is fully discharged, also referred to as weak battery, its voltage is not sufficient to supply the application. When applying a charger, the battery first has to be pre−charged to a certain level before operation. During this time; the application is supplied by the DC−DC converter while integrated current sources will pre−charge the battery to the sufficient level before reconnecting. The pin FET can drive a PMOS switch (QBAT) connected between BAT and WEAK pin. It is controlled by the charger state machine (Charging process section). The basic behaviour of the FET pin is that it is always low. Thus the PMOS is conducting, except when the battery is too much discharged at the time a charger is inserted under the condition where the application is not powered on. The FET pin is always low for BAT above the VFET threshold. Some exceptions exist which are described in the Charging process and Power Path Management section. The VFET threshold is programmable (register MISC_SET – bit CTRL_VFET). Batfet detection The presence of a PMOS (QBAT) at the FET pin is verified by the charging process during its config state. To distinguish the two types of applications, in case of no battery FET the pin FET is to be tied to ground. In the config state an attempt will be made to raise the FET pin voltage slightly up to a detection threshold. If this is successful it is considered that a battery FET is present. The batfet detection is completed for the whole charge cycle and will be done again upon unplug condition (VBAT < VINDET or VIN − VBAT < VCHGDET) or register reset (register CTRL1– bit REG_RST). Weak wait Weak wait state is entered from wait state (see Charging process section) in case of BATFET present, battery voltage IOUT VBAT VCHG ICHG VRECHG VBAT VSYS IBAT IWEAK VBAT VFET IBAT ISYS IEOC ISAFE VSAFE Weak Wait Weak Safe Weak Charge Constant Current Figure 14. Weak Charge Profile http://onsemi.com 14 Constant Voltage End of Charge NCP1852, NCP1852A Weak Charge Exit Charge Timer A charge timer TCHG is running that will make that the overall charge to the battery will not exceed a certain amount of energy. The charge timer is running during charger active states and halted during charger not active states (see Charging process section). The timer can also be cleared any time through I2C (register CTRL1 – bit TCHG_RST). The state machine transitions to fault state when the timer expires. This timer can be disabled (Register CTRL2 bit CHGTO_DIS). USB Timer A USB charge timer TUSB is running in the charger active states while halted in the charger non active states. The timer keeps running as long as the lowest input current limit remains selected either by ILIM pin or I2C (register I_SET – bit IINLIM and IINLIM_EN). This will avoid exceeding the maximum allowed USB charge time for un−configured connections. When expiring, the state machine will transition to fault state. The timer is cleared in the off state or by I2C command (register CTRL1 – bit TCHG_RST). Wake up Timer Before entering weak charge state, NCP1852 verifies if the input current available is enough to supply both the application and the charge of the battery. A wake−up timer TWU verifies if ILIM pin is raised fast enough or application powered up (by monitoring register I_SET – bit IINLIM and IINLIM_EN level) after a USB attachment. The wake up timer is running in weak wait state and weak safe state and clears when the input current limit is higher than 100 mA. In some application cases, the system may not be able to start in weak charge states due to current capability limitation or/and configuration of the system. If so, in order to avoid unexpected “drop and retry” sequence of the buck output, the charge state machine allows only 3 system power−up sequences based on SPM pin level: If SPM pin level is toggled 3 times during weak charge states, the system goes directly to safe charge state and a full charge mode sequence is initiated (“Power fail” condition in Charging process section). Power Path Management Power path management can be supported when a battery FET (QBAT) is placed between the application and the battery. When the battery is fully charged (end of charge state), power path management disconnects the battery from the system by opening QBAT, while the DC−DC remains active. This will keep the battery in a fully charged state with the system being supplied from the DC−DC. If a load transient appears exceeding the DC−DC output current and thus causing VSENSEN to fall below VRECHG, the FET QBAT is instantaneously closed to reconnect the battery in order to provide enough current to the application. The FET QBAT remains closed until the end of charge state conditions are reached again. The power path management function is enabled through the I2C interface (register CRTL2 bit PWR_PATH=1). Safety Timer Description The safety timer ensures proper and safe operation during charge process. The set and reset condition of the different safety timer (Watchdog timer, Charge timer, Wakeup timer and USB timer) are detailed below. When a timer expires (condition “timeout” in Charging process section), the charge process is halted. Watchdog Timer Watchdog timer ensures software remains alive once it has programmed the IC. The watchdog timer is no longer running since I2C interface is not available. Upon an I2C write, automatically a watchdog timer TWD is started. The watchdog timer is running during charger active states and fault state. Another I2C write will reset the watchdog timer. When the watchdog times out, the state machine reverts to fault state and reported through I2C interface (register CHINT2– bit WDTO). Also used to time out the fault state. This timer can be disabled (Register CTRL2 bit WDTO_DIS). Input Current Limitation In order to be USB specification compliant, the input current at VIN is monitored and could be limited to the IINLIM threshold. The input current limit threshold is selectable through the ILIMx pin. When low, the one unit USB current is selected (IIN ≤ 100 mA), where when made high 5 units are selected (IIN ≤ 500 mA). In addition, this current limit can be programmed through I2C (register MISC_SET bits IINLIM) therefore defeating the state of the ILIMx pin. In case of non−limited input source, current limit can be disabled (register CTRL2 bit IINLIM_EN). The current limit is also disabled in case the input voltage exceeds the VBUSOV threshold. http://onsemi.com 15 NCP1852, NCP1852A IBAT VBAT VCHG VRECHG ICHG IPRE VPRE IEOC ISAFE VSAFE Safe Charge Pre Charge Constant Current Constant Voltage End of Charge Figure 15. Typical Charging Profile of NCP1852 with Input Current Limit Input Voltage Based Automatic Charge Current ILIM1 ILIM2 Input Current Limit 0 0 100 mA 0 1 Automatic Charge Current 1 0 500 mA Between TWARN and TSD threshold, a junction temperature management option is available by setting 1 to TJ_WARN_OPT bit (register CONTROL). In this case, if the die temperature hits TM1 threshold, an interrupt is generated again but NCP1852 will also reduce the charge current ICHG by two steps or 200 mA. This should in most cases stabilize the die temperature because the power dissipation will be reduced by approximately 50 mW. If the die temperature increases further to hit TM2, an interrupt is generated and the charge current is reduced to its lowest level or 400 mA. The initial charge current will be re−established when the die temperature falls below the TWARN again. If bit TJ_WARN_OPT = 0 (register CTRL1), the charge current is not automatically reduced, no current changes actions are taken by the chip until TSD. 1 1 900 mA Battery Temperature Management If the input power source capability is unknown, automatic charge current will automatically increase the charge current step by step until the VIN drops to VBUSUV. Upon VBUSUV being triggered, the charge current ICHG is immediately reduced by 1 step and stays constant until VIN drops again to VBUSUV. The ICHG current is clamped to the I2C register value (register IBAT_SET, bits ICHG). This unique feature is enabled when the pins ILIM1 = 0 and ILIM2 = 1 or through I2C register (register CRTL2 bit AICL_EN). For battery safety, charging is not allowed for too cold or too hot batteries. The battery temperature is monitored through a negative temperature coefficient (NTC) thermistor mounted in the battery pack or on the phone PCB close to the battery pack. In some cases the NTC is handled by the platform and will not be connected to the charger IC. NCP1852 provides a NTC pin for monitoring an external NTC thermistor. NTC pin is connected to an internal voltage VREG through pull−up resistor (RNTCPU). By connecting a NTC thermistor between NTC pin and GND, internal comparators can monitor voltage variation and provide temperature information to the state machine. Junction Temperature Management During the charge process, NCP1852 monitors the temperature of the chip. If this temperature increases to TWARN, an interrupt request (described in section Charge status reporting ) is generated and bit TWARN_SNS is set to ‘1’ (register NTC_TH_SENSE). Knowing this, the user is free to halt the charge (register CTRL − bit CHG_EN) or reduce the charge current (register I_SET − bits ICHG). When chip temperature reaches TSD value, the charge process is automatically halt. http://onsemi.com 16 NCP1852, NCP1852A temperature scheme (bit JEITA_OPT = 1 in CTRL1 register) will halt charging outside the cold−hot window while reducing the charge voltage and current in the warm−hot and chilly−cold window with VCHGRED (register NTC_SET1) and ICHGRED (register NTC_SET1). The state machine (see Charging process section), takes the chilly−warm respectively the cold−hot window for not out of temp detection. This boils down into selecting between ICHGRED or no current for the warm−hot and cold−chilly window. In both cases, the charge voltage and charge current can be reprogrammed while in the warm−hot and cold−chilly window. Together with the programmable thresholds this effectively allows the use of different charging schemes at different temperatures as well as to accommodate to different NTC characteristics. Cold, chilly, warm and hot threshold can be set respectively with bits BATCOLD, BATCHILLY, BATWARM and BATHOT of NTC_SET2 register. In addition to the above, comparators monitor the NTC presence. When the NTC is removed (VNTC > VNTCRMV), no more charge current is supplied to the battery and an interrupt is generated (describe in section Charge status reporting). This functionality can be disabled through programming (bit NTC_EN in register CTRL1). When the NTC is not used in the application the NTC pin can be tied to ground (VNTC < VNTCDIS) which will disable the battery temperature monitoring function. VREG RNTCPU + − V RMOVED + − + − − + − + − + VCOLD NTC VCHILLY + VWARM VHOT VNTCDIS NCP1852 Figure 16. NTC Monitoring Circuit Four thresholds ‘cold’, ‘chilly’, ‘warm’ and ‘hot’ are provided those are all programmable. The corresponding voltage levels of these thresholds are respectively VCOLD, VCHILLY, VWARM and VHOT. Interrupts (describe in section Charge status reporting) are generated when crossing either threshold. Two charging schemes are available through I2C using these four thresholds. The default scheme (bit JEITA_OPT = 0 in CTRL1 register) will halt charging outside the cold−warm window. A second extended VBAT IBAT VCHG VBAT VCHG − VCHGRED ICHG ICHGRED IBAT Battery Temperature TCOLD TCHILLY TWARM THOT Figure 17. Charge Voltage and Current versus Battery Temperature (JEITA_OPT) http://onsemi.com 17 NCP1852, NCP1852A Use Case of Current and Voltage Charge If configured, charge current and voltage is automatically modified by the input current limit, chip temperature and battery temperature. IBAT Constant current charge mode ICHG = 1.5 A, VCHG = 4.2 V, VCHGRED = 0.2 V, ICHGRED = 0.7 A VBAT 4.2 V VBAT 4V 1.5 A 1.3 A IBAT IBAT 1A 0.7 A 0.6 A 0.5 A 0.4 A Chip temperature: : USB 5 units charge: IIINLIM = 500 mA t Battery temperature: TJ > TH1 TJ > TH2 TBAT < TCOLD TBAT: OK TBAT > TWARM TBAT > THOT Figure 18. Use Case Charge Voltage and Current Regulated Power Supply (Trans pin) NCP1852 has embedded a linear voltage regulator (VTRANS) able to supply up to ITRMAX to external loads. This output can be used to power USB transceiver. Trans pin is enabled if a VBUS valid is connected on input pin (VBUSUV < VIN < VBUSOV) and can be disabled through I2C (bit TRANS_EN_REG register CTRL2). http://onsemi.com 18 NCP1852, NCP1852A Charge Status Reporting If more than 1 interrupt appears, only 1 pulse is generated while interrupt registers (STAT_INT, CH1_INT, CH2_INT, BST_INT) will not fully clear. Sense and Status Registers At any time the system processor can know the status of all the comparators inside the chip by reading VIN_SNS, VBAT_SNS, and TEMP_SNS registers (read only). These bits give to the system controller the real time values of all the corresponding comparators outputs (see BLOCK DIAGRAM). FLAG pin FLAG pin is to used to report charge status to the system processor and for interruption request. During charger active states and wait state, the pin FLAG is low in order to indicate that the charge of the battery is in progress. When charge is completed or disabled or a fault occurs, the FLAG pin is high as the charge is halted. STATUS and CONTROL Registers The status register contains the current charge state, NTC and BATFET connection as well as fault and status interrupt (bits FAULTINT and STATINT in register STATUS). The charge state (bits STATE in register STATUS) is updated on the fly and corresponds to the charging state describe in Charging process section. An interruption (see description below) is generated upon a state change. In the config state, hardware detection is performed on BAFTET and NTC pins. From wait state, their statuses are available (bit BATFET and NTC in register STATUS). STATINT bit is set to 1 if an interruption appears on STAT_INT register (see description below). FAULTINT bit is set to 1 if an interruption appears on registers CH1_INT, CH1_INT or BST_INT. Thanks to this register, the system controller knows the chip status with only one I2C read operation. If a fault appears or a status change (STATINT bits and FAULTINT), the controller can read corresponding registers for more details. Interruption Upon a state or status change, the system controller is informed by sensing FLAG pin. A TFLAGON pulse is generated on this pin in order to signalize an event. The level of this pulse depends on the state of the charger (see Charging process section): • When charger in is charger active states and wait state the FLAG is low and consequently the pulse level on FLAG pin is high. • In the others states, the pulse level is low as the FLAG stable level is high. Charge state transition even and all bits of register STAT_INT, CH1_INT, CH2_INT, BST_INT generate an interrupt request on FLAG pin and can be masked with the corresponding mask bits in registers STAT_MSK, CH1_MSK, CH2_MSK and BST_MSK. All interrupt signals can be masked with the global interrupt mask bit (bit INT_MASK register CTRL1). All these bits are read to clear. The register map (see REGISTERS MAP section) indicated the active transition of each bits (column “TYPE” in see REGISTERS MAP section). Battery Removal and No Battery Operation During normal charge operation the battery may bounce or be removed. The state transition of the state machine only occurs upon deglitched signals which allow bridging any battery bounce. True battery removal will last longer than the debounce times. The NCP1852 responses depend on NTC and BATFET presence: If the battery is equipped with an NTC its removal is detected (VNTC > VNTCRMV) and the state machine transits to fault state and an interrupt is generated (bit BATRMV register CH1_INT). Then, in case of applications with BATFET, the state machine will end up in weak wait state so the system is powered by the DC−DC converter (see Weak wait section) without battery. In case of application without BATFET, the state machine will end up in fault state (DC−DC off) so the system is not powered. With a battery pack without NTC support, the voltage at VBAT will rapidly reach the DCDC converter setting VCHG and then transition to end of charge state causing DC−DC off. Thus VBAT falls (“Battery fail” condition in Charging process section). Factory Mode During factory testing no battery is present in the application and a supply could be applied through the bottom connector to power the application. The state machine will support this mode of operation under the condition that the application includes a battery FET and uses batteries with NTC support (similar as no battery operation). In this case, the state machine will end up in weak wait state (see Weak wait section). The application is supplied while the absence of the battery pack is interpreted as a battery pack out of temperature (VNTC > VCOLD). Through I2C the device is entirely programmable so the controller can configure appropriate current and voltage threshold for handle factory testing. Factory regulation mode (Register CTRL2 Bit FCTRY_MOD_REG) is accessible for factory testing purpose. In this mode, input and charge current loops are disabled, allowing full power to the system. http://onsemi.com 19 NCP1852, NCP1852A CHARGING PROCESS CHARGER ACTIVE: WEAK CHARGE MODE CHARGER NOT ACTIVE MODE WEAK WAIT − BUCK: ON − IWEAK: OFF − ISAFE: OFF − FLAG: LOW − QFET: OFF VCAP > VSYSUV OFF − Charger OFF IQ < IOFF − I2C available −VIN < VINDET or −VIN − VBAT < VCHGDET Halt Charging: VNTC > VCOLD or VNTC < VWARM Start Charging: VNTC < VCOLD or VNTC > VWARM ANY STATE −VIN > VINDET and −VIN − VBAT > VCHGDET WEAK SAFE Batfet present and VBAT < VFET and SPM = 0 REG_RST = 1 CONFIG − BUCK: ON − IWEAK: OFF − ISAFE: ON − FLAG: LOW − QFET: OFF − Power−up − NTC and BATFET detection − Q1: ON VNTC > VCOLD or VNTC < VWARM or VBAT > VSAFE VBAT > VSAFE and IINLIM ≥ 500 mA WEAK CHARGE −VIN > VINOV or −VBAT > VBUCKOV or −Timeout or −Power fail or −TJ > TSD or −CHR_EN = 0 Power−up and detection done WAIT − BUCK: OFF − IWEAK: OFF − ISAFE: OFF − FLAG: LOW − QFET: ON − BUCK: ON − IWEAK: ON − ISAFE: OFF − FLAG: LOW − QFET: OFF FAULT Fault removed and CHR_EN = 1 −Timeout −TJ > TSD or −VIN > VINOV or −VBAT > VBATOV or −CHR_EN = 0 − BUCK: OFF − IWEAK: OFF − ISAFE: OFF − FLAG: HIGH − QFET: ON −Timeout −TJ > TSD or −VIN > VINOV or −VBAT > VBUCKOV or −VNTC > VNTCRMV or −CHR_EN = 0 −TJ > TSD or −VIN > VINOV or −VNTC > VNTCRMV or −CHR_EN = 0 VBAT > VFET FULL CHARGE − BUCK: ON − IWEAK: OFF − ISAFE: OFF − FLAG: LOW − QFET: ON END OF CHARGE − BUCK: OFF* − IWEAK: OFF − ISAFE: OFF − FLAG: HIGH − QFET: ON* −VSENSN > VRECHG and −pwr_path = 1 −VBAT > VRECHG and −IBAT < IEOC −VBAT > VRECHG and −IBAT < IEOC DPP − BUCK: ON − IWEAK: OFF − ISAFE: OFF − FLAG: HIGH − QFET: ON Halt Charging: VNTC > VCOLD or VNTC < VWARM or Battery fail VBAT > VPRE VBAT < VPRE PRE CHARGE − BUCK: ON (precharge) − IWEAK: OFF − ISAFE: OFF − FLAG: LOW − QFET: ON VBAT > VSAFE VBAT < VSAFE Timeout SAFE CHARGE − BUCK: OFF − IWEAK: OFF − ISAFE: ON − FLAG: LOW − QFET: ON Start Charging: VCOLD > VNTC > VWARM CHARGER ACTIVE: FULL CHARGE MODE (*) see Power Path Management section Figure 19. Detailed Charging Process http://onsemi.com 20 NCP1852, NCP1852A BOOST MODE OPERATION The DC−DC Converter can also be operated in a Boost mode where the application voltage is stepped up to the input VIN for USB OTG supply. The converter operates in a 1.5 MHz fixed frequency PWM mode or in pulse skipping mode under low load condition. In this mode, where CAP is the regulated output voltage, Q3 is the main switch and Q2 is the synchronous rectifier switch. While the boost converter is running, the Q1 MOSFET is fully turned ON. turns off the PWM converter. A fault is indicated to the system controller (bit VBATLO register BST_INT) A toggle on OTG pin or OTG_EN bit (register CTRL1) is needed to start again a boost operation. Boost Status Reporting STATUS and CTRL registers The status register contains the boost status. Bits STATE in register STATUS gives the boost state to the system controller. Bits FAULTINT and STATINT in register STATUS are also available in boost mode. If a fault appears or a status changes (STATINT bits and FAULTINT) the processor can read corresponding registers for more details. Interruption In boost mode, valid interrupt registers are STAT_INT and BST_INT while CH1_INT and CH2_INT are tied to their reset value. Upon a state or status changes, the system controller is informed by sensing FLAG pin. Like in charge mode, TFLAGON pulse is generated on this pin in order to signalize the event. The pulse level is low as the FLAG level is high in boost mode. Charge state transition even and all signals of register BST_INT can generate an interrupt request on FLAG pin and can be masked with the corresponding mask bits in register BST_MSK. All these bits are read to clear. The register map (see Registers Map section) indicates the active transition of each bits (column “TYPE” in see Registers Map section). If more than 1 interrupt appears, only 1 pulse is generated while interrupt registers (listed just above) will not fully clear. Sense and Status Registers At any time the system controller can know the status of all the comparator inside the chip by reading VIN_SNS and TEMP_SNS registers (read only). These bits give to the controller the real time values of all the corresponding comparators outputs (see Block Diagram). Boost Start−up The boost mode is enabled through the OTG pin or I2C (register CTRL1 − bit OTG_EN). Upon a turn on request, the converter regulates CAP pin, and the output voltage is present on IN pin through the Q1 MOSFET which is maintained close unless OVLO event. During start−up phase, if the IN pin cannot reach voltage higher than VBUSUV within 16 ms, then a fault is indicated to the system controller (bit VBUSILIM register BST_INT) and the boost is turns−off. VIN Over−Voltage Protection The NCP1852 contains integrated over−voltage protection on the VIN line. During boost operation (VIN supplied), if an over−voltage condition is detected (VIN > VBUSOV), the controller turns off the PWM converter. OTG_EN bit (register CTRL1) is set to 0 and a fault is indicated to the system controller (bit VBUSOV register BST_INT) VIN Over−Current Protection The NCP1852 contains over current protection to prevent the device and battery damage when VIN is overloaded. When the IN voltage drops down to VBUSUV, NCP1852 determine an over−current condition is met, so Q1 MOSFET and PWM converter are turned off. A fault is indicated to the system controller (bit VBUSILIM register BST_INT). Battery Under−Voltage Protection During boost mode, when the battery voltage is lower than the battery under voltage threshold (VBAT < VIBSTL), the IC I2C DESCRIPTION NCP1852 can support a subset of I2C protocol, below are detailed introduction for I2C programming. FROM MCU to NCPxxxx FROM NCPxxxx to MCU START IC ADRESS 1 ACK 0 ACK DATA 1 ACK DATA n /ACK STOP READ OUT FROM PART STOP WRITE INSIDE PART 1 à READ START IC ADRESS DATA 1 ACK DATA n /ACK ACK If PART does not Acknowledge, the /NACK will be followed by a STOP or Sr. If PART Acknowledges, the ACK can be followed by another data or Stop or Sr 0 à WRITE Figure 20. General Protocol Description http://onsemi.com 21 NCP1852, NCP1852A • In case of read operation, the NCP1852 will output the The first byte transmitted is the Chip address (with LSB bit sets to 1 for a read operation, or sets to 0 for a Write operation). Then the following data will be: • In case of a Write operation, the register address (@REG) we want to write in followed by the data we will write in the chip. The writing process is incremental. So the first data will be written in @REG, the second one in @REG + 1…. The data are optional. data out from the last register that has been accessed by the last write operation. Like writing process, reading process is an incremental process. Read Out from Part The Master will first make a “Pseudo Write” transaction with no data to set the internal address register. Then, a stop then start or a Repeated Start will initiate the read transaction from the register address the initial write transaction has set: FROM MCU to NCPxxxx FROM NCPxxxx to MCU STETS INTERNAL REGISTER POINTER START IC ADRESS 0 ACK REGISTER ADRESS ACK STOP 0 à WRITE START IC ADRESS 1 ACK ACK DATA 1 /ACK DATA n STOP REGISTER ADRESS + (n − 1) VALUE REGISTER ADRESS VALUE n REGISTERS READ 1 à READ Figure 21. Read Out from Part The first WRITE sequence will set the internal pointer on the register we want access to. Then the read transaction will start at the address the write transaction has initiated. Write in Part: Write operation will be achieved by only one transaction. After chip address, the MCU first data will be the internal register we want access to, then following data will be the data we want to write in Reg, Reg + 1, Reg + 2,…., Reg +n. Write n Registers: FROM MCU to NCPxxxx FROM NCPxxxx to MCU WRITE VALUE IN REGISTER REG0 SETS INTERNAL REGISTER POINTER START IC ADRESS 0 ACK REGISTER REG0 ADRESS ACK WRITE VALUE IN REGISTER REG0 + (n − 1) ACK REG VALUE ACK REG + (n − 1) VALUE STOP n REGISTERS WRITE 0 à WRITE Figure 22. Write in n Registers I2C Address NCP1852 has fixed I2C but different I2C address (0$10, 7 bit address, see below table A7~A1), NCP1852 supports 7−bit address only. Table 5. NCP1852 I2C ADDRESS I2C Address (Note 7) Default Hex A7 A6 A5 A4 A3 A2 A1 A0 $6C / $6D 0 1 1 0 1 1 0 X 7. Other addresses are available upon request. http://onsemi.com 22 NCP1852, NCP1852A Table 6. REGISTERS MAP Bit Type Reset Name RST Value Function STATUS REGISTER − Memory location : 00 7−4 R No_Reset STATE[3:0] 0000 Charge mode: −0000 : OFF −0001 : WAIT + STBY −0010 : SAFE CHARGE −0011 : PRE CHARGE −0100 : FULL CHARGE −0101 : VOLTAGE CHARGE −0110 : CHARGE DONE −0111 : DPP −1000 : WEAK WAIT −1001 : WEAK SAFE −1010 : WEAK CHARGE −1011 : FAULT Boost mode: −1100 : BOOST WAIT(s_WAIT) −1101 : BOOST MODE (s_ON) −1110 : BOOST FAULT( s_FAULT) −1111 : BOOST OVER LOAD (s_OL)) 3 R No_Reset BATFET 0 Indicate if a batfet is connected: 0 : No BATFET is connected 1 : BATFET is connected. 2 R No_Reset NTC 0 Indicate if a ntc resistor is present: 0 : No NTC connected 1: NTC connected 1 R No_Reset STATINT 0 Status interrupt: 0 : No status interrupt 1 : Interruption flagged on STAT_INT register 0 R No_Reset FAULTINT 0 Fault interrupt: 0 : No status interrupt 1 : interruption flagged on CHRIN1, CHRIN2 or BST_INT register CTRL1 REGISTER − Memory location : 01 7 RW OFF STATE, POR, REG_RST REG_RST 0 Reset: 0 : No reset 1 : Reset all registers 6 RW OFF STATE, POR, REG_RST CHG_EN 1 Charge control: 0 : Halt charging (go to fault state) or OTG operation 1 : Charge enabled / Charge resume 5 RW OFF STATE, POR, REG_RST, CHGMODE OTG_EN 0 On the go enable: 0 : no OTG operation 1 : OTG operation (set by I2C or OTG pin) 4 RW OFF STATE, POR, REG_RST NTC_EN 1 ntc pin operation enable: 0 : Battery temperature igniore, 1 : Battery temperature modify the charge profile. 3 RW OFF STATE, POR, REG_RST TJ_WARN_OPT 0 Enable charge current vs Junction temperature 0: No current change versus junction temperature 1: Charge current is reduced when TJ is too high. 2 RW OFF STATE, POR, REG_RST, OTGMODE JEITA_OPT 0 NTC warning operation enable: 0 : Hold the charge when VNTC > VWARM. 1 : Reduced the charge when VNTC > VWARM. 1 RW OFF STATE, POR, REG_RST, TRM_RST TCHG_RST 0 Charge timer reset: 0 : no reset 1 : Reset and resume charge timer(tchg timer) (self clearing) 0 RW OFF STATE, POR, REG_RST INT_MASK 1 global interrupt mask 0 : All Interrupts can be active. 1 : All interrupts are not active http://onsemi.com 23 NCP1852, NCP1852A Table 6. REGISTERS MAP Bit Type Reset Name RST Value Function CTRL2 REGISTER − Memory location : 02 7 RW OFF STATE, POR, REG_RST, OTGMODE WDTO_DIS 0 Disable watchdog timer 0: Watchdog timer enable 1: Watchdog timer disable 6 RW OFF STATE, POR, REG_RST, OTGMODE CHGTO_DIS 0 Disable charge timer 0: Charge timer enable 1: Charge timer disable 5 RW OFF STATE, POR, REG_RST, OTGMODE PWR_PATH 0 Power Path Management: 0: Power Path disable 1: Power Path enable 4 RW OFF STATE, POR, REG_RST TRANS_EN_REG 1 Trans pin operation enable: 0 : Trans pin is still off 1 : Trans pin is supply 3 RW OFF STATE, POR, REG_RST, OTGMODE FCTRY_MOD_REG 0 Factory mode: 0: Factory mode disable 1: Enable factory mode. 2 RW OFF STATE, POR, REG_RST, OTGMODE IINSET_PIN_EN 1 Enable input current set pin: 0: Input current limit and AICL control by I2C 1: Input current limit and AICL control by pins ILIMx 1 RW OFF STATE, POR, REG_RST, OTGMODE IINLIM_EN 1 Enable input current limit: 0: No input current limit 1: Input current limit is IINLIM[3:0] 0 RW OFF STATE, POR, REG_RST, OTGMODE AICL_EN 0 Enable automatic charge current: 0: No AICL 1: AICL STAT_INT REGISTER − Memory location : 03 7−6 R No_Reset RESERVED 5 RCDual OFF STATE, POR, REG_RST TWARN 0 0 : Silicon temperature is below TWARN threshold 1 : Silicon temperature is above TWARN threshold 4 RCDual OFF STATE, POR, REG_RST TM1 0 0 : Silicon temperature is below T1 threshold 1 : Silicon temperature is above T1 threshold 3 RCDual OFF STATE, POR, REG_RST TM2 0 0 : Silicon temperature is below T2 threshold 1 : Silicon temperature is above T2 threshold 2 RCDual OFF STATE, POR, REG_RST TSD 0 0 : Silicon temperature is below TSD threshold 1 : Silicon temperature is above TSD threshold 1 RCDual OFF STATE, REG_RST, POR, OTGMODE CHGEX 0 0: Input voltage is lower than VINEXT 1: charger in extended range, VIN is higher than VINEXT 0 RCDual OFF STATE, REG_RST, POR, OTGMODE VBUSOK 0 0: changer not in USB range 1: charger in USB charging range VBUSUV < VIN < VBUSOV CH1_INT REGISTER − Memory location : 04 7−5 R No_Reset RESERVED 0 4 RCDual OFF STATE, REG_RST, POR, OTGMODE VINLO 0 VIN changer detection interrupt: 1: VIN - VBAT > VCHGDET and VIN < VINDET 3 RCDual OFF STATE, REG_RST, POR, OTGMODE VINHI 0 VIN over voltage lock out interrupt: 1: VIN > VINOV 2 RCDual OFF STATE, REG_RST, POR, OTGMODE BATRMV 0 battery temp out of range interrupt: 1: VNTC > VNTCRMV http://onsemi.com 24 NCP1852, NCP1852A Table 6. REGISTERS MAP Bit Type Reset Name RST Value Function CH1_INT REGISTER − Memory location : 04 1 RCDual OFF STATE, REG_RST, POR, OTGMODE BUCKOVP 0 VBAT over voltage interrupt: 1: VBAT > VOVP 0 R No_Reset CHINT2 0 charger related interrupt (CH2_INT register) CH2_INT REGISTER − Memory location : 05 7 RCDual OFF STATE, REG_RST, POR, OTGMODE NTCHOT 0 Battery Temperature exceeds NTC HOT threshold 6 RCDual OFF STATE, REG_RST, POR, OTGMODE NTCWARM 0 Battery Temperature exceeds NTC WARM threshold 5 RCDual OFF STATE, REG_RST, POR, OTGMODE NTCCHILLY 0 Battery Temperature is lower than NTC CHILLY threshold 4 RCDual OFF STATE, REG_RST, POR, OTGMODE NTCCOLD 0 Battery Temperature is lower than NTC COLD threshold 3 RCSingle OFF STATE, POR, REG_RST, TRM_RST, OTGMODE WDTO 0 watchdog timeout expires interrupt: 1: 32s timer expired. 2 RCSingle OFF STATE, POR, REG_RST, TRM_RST, OTGMODE USBTO 0 usb timeout expires initerrupt: 1: 2048s timer expired 1 RCSingle OFF STATE, POR, REG_RST, TRM_RST, OTGMODE CHGTO 0 charge timeout expires interrupt: 1: 3600s timer expired 0 R No_Reset CHINT1 0 charger related interrupt (CH1_INT register) BST_INT REGISTER − Memory location : 06 7−3 R No_Reset RESERVED 00000 2 RCDual OFF STATE, POR, REG_RST, CHGMODE VBUSILIM 0 vbus overload interrupt: 1: Vbus voltage < VBUSUV 1 RCDual OFF STATE, POR, REG_RST, CHGMODE VBUSOV 0 vbus overvoltage interrupt: 1: Vbus voltage < VBUSOV 0 RCDual OFF STATE, POR, REG_RST, CHGMODE VBATLO 0 vbat overvoltage interrupt: 1: Vbat voltage < VIBSTL VIN_SNS REGISTER − Memory location : 07 7 R No_Reset VINOVLO_SNS 0 VIN over voltage lock out comparator 1: VIN > VINOV 6 R No_Reset CHEXTD7V_SNS 0 VIN extended range comparator 1: VIN > VINEXT 5 R No_Reset VBUSOV_SNS 0 VIN not is USB range comparator 1: VIN > VBUSOV 4 R No_Reset VBUSUV_SNS 0 VIN not is USB range comparator 1: VIN < VBUSUV 3 R No_Reset VINDET_SNS 0 VIN voltage detection comparator 1: VIN > VINDET 2 R No_Reset VCHGDET_SNS 0 VIN changer detection comparator 1: VIN − VBAT > VCHGDET 1 R No_Reset VBOOST_UV_SNS 0 VIN OTG under voltage comparator 1: VIN < VBUSUV http://onsemi.com 25 NCP1852, NCP1852A Table 6. REGISTERS MAP Bit Type Reset Name RST Value RESERVED 0 Function VIN_SNS REGISTER − Memory location : 07 0 R No_Reset VBAT_SNS REGISTER − Memory location : 08 7 R No_Reset NTC_REMOVAL_SNS 0 NTC removal comparator: 1: Battery removal, VNTC > VNTCRMV 6 R No_Reset VBAT_OV_SNS 0 VBAT over voltage comparator 1: VBAT > VOVP 5 R No_Reset VRECHG_OK_SNS 0 VBAT recharge comparator 1: VBAT > VRECHG 4 R No_Reset VFET_OK_SNS 0 VBAT weak charge comparator 1: VBAT > VFET 3 R No_Reset VPRE_OK_SNS 0 VBAT precharge comparator 1: VBAT > VPRE 2 R No_Reset VSAFE_OK_SNS 0 VBAT safe comparator 1: VBAT > VSAFE 1 R No_Reset IEOC_OK_SNS 0 End of charge current comparator 1: ICHARGE > IEOC 0 R No_Reset RESERVED 0 TEMP_SNS REGISTER − Memory location : 09 7 R No_Reset NTC_COLD_SNS 0 NTC cold comparator : 1: VNTC < VCOLD 6 R No_Reset NTC_CHILLY_SNS 0 NTC warm comparator : 1: VNTC > VCHILLY 5 R No_Reset NTC_WARM_SNS 0 NTC hot comparator : 1: VNTC > VHOT 4 R No_Reset NTC_HOT_SNS 0 NTC disable comparator : 1: VNTC > VNTCDIS 3 R No_Reset TSD_SNS 0 Chip thermal shut down comparator 1: Chip Temp > TSD 2 R No_Reset TM2_SNS 0 Chip thermal shut down comparator 1: Chip Temp > tm2 1 R No_Reset TM1_SNS 0 Chip thermal shut down comparator 1: Chip Temp > tm1 0 R No_Reset TWARN 0 Chip thermal shut down comparator 1: Chip Temp > twarn STAT_MSK REGISTER − Memory location : 0A 7 R No_Reset RESERVED 0 6 R No_Reset RESERVED 0 5 RW OFF STATE, POR, REG_RST TWARN_MASK 0 TWARN interruption mask bit. 4 RW OFF STATE, POR, REG_RST TM1_MASK 0 TM1 interruption mask bit. 3 RW OFF STATE, POR, REG_RST TM2_MASK 0 TM2 interruption mask bit. 2 RW OFF STATE, POR, REG_RST TSD_MASK 0 TSD interruption mask bit. 1 R No_Reset RESERVED 0 0 RW OFF STATE, POR, REG_RST, OTGMODE VBUSOK_MASK 0 http://onsemi.com 26 VBUSOK interruption mask bit. NCP1852, NCP1852A Table 6. REGISTERS MAP Bit Type Reset Name RST Value Function CH1_MSK REGISTER − Memory location : 0B 7−5 R No_Reset RESERVED 0 4 RW OFF STATE, POR, REG_RST, OTGMODE VINLO_MASK 0 VINLO interruption mask bit. 3 RW OFF STATE, POR, REG_RST, OTGMODE VINHI_MASK 0 VINHI interruption mask bit. 2 RW OFF STATE, POR, REG_RST, OTGMODE BATRMV_MASK 0 BATRMV interruption mask bit. 1 RW OFF STATE, POR, REG_RST, OTGMODE BUCKOVP_MASK 0 BUCKOVP interruption mask bit. 0 RW OFF STATE, POR, REG_RST, OTGMODE STATECHG_MASK 0 State transition interruption mask bit. CH2_MSK REGISTER − Memory location : 0C 7 RW OFF STATE, POR, REG_RST, OTGMODE NTCHOT_MASK 0 NTCHOT interruption mask bit. 6 RW OFF STATE, POR, REG_RST, OTGMODE NTCWARM_MASK 0 NTCWARM interruption mask bit. 5 RW OFF STATE, POR, REG_RST, OTGMODE NTCCHILLY_MASK 0 NTCCHILLY interruption mask bit. 4 RW OFF STATE, POR, REG_RST, OTGMODE NTCCOLD_MASK 0 NTCCOLD interruption mask bit. 3 RW OFF STATE, POR, REG_RST, OTGMODE WDTO_MASK 1 WDTO interruption mask bit. 2 RW OFF STATE, POR, REG_RST, OTGMODE USBTO_MASK 1 USBTO interruption mask bit. 1 RW OFF STATE, POR, REG_RST, OTGMODE CHGTO_MASK 1 CHGTO interruption mask bit. 0 R No_Reset RESERVED 0 BST_MSK REGISTER − Memory location : 0D 7−4 R No_Reset RESERVED 0 3 RW OFF STATE, POR, REG_RST, OTGMODE VBUSILIM_MASK 1 VBUSILIM interruption mask bit. 2 RW OFF STATE, POR, REG_RST, OTGMODE VBUSOV_MASK 1 VBUSOV interruption mask bit. 1 RW OFF STATE, POR, REG_RST, OTGMODE VBATLO_MASK 1 VBATLO interruption mask bit. 0 RW OFF STATE, POR, REG_RST, OTGMODE STATEOTG_MASK 1 STATEOTG interruption mask bit. VBAT_SET REGISTER − Memory location : 0E 7−6 R No_Reset RESERVED 00 0−5 RW OFF STATE, POR, REG_RST, OTGMODE CTRL_VBAT [5:0] 001100 000000: 3.3 V 001100: 3.6 V 110000: 4.5 V Step: 0.025 V IBAT_SET REGISTER − Memory location : 0F 7 R No_Reset RESERVED 0 6−4 RW OFF STATE, POR, REG_RST, OTGMODE IEOC[2:0] 010 http://onsemi.com 27 000: 100 mA 010: 150 mA 111: 275 mA Step: 25 mA NCP1852, NCP1852A Table 6. REGISTERS MAP Bit Type Reset Name RST Value ICHG[3:0] 0110 Function IBAT_SET REGISTER − Memory location : 0F 3−0 RW OFF STATE, POR, REG_RST, OTGMODE Output range current programmable range: 0000: 400 mA 1110: 1.8 A Step: 100 mA MISC_SET REGISTER − Memory location : 10 7 R No_Reset RESERVED 0 6−5 RW OFF STATE, POR, REG_RST, OTGMODE IWEAK[1:0] 01 Charge current during weak battery states: 00: Disable 01: 100 mA 10: 200 mA 11: 300 mA 4−2 RW OFF STATE, POR, REG_RST, OTGMODE CTRL_VFET[2:0] 011 Battery to system re−conection threshold: 000: 3.1 V 001: 3.2 V 010: 3.3 V 011: 3.4 V 100: 3.5 V 101: 3.6 V 1−0 RW OFF STATE, POR, REG_RST, OTGMODE IINLIM[2:0] 00 Input current limit range: 00: 100 mA 01: 500 mA 10: 900 mA 11: 1500 mA NTC_SET1 REGISTER − Memory location : 11 7−4 R No_Reset RESERVED 000 3−2 RW OFF STATE, POR, REG_RST, OTGMODE VCHRED[1:0] 10 Charge voltage reduction according to battery temperature: 00: 000 mV 01: 100 mV 10: 200 mV 11: 300 mV 1−0 RW OFF STATE, POR, REG_RST, OTGMODE ICHRED[1:0] 00 Charge current reduction according to battery temperature: 00: 400 mA 01: 500 mA 10: 600 mA 11: 700 mA NTC_SET2 REGISTER − Memory location : 12 7−5 RW OFF STATE, POR, REG_RST, OTGMODE BATCOLD[2:0] 101 Cold battery temperature threshold: 101: 1.725 V Step: 0.146 V 4−2 RW OFF STATE, POR, REG_RST, OTGMODE BATHOT[2:0] 011 Hot battery temperature threshold: 011: 0.525 V Step: 0.146 V OFF STATE, POR, REG_RST, OTGMODE BATCHILLY 0 Chilly battery temperature threshold: 0: VCHILLY + 0.146 V 1: VCHILLY + 0.219 V OFF STATE, POR, REG_RST, OTGMODE BATWARM 0 Warm battery temperature threshold: 0: VWARM – 0.146 V 1: VWARM – 0.219 V 1 0 RW http://onsemi.com 28 NCP1852, NCP1852A APPLICATION INFORMATION Components Selection The bandwidth is recommended to be high enough in case of application with a BATFET because the system can be directly connected to the buck output. And in this case, the battery does not play any role upon a load transient as it’s disconnected from the buck converter. USB dedicated charge VIN = 5 V VCHG = 4.2 V ICHG = 1.5 A L1 = 2.2 mH DIL1 = 0.189 A IPEAKMAX = 1.59 A Resistance R1 R1 (charge current sense resistor) resistor is determined by considering thermal constrain as its value is 68 mW typical. The power dissipation is given by: Inductor L1 NCP1852 is recommended to be used with 2.2 mH inductor. Below will give inductor ripple and maximum current for 2 different application cases knowing the following relation: ǒ DI L + V BAT 1* Ǔ V BAT V IN V BAT 2 is maximum V IN The worst case is when V BAT * so when V BAT + DI LMAX + 1 F SWCHG L1 V IN 2 V IN DI 1 @ ;I + I CHG ) LMAX 4 L1 @ F SWCHG PEAKMAX 2 P R1 + R 1 Capacitor C6 A 10 mF output capacitor is recommended for proper operation and design stability. The bandwidth of the system is defined by the following relation: F BW + 1 2p ǸL1 C6 (I CHG) 2 The worst case is ICHG = 1.5 A so PR1 = 0.153 W. + 33 kHz BILL OF MATERIAL IN CIN 1 mF NCP1852 CAP CCAP CBOOT 2.2 mF RSNS 68 mW CSYS CBOOT 10 mF 10 nF SENSP WEAK CORE CCORE FET 2.2 mF QBAT (*) BAT CTRS USB PHY LX SENSN 4.7 mF VBUS D+ D− GND SW TRANS NTC ILIM1 ILIM2 OTG AGND FLAG PGND SPM 0.1 mF SCL SDA Figure 23. NCP1852 Typical Application Example http://onsemi.com 29 + SYSTEM NCP1852, NCP1852A Item Part Description Ref Value PCB Footprint Manufacturer Manufacturer Reference 1 Ceramic Capacitor 25 V X5R CIN 1 mF 0603 MURATA GRM188R61E105K 2 Ceramic Capacitor 25 V X5R CCAP 4.7 mF 0805 MURATA GRM21BR61E475KA12L 3 Ceramic Capacitor 6.3 V X5R CCORE 2.2 mF 0402 MURATA GRM155R60J225M 4 Ceramic Capacitor 6.3 V X5R CTRS 0.1 mF 0402 MURATA GRM155R60J104K 5 Ceramic Capacitor 10 V X5R CBOOT 10 nF 0402 MURATA GRM155R60J103K 6 Ceramic Capacitor 6.3 V X5R COUT 10 mF 0603 MURATA GRM188R60J106M 7 SMD Inductor LX 2.2 mH 2.0 x 2.5 mm CYNTEC PIFE25201T 8 SMD Resistor 0.25 W, 1% RSNS 68 mW 0603 PANASONIC ERJ3BWFR068V 9 Power channel P−MOSFET QBAT 30 mW UDFN 2*2mm ONSEMI NTLUS3A40PZ PCB Layout Consideration The high current charge path through IN, CAP, SW, inductor L1, Resistor R1, optional BAFTET, and battery pack must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. An IWEAK current can flow through WEAK and BAT traces which define the appropriate track width. It’s suggested to keep as complete ground plane under NCP1852 as possible. PGND and AGND pin connection must be connected to the ground plane. Care should be taken to avoid noise interference between PGND and AGND. Finally it is always good practice to keep the sensitive tracks such as feedbacks connections (SENSP, SENSN, BAT) away from switching signal connections by laying the tracks on the other side or inner layer of PCB. Particular attention must be paid with CCORE capacitor as it’s decoupling the supply of internal circuitry including gate driver. This capacitor must be placed between CORE pin and PGND pin with a minimum track length. The high speed operation of the NCP1852 demands careful attention to board layout and component placement. To prevent electromagnetic interference (EMI) problems, attention should be paid specially with components CIN, LX, CCAP, and COUT as they constitute a high frequency current loop area. The power input capacitor CIN, connected from IN to PGND, should be placed as close as possible to the NCP1852. The output inductor LX and the output capacitor COUT connected between RSNS and PGND should be placed close to the IC. CCAP capacitor should also be placed as close as possible to CAP and PGND pin. IN Power path Q1 Q2 CORE CIN 1 mF CCORE 2.2 mF Noise sensitive path SW CAP LX 2.2 mF Q3 CCAP 4.7 mF RSNS 68 mW + 10 mF CSYS NCP1852 PGND Figure 24. NCP1852 Power Path ORDERING INFORMATION Part Number NCP1852FCCT1G NCP1852AFCCT1G Specific Device Code VSYSOV ROBSTOL RNTCPU I2C address 1852 7V 170 W 10 kW $6C 1852A 7V 50 W 10 kW $6C http://onsemi.com 30 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS 25 Pin Flip−Chip, 2.55x2.20 CASE 499BN ISSUE A DATE 26 OCT 2011 SCALE 4:1 PIN A1 REFERENCE D ÈÈ A B A3 A2 DIM A A1 A2 A3 b D E e E 2X 0.10 C 2X 0.10 C DETAIL A TOP VIEW A2 DETAIL A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. GENERIC MARKING DIAGRAM* 0.10 C A XXXXXX AYWW G 0.05 C NOTE 3 A1 25X SEATING PLANE XXXXXX= Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package e b 0.05 C A B 0.03 C C SIDE VIEW E MILLIMETERS MIN MAX 0.60 −−− 0.17 0.23 0.36 REF 0.04 REF 0.24 0.29 2.55 BSC 2.20 BSC 0.40 BSC e D *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. C B A 1 2 3 4 RECOMMENDED SOLDERING FOOTPRINT* 5 BOTTOM VIEW PACKAGE OUTLINE A1 0.40 PITCH 25X 0.40 PITCH 0.25 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON54510E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 25 PIN FLIP−CHIP, 2.55X2.20 PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com ◊ TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative