NCP2811
NOCAPt Advanced Stereo
Headphone Amplifier
NCP2811 is a dual audio power amplifier designed for portable
communication device applications such as mobile phones. This part
is capable of delivering 27 mW of continuous average power into a
16 Ω load from a 2.7 V power supply with a THD+N of 1%.
Based on the power supply delivered to the device, an internal
power management block generates a symmetrical positive and
negative voltage. Thus, the internal amplifiers provide outputs
referenced to Ground. In this True Ground configuration, the two
external heavy coupling capacitors can be removed. It offers
significant space and cost savings compared to a typical stereo
application.
NCP2811 is available with an external adjustable gain (version A),
or with an internal gain of −1.5 V/V (version B). It reaches a superior
−100 dB PSRR and noise floor. Thus, it offers high fidelity audio
sound, as well as a direct connection to the battery. It contains circuitry
to prevent from “Pop & Click” noise that would otherwise occur
during turn−on and turn−off transitions. The device is available in 12
bump CSP package (2 x 1.5 mm) which help to save space on the
board. It is also available in WQFN12 and TSSOP−14 packages.
http://onsemi.com
MARKING
DIAGRAMS
12 PIN CSP
FC SUFFIX
CASE 499AZ
x
= A for NCP2811A
= B for NCP2811B
z
= C for backside laminate
A
= Assembly Location
Y
= Year
WW = Work Week
G
= Pb−Free Package
Features
WQFN12
MT SUFFIX
CASE 510AH
1
• True Ground Configuration Output Eliminates DC−Blocking
•
•
•
•
•
•
•
•
•
•
Capacitors:
− Save Board Area
− Save Component Cost
− No Low−Frequency Response Attenuation
High PSRR (−100 dB): Direct Connection to the Battery
“Pop and Click” Noise Protection Circuitry
Internal Gain (−1.5 V/V) or External Adjustable Gain
Ultra Low Current Shutdown Mode
2.7 V – 5.0 V Operation
Thermal Overload Protection Circuitry
CSP 2 x 1.5 mm
WQFN12 3 x 3 mm
TSSOP−14
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
• Headset Audio Amplifier for
− Cellular Phones
− MP3 Player
− Personal Digital Assistant and Portable Media Player
− Portable Devices
2811xz
AYWW
G
x
A
L
Y
W
G
2811x
ALYWG
G
= A for NCP2811A
= B for NCP2811B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
14
TSSOP−14
DTB SUFFIX
CASE 948G
14
1
2811
x
ALYWG
G
1
x
A
L
Y
W
G
= A for NCP2811A
= B for NCP2811B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
© Semiconductor Components Industries, LLC, 2010
November, 2010 − Rev. 3
1
Publication Order Number:
NCP2811/D
NCP2811
C3
1 mF
C2
PGND
C4
PVM
PVM
B3
INL
SPVM B4
A2
10 OUTL
SD
A4
B2
OUTL
INR
A3
OUTR
OUTR
AGND
10
A version
A1
CPP
CPM
B1 C1
VP
Audio Left
SD
Audio Right
CPM
VP
CPP
1 mF
B1 C1
VP
C3
1 mF
C2
PGND
C4
PVM
PVM
Audio Left B3
INL
SPVM
B4
SD
A2
SD
A4 10 OUTL
OUTL
Audio Right B2
INR
OUTR
A3
OUTR
AGND
10
A1
B version
CPP
CPM
VP
1 mF
CPM
1 mF
CPP
1 mF
Figure 1. Application Schematics
VP
OUTL
OUTR
WQFN12
12 PIN CSP
A2
AGND
SD
A3
A4
OUTR OUTL
B1
B2
B3
B4
VP
INR
INL
SPVM
C1
C2
C3
C4
CPP
PGND CPM
(Top View)
PVM
CPP
PGND
CPM
NC
INR
AGND
PVM
SD
INL
A1
TSSOP14
(Top View)
Figure 2. Pin Configurations
http://onsemi.com
2
OUTL
OUTR
NC
INR
AGND
INL
NC
NC
VP
CPP
PGND
CPM
PVM
SD
(Top View)
NCP2811
1 mF
VP
Cs
1 mF
VP
CPM
CPP
VRP
PGND
PVM
POWER MANAGEMENT
1 mF
SPVM
VRM
Left
Audio
VRP
INL
−
OUTL
+
VRM
SD
BIASING
Use 10 ohm
resistor for
capacitive drive
capability
CLICK/POP
SUPPRESSION
VRP
+
Right
Audio
OUTR
INR
−
VRM
AGND
Figure 3. Typical Application Schematic version A
http://onsemi.com
3
NCP2811
VP
1 mF
Cs
1 mF
CPP
VP
CPM
VRP
PGND
1 mF
PVM
POWER MANAGEMENT
VRM
Left
Audio
VRP
INL
−
OUTL
+
VRM
SD
BIASING
Use 10 ohm resistor
for capacitive
drive capability
CLICK/POP
SUPPRESSION
VRP
+
Right
Audio
INR
OUTR
−
VRM
AGND
Figure 4. Typical Application Schematic version B
Table 1. PIN FUNCTION DESCRIPTION
PIN
CSP
PIN
TQFN
PIN TSSOP
PIN
NAME
TYPE
A1
7
10
AGND
GROUND
A2
5
7
SD
INPUT
A3
10
13
OUTR
OUTPUT
Right audio channel output signal
A4
11
14
OUTL
OUTPUT
Left audio channel output signal
B1
12
2
VP
POWER
Positive supply voltage. It can be connected for example to a Lithium/Ion
battery
B2
8
11
INR
INPUT
Right input of the first audio source
B3
6
9
INL
INPUT
Left input of the first audio source
B4
−
−
SPVM
POWER
Amplifier negative power supply voltage. Connect to PVM
C1
1
3
CPP
INPUT/
OUTPUT
Charge pump flying capacitor positive terminal. A 1 mF ceramic filtering
capacitor to CPM is needed
C2
2
4
PGND
GROUND
Power ground, connect to ground reference
C3
3
5
CPM
INPUT
C4
4
6
PVM
OUTPUT
DESCRIPTION
Analog ground. Connect to ground reference
Enable activation
Charge pump flying capacitor negative terminal. A 1 mF ceramic filtering
capacitor to CPP is needed
Charge pump output. A 1 mF ceramic filtering capacitor to ground is
needed
http://onsemi.com
4
NCP2811
Table 2. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
AVIN, PVIN Pins: Power Supply Voltage (Note 2)
VP
− 0.3 to + 6.0
V
INL, INR Pins: Input (Note 2)
A version
B version
VIN
V
−VP – 0.3 to VP + 0.3
−2 to +2
VYY
−0.3 to VP + 0.3
V
Human Body Model (HBM) ESD Rating are (Note 3)
SD Pin: Input (Note 2)
ESD HBM
2000
V
Machine Model (MM) ESD Rating are (Note 3)
ESD MM
200
V
RqJC
(Note 7)
°C/W
Operating Ambient Temperature Range
TA
−40 to + 85
°C
Operating Junction Temperature Range
TJ
−40 to + 125
°C
Maximum Junction Temperature (Note 6)
TJMAX
+ 150
°C
Storage Temperature Range
TSTG
−65 to + 150
°C
Moisture Sensitivity (Note 5)
MSL
Level 1
CSP 1.5 x 2.0 mm package (Notes 6 and 7)
Thermal Resistance Junction to Case
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Notes:
1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = 25°C.
2. According to JEDEC standard JESD22−A108B.
3. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) ±200 V per JEDEC standard: JESD22−A115 for all pins.
4. Latch up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78 class II.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
6. The thermal shutdown set to 150°C (typical) avoids irreversible damage on the device due to power dissipation.
7. The RJA is highly dependent of the PCB Heatsink area. For example, RJA can equal 195°C/W with 50 mm2 total area and also 135°C/W with
50 mm2. The bumps have the same thermal resistance and all need to be connected to optimize the power dissipation.
R qCA +
125 * T A
* R qJC
PD
http://onsemi.com
5
NCP2811
Table 3. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for VIN
between 2.7 V to 5.0 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and VIN = 3.6 V.
Parameter
Symbol
Conditions
VP
Operational Power Supply
IDD
Supply quiescent current
Both channels enabled
ISD
Shutdown current
VP = 2.7 V to 5.0 V
VOS
Output offset voltage
VP = 2.7 V to 5.0 V
VIH
High−Level input voltage SD pin
VIL
Low−Level input voltage SD pin
RSD
SD pin pull−down impedance
TWU
Turning on time
TSD
Thermal shutdown temperature
VLP
Max output swing (peak value)
VP = 2.9 V to 5.0 V
Headset ≥ 16 W
THD+N = 1%
PO
Max output power (output in phase)
VP = 2.7V, THD+N = 1%
Headset = 16 W
VP = 2.7V, THD+N = 1%
Headset = 32 W
VP = 3.6V, THD+N = 1%
Headset = 16 W
VP = 3.6V, THD+N = 1%
Headset = 32 W
VP = 5.0V, THD+N = 1%
Headset = 16 W
VP = 5.0V, THD+N = 1%
Headset = 32 W
PSRR
THD+N
VP = 2.7 V to 5.0 V
Input shorted to ground
F = 217 Hz
F = 1 kHz
Total harmonic distortion + noise (Note 8)
Headset = 16 W
POUT = 25 mW
VN
Output noise voltage (Note 8)
ZIN
Input impedance
ZSD
Output impedance in shutdown mode
UVLO hysteresis
Av
Unit
5.0
V
6.0
mA
1
V
KW
1
ms
160
°C
VRMS
27
mW
37
90
64
110
64
−80
−60
dB
dB
−106
−95
0.01
%
A−Weighting filter
7
mVRMS
B version only
20
KW
10
KW
2.3
V
100
mV
B version only
8. Guaranteed by design and characterized.
http://onsemi.com
6
V
190
1
Falling edge
Voltage Gain
mA
mV
±1
0.4
Power supply rejection ratio (Note 8)
UVLOHYST
Max
1.2
Headset ≥ 16 W
UVLO threshold
Typ
2.7
Crosstalk (Note 8)
UVLO
Min
−1.53
−1.5
−1.48
V/V
NCP2811
TYPICAL OPERATING CHARACTERISTICS
100
100
16 W out of Phase
16 W in Phase
10
THD+N (%)
THD+N (%)
10
1
0.1
THD+N_L (%)
THD+N_R (%)
0.01
1
0.1
THD+N_L (%)
0.01
THD+N_R (%)
0.001
0
100
20
40
60
80
100
120
140
0.001
160
20
40
60
80
100
120
140
160 180
Pout (mW)
Pout (mW)
Figure 5. THD+N vs. Pout @ Vp = 3.6 V
Figure 6. THD+N vs. Pout @ Vp = 3.6 V
100
16 W in Phase
2.7 V
10
0
16 W out of Phase
2.7 V
10
3.0 V
0.1
THD (%)
3.6 V
1
4.2 V
Vp = 5 V
0.01
0.001
0
100
20
40
60
100
120
Vp = 5 V
140
160
0.001
180
0
20
40
60
80
100
120
140
Pout (mW)
Figure 7. THD+N vs. Pout LEFT
Figure 8. THD+N vs. Pout RIGHT
160 180
100
16 W out of Phase
16 W out of Phase
2.7 V
2.7 V
10
3.0 V
3.6 V
4.2 V
Vp = 5 V
1
0.1
3.0 V
3.6 V
1
4.2 V
Vp = 5 V
0.1
0.01
0.01
0.001
4.2 V
0.1
Pout (mW)
10
THD (%)
80
3.6 V
1
0.01
THD (%)
THD (%)
3.0 V
0
20
40
60
80
100
120
140
160
0.001
180
0
20
40
60
80
100
120
140
Pout (mW)
Pout (mW)
Figure 9. THD+N vs. Pout LEFT
Figure 10. THD+N vs. Pout RIGHT
http://onsemi.com
7
160 180
NCP2811
TYPICAL OPERATING CHARACTERISTICS
100
100
32 W in Phase
10
THD+N_L (%)
THD+N (%)
THD+N (%)
10
1
THD+N_R (%)
0.1
0
100
10
20
30
40
50
60
70
90
80
0.001
100
0
30
40
50
60
70
80
90 100
Figure 12. THD+N vs. Pout @ Vp = 3.6 V
100
32 W in Phase
32 W in Phase
2.7 V
2.7 V
10
3.0 V
3.6 V
4.2 V
Vp = 5 V
0.1
3.0 V
3.6 V
4.2 V
1
Vp = 5 V
0.1
0.01
0.01
0
10
20
30
40
50
60
70
80
90
0.001
100
0
10
20
30
40
50
60
70
80
Pout (mW)
Pout (mW)
Figure 13. THD+N vs. Pout LEFT
Figure 14. THD+N vs. Pout RIGHT
90 100
100
100
32 W out of Phase
32 W out of Phase
10
10
2.7 V
3.0 V
3.6 V
1
THD (%)
THD (%)
20
Figure 11. THD+N vs. Pout @ Vp = 3.6 V
1
4.2 V
0.1
Vp = 5 V
2.7 V
3.0 V
1
3.6 V
4.2 V
0.1
Vp = 5 V
0.01
0.01
0.001
10
Pout (mW)
THD (%)
THD (%)
THD+N_R (%)
0.1
Pout (mW)
10
0.001
THD+N_L (%)
1
0.01
0.01
0.001
32 W out of Phase
0
10
20
30
40
50
60
70
80
90
0.001
100
0
10
20
30
40
50
60
70
80
Pout (mW)
Pout (mW)
Figure 15. THD+N vs. Pout LEFT
Figure 16. THD+N vs. Pout RIGHT
http://onsemi.com
8
90 100
NCP2811
TYPICAL OPERATING CHARACTERISTICS
1
1
0.1
16 W out of Phase
VP = 3.6 V
VP = 5.0 V
0.01
THD+N (%)
THD+N (%)
16 W out of Phase
VP = 2.7 V
0.1
VP = 3.6 V
0.01
VP = 2.7 V
VP = 5.0 V
0.001
10
100
1,000
10,000
0.001
100,000
10
100
1,000
FREQUENCY (Hz)
Figure 17. THD vs. Frequency LEFT
@ Pout = 32 mW
Figure 18. THD vs. Frequency RIGHT
@ Pout = 32 mW
1
32 W out of Phase
32 W out of Phase
VP = 2.7 V
VP = 3.6 V
0.1
VP = 5.0 V
THD+N (%)
THD+N (%)
VP = 2.7 V
0.01
10
100
1,000
10,000
VP = 5.0 V
0.01
10
100
10,000
100,000
FREQUENCY (Hz)
Figure 19. THD vs. Frequency LEFT
@ Pout = 32 mW
Figure 20. THD vs. Frequency RIGHT
@ Pout = 32 mW
80
85°C
70
25°C
25°C
60
100
1,000
FREQUENCY (Hz)
120
85°C
50
80
(mW)
(mW)
VP = 3.6 V
0.1
0.001
100,000
140
−40°C
60
−40°C
40
30
40
20
20
0
100,000
FREQUENCY (Hz)
1
0.001
10,000
10
2.7
3.2
3.7
4.2
0
4.7
2.7
3.2
3.7
4.2
4.7
VP (V)
VP (V)
Figure 21. Maximum Output Power LEFT vs.
VP (THD+N < 1%)
Figure 22. Maximum Output Power LEFT vs.
VP (THD+N < 0.1%)
http://onsemi.com
9
NCP2811
TYPICAL OPERATING CHARACTERISTICS
0
−60
−65
−20
−70
(dB)
PSRR (dB)
−75
−40
−60
Left to Right
−90
−95
−100
−80
NCP2811B Left
−100
−120
−80
−85
NCP2811B Right
10
100
1000
10,000
100,000
−105
−110
−115
−120
Right to Left
10
100
1000
10,000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 23. PSRR at Vp = 3.6 V
Figure 24. Crosstalk vs. Frequency
@ Vp = 3.6 V
http://onsemi.com
10
100,000
NCP2811
DETAIL OPERATING DESCRIPTION
Detailed Descriptions
filter with Rin (externally selectable for A version, 20 kW for
B version).
The size of the capacitor must be large enough to couple
in low frequencies without severe attenuation in the audio
bandwith (20 Hz – 20 kHz).
The cut off frequency for the input high−pass filter is:
The NCP2811 is a stereo headphone amplifier with a true
ground architecture. This architecture eliminates the need to
use 2 external big capacitors required by conventional
headphone amplifier.
The structure of the NCP2811 is basically composed of 2
true ground amplifiers, an UVLO, a short circuit protection
and also a thermal shutdown. A special circuitry is
embedded to eliminate any pop and click noise that occurs
during turn on and turn off time. The A version has an
external gain selectable by two resistor, B version has a gain
of 1.5 V/V.
Fc +
A Fc < 20 Hz is recommended.
Charge Pump Capacitor Selection
Use ceramic capacitor with low ESR for better
performances. X5R / X7R capacitor is recommended.
The flying capacitor (C2) serves to transfer charge during
the generation of the negative voltage.
The CPVM capacitor (C3) must be equal at least to the
CFly capacitor to allow maximum transfer charge. The
CPVM value must not exceed 1 mF. Higher capacitor value
can damage the part.
Table 4 suggests typical value and manufacturer:
NOCAPt
NOCAPt is a patented architecture which requires only
2 small ceramic capacitors. It generates a symmetrical
positive and negative voltage and it allows the output of the
amplifiers to be biased around the ground.
Current Limit Protection Circuit
The NCP2811 embed a protection circuitry against short
to ground. When an output is shorted to GND and when a
signal appears at the input, the current is limited to 300 mA.
Table 4.
Thermal Overload Protection
Internal amplifiers are switched off when the temperature
exceed 160°C, and will be switch on again when the
temperature decrease below 140°C.
Value
Reference
Package
Manufacturer
1 mF
C1005X5R0J105K
0402
TDK
1 mF
GRM155R60J105K19
0402
Murata
Lower value of capacitors can be used but the maximum
output power is reduced and the device may not operate to
specifications.
Under Voltage Lockout
When the battery voltage decreases below 2.3 V, the
amplifiers are turned off. The hysteresis to turn on it again
is 100 mV.
Power Supply Decoupling Capacitor (C1)
The NCP2811 is a True Ground amplifier which requires
the adequate decoupling capacitor to reduce noise and
THD+N. Use X5R / X7R ceramic capacitor and place it
closed to the CPVDD pin. A value of 1 mF is recommended.
Pop and Click Suppression Circuitry
The NCP2811 includes a special circuitry to eliminate any
pop and click noise during turn on and turn off time. Basic
amplifier creates an offset during these transitions at the
output which give a parasitic noise called “pop and click
noise”. The NCP2811 eliminates this problem.
Shutdown Function
The device enters in shutdown mode when shutdown signal
is low. During the shutdown mode, the DC quiescent current
of the circuit does not exceed 500 nA. In this configuration,
the output impedance is 10 kW on each output.
Gain Setting Resistor Selection (Rin & Rf, A version
only)
Rin and Rf set the closed loop gain of the amplifier. A low
gain configuration (close to 1) minimizes the THD + noise
values and maximizes the signal to noise ratio.
A closed loop gain in the range of 1 to 10 is recommended
to optimize overall system performance.
The formula to calculate the gain is:
Av + *
1
2pR inC in
Output Resistor for Capacitive Drive Capability
Under normal operation, NCP2811 maximum direct
capacitive load is in the 80 pF range. If, for any reason, high
value capacitive loads should be connected to NCP2811
outputs, an additional 10 W resistor should be placed
between the NCP2811 output and the capacitive load to
ensure amplifier stability.
Rf
R in
Layout Recommendation
Connect C1 as close as possible of the Vp pin.
Connect C2 and C3 as close as possible of the NCP2811.
Route audio signal and AGND far from Vp, CPP, CPM,
PVM and PGND to avoid any perturbation due to the
switching.
Input Capacitor Selection
The input coupling capacitor blocks the DC voltage at the
amplifier input terminal. This capacitor creates a high−pass
http://onsemi.com
11
NCP2811
Table 5. ORDERING INFORMATION
Device
Package
Shipping†
NCP2811ADTBR2G
TSSOP−14
(Pb−Free)
2500/Tape & Reel
NCP2811BDTBR2G
TSSOP−14
(Pb−Free)
2500/Tape & Reel
NCP2811AFCT1G
Flip−Chip 12
(Pb−Free)
3000/Tape & Reel
NCP2811BFCT1G
Flip−Chip 12
(Pb−Free)
3000/Tape & Reel
NCP2811BFCCT1G
Flip−Chip 12
(Backside Laminate Coating)
(Pb−Free)
3000/Tape & Reel
NCP2811AMTTXG
WQFN12
(Pb−Fre)
3000/Tape & Reel
NCP2811BMTTXG
WQFN12
(Pb−Free)
3000/Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP12 2.00x1.50x0.596
CASE 499AZ
ISSUE A
DATE 03 JUN 2022
GENERIC
MARKING DIAGRAM*
XXXXXX
AYWW
G
XXXX
A
Y
WW
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON30285E
WLCSP12 2.00x1.50x0.596
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WQFN12 3x3, 0.5P
CASE 510AH−01
ISSUE O
DATE 20 JAN 2009
1
SCALE 4:1
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
A
D
PIN ONE
REFERENCE
2X
0.10 C
2X
L
B
L1
DETAIL A
ALTERNATE
CONSTRUCTIONS
E
ÎÎÎ
ÏÏ
ÏÏÏ ÏÏ
ÎÎ
EXPOSED Cu
0.10 C
TOP VIEW
DETAIL B
A3
0.10 C
A1
NOTE 4
C
SIDE VIEW
ALTERNATE
CONSTRUCTIONS
SEATING
PLANE
D2
DETAIL A
12X
4
L
7
E2
12X
b
0.10 C A B
1
0.05 C
K
MOLD CMPD
A1
A
DETAIL B
0.10 C
13X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
NOTE 3
12
e
A3
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MILLIMETERS
MIN
MAX
0.65
0.85
0.00
0.05
0.22 REF
0.20
0.30
3.00 BSC
1.30
1.50
3.00 BSC
1.30
1.50
0.50 BSC
0.20
−−−
0.30
0.50
0.00
0.15
GENERIC
MARKING DIAGRAM*
XXXXX
XXXXX
ALYWG
G
XXXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”,
may or may not be present.
BOTTOM VIEW
SOLDERING FOOTPRINT*
12X
0.63
PACKAGE
OUTLINE
1
2X
2X
1.50 3.30
12X
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
98AON38317E
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
STATUS: ON SEMICONDUCTOR STANDARD
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
NEW STANDARD:
© Semiconductor Components Industries, LLC, 2002
Case Outline Number:
http://onsemi.com
WQFN12, 3X3, 0.5P
DESCRIPTION:
October, 2002
− Rev. 0
PAGE 1 OFXXX
2
1
DOCUMENT NUMBER:
98AON38317E
PAGE 2 OF 2
ISSUE
O
REVISION
RELEASED FOR PRODUCTION. REQ. BY J. SAMUDIO.
DATE
20 JAN 2009
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
© Semiconductor Components Industries, LLC, 2009
January, 2009 − Rev. 01O
Case Outline Number:
510AH
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
DETAIL E
K
A
−V−
K1
J J1
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
G
D
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
DOCUMENT NUMBER:
98ASH70246A
DESCRIPTION:
TSSOP−14 WB
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
onsemi Website: www.onsemi.com
◊
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
工商网监
湘ICP备2023018690号
