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NCP3020AGEVB

NCP3020AGEVB

  • 厂商:

    ONSEMI(安森美)

  • 封装:

    -

  • 描述:

    BOARD EVAL NCP3020A BUCK CTLR

  • 数据手册
  • 价格&库存
NCP3020AGEVB 数据手册
NCP3020A, NCP3020B, NCV3020A, NCV3020B Synchronous Buck Controller, 28 V The NCP3020 is a PWM device designed to operate from a wide input range and is capable of producing an output voltage as low as 0.6 V. The NCP3020 provides integrated gate drivers and an internally set 300 kHz (NCP3020A) or 600 kHz (NCP3020B) oscillator. The NCP3020 also has an externally compensated transconductance error amplifier with an internally fixed soft−start. Protection features include lossless current limit and short circuit protection, output overvoltage protection, output undervoltage protection, and input undervoltage lockout. The NCP3020 is currently available in a SOIC −8 package. www.onsemi.com 8 1 SOIC−8 NB CASE 751 MARKING DIAGRAM Features • • • • • • • • • • 8 3020x ALYW G Input Voltage Range from 4.7 V to 28 V 300 kHz Operation (NCP3020B – 600 kHz) 0.6 V Internal Reference Voltage Internally Programmed 6.8 ms Soft−Start (NCP3020B – 4.4 ms) Current Limit and Short Circuit Protection Transconductance Amplifier with External Compensation Input Undervoltage Lockout Output Overvoltage and Undervoltage Detection NCV Prefix for Automotive and Other Applications Requiring Site and Change Controls This is a Pb−Free Device 1 3020x A L Y W G = Specific Device Code x = A or B = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS BST VCC COMP VIN HSDR FB GND CIN VSW LSDR CBST VCC BST CC1 Vout VSW FB CC2 Device L0 COMP RC ORDERING INFORMATION Q1 HSDR GND RFB1 Q2 LSDR RFB2 RISET Figure 1. Typical Application Circuit © Semiconductor Components Industries, LLC, 2013 December, 2018 − Rev. 7 Package Shipping† NCP3020ADR2G SOIC−8 2500 / Tape & Reel (Pb−Free) NCP3020BDR2G SOIC−8 2500 / Tape & Reel (Pb−Free) NCV3020ADR2G SOIC−8 2500 / Tape & Reel (Pb−Free) NCV3020BDR2G SOIC−8 2500 / Tape & Reel (Pb−Free) C0 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1 Publication Order Number: NCP3020/D NCP3020A, NCP3020B, NCV3020A, NCV3020B VCC INTERNAL BIAS BST POR/STARTUP VC THERMAL SD BOOST CLAMP CLK/ DMAX/ SOFT START OSCILLATOR GATE DRIVE LOGIC RAMP 1.5 V LEVEL SHIFT HSDR VCC VSW CURRENT LIMIT SAMPLE & HOLD ISET + − COMP REF OTA VC LSDR PWM COMP FB + − + − BST_CHRG OOV OUV GND Figure 2. NCP3020 Block Diagram PIN FUNCTION DESCRIPTION Pin Pin Name Description 1 VCC The VCC pin is the main voltage supply input. It is also used in conjunction with the VSW pin to sense current in the high side MOSFET. 2 COMP The COMP pin connects to the output of the Operational Transconductance Amplifier (OTA) and the positive terminal of the PWM comparator. This pin is used in conjunction with the FB pin to compensate the voltage mode control feedback loop. 3 FB 4 GND Ground Pin 5 LSDR The LSDR pin is connected to the output of the low side driver which connects to the gate of the low side N−FET. It is also used to set the threshold of the current limit circuit (ISET) by connecting a resistor from LSDR to GND. 6 VSW The VSW pin is the return path for the high side driver. It is also used in conjunction with the VCC pin to sense current in the high side MOSFET. 7 HSDR The HSDR pin is connected to the output of the high side driver which connects to the gate of the high side N−FET. 8 BST The BST pin is the supply rail for the gate drivers. A capacitor must be connected between this pin and the VSW pin. The FB pin is connected to the inverting input of the OTA. This pin is used in conjunction with the COMP pin to compensate the voltage mode control feedback loop. www.onsemi.com 2 NCP3020A, NCP3020B, NCV3020A, NCV3020B ABSOLUTE MAXIMUM RATINGS (measured vs. GND pin 8, unless otherwise noted) Rating High Side Drive Boost Pin Boost to VSW differential voltage COMP Feedback Symbol VMAX VMIN Unit BST 45 −0.3 V BST−VSW 13.2 −0.3 V COMP 5.5 −0.3 V FB 5.5 −0.3 V High−Side Driver Output HSDR 40 −0.3 V Low−Side Driver Output LSDR 13.2 −0.3 V Main Supply Voltage Input VCC 40 −0.3 V Switch Node Voltage VSW 40 −0.6 V Maximum Average Current VCC, BST, HSDRV, LSDRV, VSW, GND Imax Operating Junction Temperature Range (Note 1) TJ −40 to +140 °C TJ(MAX) +150 °C Storage Temperature Range Tstg −55 to +150 °C Thermal Characteristics (Note 2) SOIC−8 Plastic Package Thermal Resistance Junction−to−Air RqJA 165 °C/W RF 260 Peak °C Maximum Junction Temperature Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free (Note 3) 130 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The maximum package power dissipation limit must not be exceeded. PD + T J(max) * T A R qJA 2. When mounted on minimum recommended FR−4 or G−10 board 3. 60−180 seconds minimum above 237°C. www.onsemi.com 3 NCP3020A, NCP3020B, NCV3020A, NCV3020B ELECTRICAL CHARACTERISTICS (−40°C < TJ < +125°C, VCC = 12 V, for min/max values unless otherwise noted) Characteristic Max Unit 28 V 5.5 8.0 mA − 7.0 11 mA VFB = 0.55 V, Switching, VCC = 4.7 V − 5.9 10 mA VFB = 0.55 V, Switching, VCC = 28 V − 7.8 13 mA UVLO Rising Threshold VCC Rising Edge 4.0 4.3 4.7 V UVLO Falling Threshold VCC Falling Edge 3.5 3.9 4.3 V Input Voltage Range Conditions Min − 4.7 VFB = 0.55 V, Switching, VCC = 4.7 V − VFB = 0.55 V, Switching, VCC = 28 V Typ SUPPLY CURRENT VCC Supply Current VCC Supply Current NCP3020A NCP3020B UNDER VOLTAGE LOCKOUT OSCILLATOR Oscillator Frequency Oscillator Frequency NCP3020A NCP3020B Ramp−Amplitude Voltage TJ = +25°C, 4.7 V v VCC v 28 V 250 300 350 kHz TJ = −40°C to +125°C, 4.7 V v VCC v 28 V 240 300 360 kHz TJ = +25°C, 4.7 V v VCC v 28 V 550 600 650 kHz TJ = −40°C to +125°C, 4.7 V v VCC v 28 V 530 600 670 kHz Vpeak − Valley (Note 4) − 1.5 − V 0.46 0.70 0.88 V Ramp Valley Voltage PWM (Note 4) Minimum Duty Cycle Maximum Duty Cycle NCP3020A NCP3020B Soft Start Ramp Time NCP3020A NCP3020B VFB = VCOMP − 7.0 − % 80 75 84 80 − − % − − 6.8 4.4 − − ms 0.9 1.4 1.9 mS ERROR AMPLIFIER (GM) Transconductance Open Loop dc Gain (Notes 4 and 6) − 70 − dB Output Source Current VFB = 545 mV 45 75 100 mA Output Sink Current VFB = 655 mV 45 75 100 mA − 0.5 500 nA TJ = 25°C 4.7 V < VCC < VIN < 28 V, −40°C < TJ < +125°C 0.591 0.588 0.6 0.6 0.609 0.612 V V COMP High Voltage VFB = 0.55 V 4.0 4.4 5.0 V COMP Low Voltage VFB = 0.65 V − 72 250 mV Feedback OOV Threshold 0.66 0.75 0.84 V Feedback OUV Threshold 0.42 0.45 0.48 V FB Input Bias Current Feedback Voltage OUTPUT VOLTAGE FAULTS OVERCURRENT ISET Source Current Current Limit Set Voltage (Note 5) 4. 5. 6. 7. TJ = 25°C, RSET = 22.5 kW 7.0 13 18 mA 140 240 360 mV Guaranteed by design. The voltage sensed across the high side MOSFET during conduction. This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal Ro of > 10 MW. This is not a protection feature. www.onsemi.com 4 NCP3020A, NCP3020B, NCV3020A, NCV3020B ELECTRICAL CHARACTERISTICS (−40°C < TJ < +125°C, VCC = 12 V, for min/max values unless otherwise noted) Characteristic Conditions Min Typ Max Unit HSDRV Pullup Resistance TJ = 25°C, VCC = 8 V, VBST = 7.5 V, VSW = GND 100 mA out of HSDR pin 5.0 11 20 W HSDRV Pulldown Resistance TJ = 25°C, VCC = 8 V, VBST = 7.5 V, VSW = GND 100 mA into HSDR pin 2.0 5.0 11.5 W LSDRV Pullup Resistance TJ = 25°C, VCC = 8 V, VBST = 7.5 V, VSW = GND 100 mA out of LSDR pin 5.0 9.0 16 W LSDRV Pulldown Resistance TJ = 25°C, VCC = 8 V, VBST = 7.5 V, VSW = GND 100 mA into LSDR pin 1.0 3.0 6.0 W HSDRV Falling to LSDRV Rising Delay VIN = 12 V, VSW = GND, VCOMP = 1.3 V 50 80 110 ns LSDRV Falling to HSDRV Rising Delay VIN = 12 V, VSW = GND, VCOMP = 1.3 V 60 80 120 ns Boost Clamp Voltage VIN = 12 V, VSW = GND, VCOMP = 1.3 V 5.5 7.5 9.6 V Thermal Shutdown (Notes 4 and 7) − 165 − °C Hysteresis (Notes 4 and 7) − 20 − °C GATE DRIVERS AND BOOST CLAMP THERMAL SHUTDOWN 4. 5. 6. 7. Guaranteed by design. The voltage sensed across the high side MOSFET during conduction. This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal Ro of > 10 MW. This is not a protection feature. www.onsemi.com 5 NCP3020A, NCP3020B, NCV3020A, NCV3020B TYPICAL PERFORMANCE CHARACTERISTICS 3.28 95 9V 3.275 85 12 V 18 V 3.27 15 V 80 75 9V 3.265 3.26 70 65 60 15 V 18 V Vout (V) EFFICIENCY (%) 90 3.255 Typical Application Circuit Figure 37 0 2 4 8 6 12 V 3.25 10 Typical Application Circuit Figure 37 0 2 4 Iout (A) 8 6 10 Iout (A) Figure 3. Efficiency vs. Output Current and Input Voltage Figure 4. Load Regulation vs. Input Voltage Input = 9 V, Output = 3.3 V, Load = 10 A C4 (Green) = VIN, C2 (Red) = VOUT C1 (Yellow) = VSW, C3 (Blue) = HSDR Input = 18 V, Output = 3.3 V, Load = 10 A C4 (Green) = VIN, C2 (Red) = VOUT C1 (Yellow) = VSW, C3 (Blue) = HSDR Figure 5. Switching Waveforms (VIN = 9 V) Figure 6. Switching Waveforms (VIN = 18 V) 606 340 NCP3020A 330 604 320 VCC = 12 V, 28 V fSW (kHz) VFB (mV) 602 600 598 VCC = 5 V VCC = 12 V, 28 V 300 VCC = 5 V 290 280 596 594 −40 −25 −10 310 270 5 20 35 50 65 80 260 −40 −25 −10 95 110 125 TEMPERATURE (°C) 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 7. Feedback Reference Voltage vs. Input Voltage and Temperature Figure 8. Switching Frequency vs. Input Voltage and Temperature (NCP3020A) www.onsemi.com 6 NCP3020A, NCP3020B, NCV3020A, NCV3020B TYPICAL PERFORMANCE CHARACTERISTICS 1.50 660 1.45 NCP3020B 640 1.40 gm (mS) fSW (kHz) VCC = 5 V 1.35 620 VCC = 12 V, 28 V 600 VCC = 5 V 580 1.30 VCC = 12 V, 28 V 1.25 1.20 1.15 1.10 560 1.05 540 −40 −25 −10 5 20 35 50 65 80 1.00 −40 −25 −10 95 110 125 5 TEMPERATURE (°C) Figure 9. Switching Frequency vs. Input Voltage and Temperature (NCP3020B) 50 65 95 110 125 80 800 THRESHOLD VOLTAGE (mV) 4.3 UVLO Rising 4.2 UVLO (V) 35 Figure 10. Transconductance vs. Input Voltage and Temperature 4.4 4.1 4.0 3.9 UVLO Falling 3.8 −40 −25 −10 5 20 35 50 65 80 760 720 640 600 560 520 480 OUV, VCC = 5 − 28 V 440 400 −40 −25 −10 95 110 125 OOV, VCC = 5 − 28 V 680 5 TEMPERATURE (°C) 9.0 7.0 8.5 ICC, SWITCHING (mA) VCC = 28 V 6.0 VCC = 12 V 5.5 VCC = 5 V 5.0 4.5 4.0 −40 −25 −10 20 35 50 65 50 65 80 95 110 125 80 VCC = 28 V 8.0 7.5 7.0 VCC = 4.7 V 6.5 6.0 5.5 NCP3020A 5 35 Figure 12. Output Overvoltage and Undervoltage vs. Input Voltage and Temperature 7.5 6.5 20 TEMPERATURE (°C) Figure 11. Input Undervoltage Lockout vs. Temperature ICC, SWITCHING (mA) 20 TEMPERATURE (°C) 5.0 −40 −25 −10 95 110 125 TEMPERATURE (°C) NCP3020B 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Figure 13. Supply Current vs. Input Voltage and Temperature (NCP3020A) Figure 14. Supply Current vs. Input Voltage and Temperature (NCP3020B) www.onsemi.com 7 NCP3020A, NCP3020B, NCV3020A, NCV3020B TYPICAL PERFORMANCE CHARACTERISTICS 7.5 750 700 650 NCP3020A tSoft−Start (ms) 900 850 800 VALLEY VOLTAGE (mV) 8.0 VCC = 5 − 28 V 600 550 500 450 400 −40 −25 −10 5 20 35 50 65 80 7.0 6.5 NCP3020A VCC = 5 V 7.0 6.0 VCC = 12 V, 28 V 6.5 5.5 6.0 5.0 NCP3020B VCC = 5 V 5.5 5.0 95 110 125 −40 −25 −10 TEMPERATURE (°C) 4.5 VCC = 12 V, 28 V 5 20 35 50 65 80 4.0 95 110 125 TEMPERATURE (°C) Figure 15. Ramp Valley Voltage vs. Input Voltage and Temperature Figure 16. Soft−Start Time vs. Input Voltage and Temperature 14 ISET (mA) 13.8 13.6 VCC = 12 V, 28 V 13.4 VCC = 5 V 13.2 13 −40 −25 −10 5 20 35 50 65 80 Input = 12 V, Output = 3.3 V, Load = 5 A C1 (Yellow) = VIN, C4 (Green) = VOUT C2 (Red) = HSDR, C3 (Blue) = LSDR 95 110 125 TEMPERATURE (°C) Figure 18. Soft−Start Waveforms Figure 17. Current Limit Set Current vs. Temperature Input = 12 V C1 (Yellow) = FB, C3 (Blue) = LSDR C2 (Red) = HSDR, C4 (Green) = VIN Input = 12 V, Output = 3.3 V, Load = 5 A C1 (Yellow) = VIN, C4 (Green) = VOUT C2 (Red) = HSDR, C3 (Blue) = LSDR Figure 19. Shutdown Waveforms Figure 20. Startup into a Current Limit www.onsemi.com 8 NCP3020B tSoft−Start (ms) 1000 950 NCP3020A, NCP3020B, NCV3020A, NCV3020B DETAILED DESCRIPTION OVERVIEW and low−side MOSFET gate drives to prevent cross conduction of the power MOSFET’s. The NCP3020A/B operates as a 300/600 kHz, voltage mode, pulse width modulated, (PWM) synchronous buck converter. It drives high−side and low−side N−channel power MOSFETs. The NCP3020 incorporates an internal boost circuit consisting of a boost clamp and boost diode to provide supply voltage for the high side MOSFET gate driver. The NCP3020 also integrates several protection features including input undervoltage lockout (UVLO), output undervoltage (OUV), output overvoltage (OOV), adjustable high−side current limit (ISET and ILIM), and thermal shutdown (TSD). The operational transconductance amplifier (OTA) provides a high gain error signal from Vout which is compared to the internal 1.5 V pk-pk ramp signal to set the duty cycle converter using the PWM comparator. The high side switch is turned on by the positive edge of the clock cycle going into the PWM comparator and flip flop following a non-overlap time. The high side switch is turned off when the PWM comparator output is tripped by the modulator ramp signal reaching a threshold level established by the error amplifier. The gate driver stage incorporates fixed non− overlap time between the high−side POR and UVLO The device contains an internal Power On Reset (POR) and input Undervoltage Lockout (UVLO) that inhibits the internal logic and the output stage from operating until VCC reaches its respective predefined voltage levels (4.3 V typical). Startup and Shutdown Once VCC crosses the UVLO rising threshold the device begins its startup process. Closed−loop soft−start begins after a 400 ms delay wherein the boost capacitor is charged, and the current limit threshold is set. During the 400 ms delay the OTA output is set to just below the valley voltage of the internal ramp. This is done to reduce delays and to ensure a consistent pre−soft−start condition. The device increases the internal reference from 0 V to 0.6 V in 24 discrete steps while maintaining closed loop regulation at each step. Each step contains 64 switching cycles. Some overshoot may be evident at the start of each step depending on the voltage loop phase margin and bandwidth. The total soft−start time is 6.8 ms for the NCP3020A and 4.4 ms for the NCP3020B. 25 mV Steps 24 Voltage Steps Internal Reference Voltage Internal Ramp OTA Output 0.7 V 0V Figure 21. Soft−Start Details www.onsemi.com 9 0.6 V NCP3020A, NCP3020B, NCV3020A, NCV3020B OOV and OUV the output is considered “undervoltage” and the device will initiate a restart. When the feedback pin voltage rises between the reference voltages of comparator 1 and comparator 2 (0.45 < VFB < 0.75), then the output voltage is considered “Power Good.” Finally, if the feedback voltage is greater than comparator 1 (VFB > 0.75 V), the output voltage is considered “overvoltage,” and the device will latch off. To clear a latch fault, input voltage must be recycled. Graphical representation of the OOV and OUV is shown in Figures 24 and 25. The output voltage of the buck converter is monitored at the feedback pin of the output power stage. Two comparators are placed on the feedback node of the OTA to monitor the operating window of the feedback voltage as shown in Figures 22 and 23. All comparator outputs are ignored during the soft−start sequence as soft−start is regulated by the OTA and false trips would be generated. After the soft−start period has ended, if the feedback is below the reference voltage of comparator 2 (VFB < 0.45 V), Soft Start Complete Vref*125% Comparator 1 Restart LOGIC FB Latch off Vref*75% Comparator 2 Vref = 0.6 V Figure 22. OOV and OUV Circuit Diagram OOVP & Power Good = 0 Hysteresis = 5 mV Voov = Vref * 125% Power Not good High Power Good = 1 Vref = 0.6 V Power Good = 1 Hysteresis = 5 mV OUVP & Power Good = 0 Figure 23. OOV and OUV Window Diagram www.onsemi.com 10 Power Not Good Low Vouv = Vref * 75% NCP3020A, NCP3020B, NCV3020A, NCV3020B 0.75 V (vref *125%) 0.6 V (vref *100%) 0.45 V (vref *75%) FB Voltage Latch off Reinitiate Softstart Softstart Complete Figure 24. Powerup Sequence and Overvoltage Latch 0.75 V (vref *125%) 0.6 V (vref *100%) 0.45 V (vref * 75%) FB Voltage Latch off Reinitiate Softstart Softstart Complete Figure 25. Powerup Sequence and Undervoltage Soft−Start www.onsemi.com 11 NCP3020A, NCP3020B, NCV3020A, NCV3020B CURRENT LIMIT AND CURRENT LIMIT SET ILimit block consists of a voltage comparator circuit which compares the differential voltage across the VCC Pin and the VSW Pin with a resistor settable voltage reference. The sense portion of the circuit is only active while the HS MOSFET is turned ON. Overview The NCP3020 uses the voltage drop across the High Side MOSFET during the on time to sense inductor current. The VIN VCC VSense Ilim Out HSDR Itrip Ref VSW Switch Cap CONTROL Iset 13 uA LSDR 6 Vset DAC / COUNTER RSet Itrip Ref−63 Steps, 6.51 mV/step Figure 26. Iset / ILimit Block Diagram Current Limit Set prior to Soft−Start, the DAC counter increments the reference on the ISET comparator until it crosses the VSET voltage and holds the DAC reference output to that count value. This voltage is translated to the ILimit comparator during the ISense portion of the switching cycle through the switch cap circuit. See Figure 26. Exceeding the maximum sense voltage results in no current limit. Steps 0 to 10 result in an effective current limit of 0 mV. The ILimit comparator reference is set during the startup sequence by forcing a typically 13 mA current through the low side gate drive resistor. The gate drive output will rise to a voltage level shown in the equation below: V set + I set * R set (eq. 1) Where ISET is 13 mA and RSET is the gate to source resistor on the low side MOSFET. This resistor is normally installed to prevent MOSFET leakage from causing unwanted turn on of the low side MOSFET. In this case, the resistor is also used to set the ILimit trip level reference through the ILimit DAC. The Iset process takes approximately 350 ms to complete prior to Soft−Start stepping. The scaled voltage level across the ISET resistor is converted to a 6 bit digital value and stored as the trip value. The binary ILimit value is scaled and converted to the analog ILimit reference voltage through a DAC counter. The DAC has 63 steps in 6.51 mV increments equating to a maximum sense voltage of 403 mV. During the Iset period Current Sense Cycle Figure 27 shows how the current is sampled as it relates to the switching cycle. Current level 1 in Figure 27 represents a condition that will not cause a fault. Current level 2 represents a condition that will cause a fault. The sense circuit is allowed to operate below the 3/4 point of a given switching cycle. A given switching cycle’s 3/4 Ton time is defined by the prior cycle’s Ton and is quantized in 10 ns steps. A fault occurs if the sensed MOSFET voltage exceeds the DAC reference within the 3/4 time window of the switching cycle. www.onsemi.com 12 NCP3020A, NCP3020B, NCV3020A, NCV3020B Trip: Vsense > Itrip Ref at 3/4 Point No Trip: Vsense < Itrip Ref at 3/4 Point Itrip Ref Vsense ¾ ¾ Current Level 1 Ton−1 Ton−2 Current Level 2 3/4 Point Determined by Prior Cycle 1/4 1/2 1/4 1/2 3/4 3/4 Ton−1 Ton Each switching cycle’s Ton is counted in 10 nS time steps. The 3/4 sample time value is held and used for the following cycle’s limit sample time Figure 27. ILimit Trip Point Description Soft−Start Current limit Boost Clamp Functionality During soft−start the ISET value is doubled to allow for inrush current to charge the output capacitance. The DAC reference is set back to its normal value after soft−start has completed. The boost circuit requires an external capacitor connected between the BST and VSW pins to store charge for supplying the high and low−side gate driver voltage. This clamp circuit limits the driver voltage to typically 7.5 V when VIN > 9 V, otherwise this internal regulator is in dropout and typically VIN − 1.25 V. The boost circuit regulates the gate driver output voltage and acts as a switching diode. A simplified diagram of the boost circuit is shown in Figure 28. While the switch node is grounded, the sampling circuit samples the voltage at the boost pin, and regulates the boost capacitor voltage. The sampling circuit stores the boost voltage while the VSW is high and the linear regulator output transistor is reversed biased. VSW Ringing The ILimit block can lose accuracy if there is excessive VSW voltage ringing that extends beyond the 1/2 point of the high−side transistor on−time. Proper snubber design and keeping the ratio of ripple current and load current in the 10−30% range can help alleviate this as well. Current Limit A current limit trip results in completion of one switching cycle and subsequently half of another cycle Ton to account for negative inductor current that might have caused negative potentials on the output. Subsequently the power MOSFETs are both turned off and a 4 soft−start time period wait passes before another soft−start cycle is attempted. VIN 8.9V Iave vs Trip Point The average load trip current versus RSET value is shown the equation below: I AveTRIP + I set R set R DS(on) * ƪ 1 V IN * V OUT 4 L Switch Sampling Circuit ƫ V OUT 1 V IN F SW BST VSW LSDR (eq. 2) Where: L = Inductance (H) ISET = 13 mA RSET = Gate to Source Resistance (W) RDS(on) = On Resistance of the HS MOSFET (W) VIN = Input Voltage (V) VOUT = Output Voltage (V) FSW = Switching Frequency (Hz) Figure 28. Boost Circuit www.onsemi.com 13 NCP3020A, NCP3020B, NCV3020A, NCV3020B Reduced sampling time occurs at high duty cycles where the low side MOSFET is off for the majority of the switching period. Reduced sampling time causes errors in the regulated voltage on the boost pin. High duty cycle / input voltage induced sampling errors can result in increased boost ripple voltage or higher than desired DC boost voltage. Figure 29 outlines all operating regions. The recommended operating conditions are shown in Region 1 (Green) where a 0.1 mF, 25 V ceramic capacitor can be placed on the boost pin without causing damage to the device or MOSFETS. Larger boost ripple voltage occurring over several switching cycles is shown in Region 2 (Yellow). The boost ripple frequency is dependent on the output capacitance selected. The ripple voltage will not damage the device or $12 V gate rated MOSFETs. Conditions where maximum boost ripple voltage could damage the device or $12 V gate rated MOSFETs can be seen in Region 3 (Orange). Placing a boost capacitor that is no greater than 10X the input capacitance of the high side MOSFET on the boost pin limits the maximum boost voltage < 12 V. The typical drive waveforms for Regions 1, 2 and 3 (green, yellow, and orange) regions of Figure 29 are shown in Figure 30. Boost Voltage Levels Normal Operation Increased Boost Ripple (Still in Specification) Increased Boost Ripple Capacitor Optimization Required 28 Region 3 26 24 In p u t V o lt a g e 22 22V 20 18 Region 2 Maxi mum Max Duty Duty Cycle Cycle Region 1 16 14 12 11.5V 10 8 71% 6 4 2 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 Duty Cycle Figure 29. Safe Operating Area for Boost Voltage with a 0.1 mF Capacitor www.onsemi.com 14 NCP3020A, NCP3020B, NCV3020A, NCV3020B VIN 7.5V VBOOST 7.5V 0V Maximum Normal VIN 7.5V VBOOST 7.5V 0V Maximum Normal VIN 7.5V VBOOST 7.5V 0V Figure 30. Typical Waveforms for Region 1 (top), Region 2 (middle), and Region 3 (bottom) To illustrate, a 0.1 mF boost capacitor operating at > 80% duty cycle and > 22.5 V input voltage will exceed the specifications for the driver supply voltage. See Figure 31. www.onsemi.com 15 NCP3020A, NCP3020B, NCV3020A, NCV3020B Boost Voltage 18 Voltage Ripple Maximum Allowable Voltage Maximum Boost Voltage 16 14 Boost Voltage (V) 12 10 8 6 4 2 0 4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 Input Voltage (V) 20.5 22.5 24.5 26.5 Figure 31. Boost Voltage at 80% Duty Cycle Inductor Selection D+ When selecting the inductor, it is important to know the input and output requirements. Some example conditions are listed below to assist in the process. V OUT ) V LSD V IN * V HSD ) V LSD ³ 27.5% + Table 1. DESIGN PARAMETERS Design Parameter (VIN) 9 V to 18 V Nominal Input Voltage (VIN) 12 V (VOUT) 3.3 V Output Voltage Input ripple voltage 300 mV Output ripple voltage (VOUTRIPPLE) 50 mV Output current rating (IOUT) 10 A Operating frequency (Fsw) 300 kHz D+ T ON T 1 T (* D Ǔ + L+ + T 12 V DI I OUT (eq. 6) V OUT I OUT @ ra @ F SW @ (1 * D) ³ 3.3 mH 3.3 V 10 A @ 24% @ 300 kHz (eq. 7) @ (1 * 27.5%) The relationship between ra and L for this design example is shown in Figure 32. (eq. 3) T OFF (eq. 5) The designer should employ a rule of thumb where the percentage of ripple current in the inductor lies between 10% and 40%. When using ceramic output capacitors the ripple current can be greater thus a user might select a higher ripple current, but when using electrolytic capacitors a lower ripple current will result in lower output ripple. Now, acceptable values of inductance for a design can be calculated using Equation 7. A buck converter produces input voltage (VIN) pulses that are LC filtered to produce a lower dc output voltage (VOUT). The output voltage can be changed by modifying the on time relative to the switching period (T) or switching frequency. The ratio of high side switch on time to the switching period is called duty cycle (D). Duty cycle can also be calculated using VOUT, VIN, the low side switch voltage drop VLSD, and the High side switch voltage drop VHSD. F+ V IN 3.3 V ra + (VINRIPPLE) V OUT The ratio of ripple current to maximum output current simplifies the equations used for inductor selection. The formula for this is given in Equation 6. Example Value Input Voltage [D+ (eq. 4) www.onsemi.com 16 L, INDUCTANCE (mH) NCP3020A, NCP3020B, NCV3020A, NCV3020B 18 17 16 18 V 15 14 15 V 13 12 11 10 12 V 9 8 7 6 5 4 9V 3 2 1 0 10% 15% 20% 25% I PP + Vout = 3.3 V 30% 35% 40% LP CU + I RMS 2 @ DCR To keep within the bounds of the parts maximum rating, calculate the RMS current and peak current. Ǹ1 ) ra12 ³ 10.02 A 2 Ǹ1 ) (0.24) 12 Input Capacitor Selection ǒ (0.24) ra I PK + I OUT @ 1 ) ³ 11.2 A + 10 A @ 1 ) 2 2 ǒ Ǔ LP tot + LP CU_DC ) LP CU_AC ) LP Core (eq. 13) (eq. 8) 2 The input capacitor has to sustain the ripple current produced during the on time of the upper MOSFET, so it must have a low ESR to minimize the losses. The RMS value of this ripple is: Ǔ (eq. 9) Iin RMS + I OUT @ ǸD @ (1 * D) An inductor for this example would be around 3.3 mH and should support an rms current of 10.02 A and a peak current of 11.2 A. The final selection of an output inductor has both mechanical and electrical considerations. From a mechanical perspective, smaller inductor values generally correspond to smaller physical size. Since the inductor is often one of the largest components in the regulation system, a minimum inductor value is particularly important in space−constrained applications. From an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by Equation 10. SlewRate LOUT + V IN * V OUT L OUT ³ 2.6 (eq. 12) The core losses and ac copper losses will depend on the geometry of the selected core, core material, and wire used. Most vendors will provide the appropriate information to make accurate calculations of the power dissipation then the total inductor losses can be capture buy the equation below: Figure 32. Ripple Current Ratio vs. Inductance + 10 A @ (eq. 11) L OUT @ F SW Ipp is the peak to peak current of the inductor. From this equation it is clear that the ripple current increases as LOUT decreases, emphasizing the trade−off between dynamic response and ripple current. The power dissipation of an inductor consists of both copper and core losses. The copper losses can be further categorized into dc losses and ac losses. A good first order approximation of the inductor losses can be made using the DC resistance as they usually contribute to 90% of the losses of the inductor shown below: VIN, (V) I RMS + I OUT @ V OUT(1 * D) (eq. 14) D is the duty cycle, IinRMS is the input RMS current, and IOUT is the load current. The equation reaches its maximum value with D = 0.5. Loss in the input capacitors can be calculated with the following equation: P CIN + ESR CIN @ ǒI IN*RMSǓ 2 (eq. 15) PCIN is the power loss in the input capacitors and ESRCIN is the effective series resistance of the input capacitance. Due to large dI/dt through the input capacitors, electrolytic or ceramics should be used. If a tantalum must be used, it must by surge protected. Otherwise, capacitor failure could occur. 12 V * 3.3 V A + ms 3.3 mH (eq. 10) Input Start−up Current This equation implies that larger inductor values limit the regulator’s ability to slew current through the output inductor in response to output load transients. Consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. This results in larger values of output capacitance to maintain tight output voltage regulation. In contrast, smaller values of inductance increase the regulator’s maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. The peak−to−peak ripple current for the NCP3020A is given by the following equation: To calculate the input startup current, the following equation can be used. I INRUSH + C OUT @ V OUT t SS (eq. 16) Iinrush is the input current during startup, COUT is the total output capacitance, VOUT is the desired output voltage, and tSS is the soft start interval. If the inrush current is higher than the steady state input current during max load, then the input fuse should be rated accordingly, if one is used. www.onsemi.com 17 NCP3020A, NCP3020B, NCV3020A, NCV3020B Output Capacitor Selection In a typical converter design, the ESR of the output capacitor bank dominates the transient response. It should be noted that DVOUT−DISCHARGE and DVOUT−ESR are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the ESL). Conversely during a load release, the output voltage can increase as the energy stored in the inductor dumps into the output capacitor. The ESR contribution from Equation 18 still applies in addition to the output capacitor charge which is approximated by the following equation: The important factors to consider when selecting an output capacitor is dc voltage rating, ripple current rating, output ripple voltage requirements, and transient response requirements. The output capacitor must be rated to handle the ripple current at full load with proper derating. The RMS ratings given in datasheets are generally for lower switching frequency than used in switch mode power supplies but a multiplier is usually given for higher frequency operation. The RMS current for the output capacitor can be calculated below: ra Co RMS + I O @ Ǹ12 2 DV OUT−CHG + (eq. 17) The maximum allowable output voltage ripple is a combination of the ripple current selected, the output capacitance selected, the equivalent series inductance (ESL) and ESR. The main component of the ripple voltage is usually due to the ESR of the output capacitor and the capacitance selected. ǒ V ESR_C + I O @ ra @ ESR Co ) Ǔ 1 8 @ F SW @ Co ESL @ I PP @ F SW V ESLOFF + D ESL @ I PP @ F SW (1 * D ) Power dissipation, package size, and the thermal environment drive MOSFET selection. To adequately select the correct MOSFETs, the design must first predict its power dissipation. Once the dissipation is known, the thermal impedance can be calculated to prevent the specified maximum junction temperatures from being exceeded at the highest ambient temperature. Power dissipation has two primary contributors: conduction losses and switching losses. The control or high−side MOSFET will display both switching and conduction losses. The synchronous or low−side MOSFET will exhibit only conduction losses because it switches into nearly zero voltage. However, the body diode in the synchronous MOSFET will suffer diode losses during the non−overlap time of the gate drivers. Starting with the high−side or control MOSFET, the power dissipation can be approximated from: (eq. 18) (eq. 19) P D_CONTROL + P COND ) P SW_TOT (eq. 20) 2 P COND + ǒI RMS_CONTROLǓ @ R DS(on)_CONTROL (eq. 25) Using the ra term from Equation 6, IRMS becomes: I RMS_CONTROL + I OUT @ C OUT @ ǒV IN * V OUTǓ ǒ ǒra12 ǓǓ D@ 1) 2 P SW_TOT + P SW ) P DS ) P RR (eq. 21) (eq. 26) (eq. 27) The first term for total switching losses from Equation 27 includes the losses associated with turning the control MOSFET on and off and the corresponding overlap in drain voltage and current. P SW + P TON ) P TOFF 2 DV OUT−DISCHG + Ǹ The second term from Equation 24 is the total switching loss and can be approximated from the following equations. A minimum capacitor value is required to sustain the current during the load transient without discharging it. The voltage drop due to output capacitor discharge is approximated by the following equation: ǒI TRANǓ @ LOUT (eq. 24) The first term is the conduction loss of the high−side MOSFET while it is on. The output capacitor is a basic component for the fast response of the power supply. In fact, during load transient, for the first few microseconds it supplies the current to the load. The controller immediately recognizes the load transient and sets the duty cycle to maximum, but the current slope is limited by the inductor value. During a load step transient the output voltage initially drops due to the current variation inside the capacitor and the ESR (neglecting the effect of the effective series inductance (ESL)). DV OUT−ESR + DI TRAN @ ESR Co (eq. 23) C OUT @ V OUT Power MOSFET Selection The ESL of capacitors depends on the technology chosen but tends to range from 1 nH to 20 nH where ceramic capacitors have the lowest inductance and electrolytic capacitors then to have the highest. The calculated contributing voltage ripple from ESL is shown for the switch on and switch off below: V ESLON + ǒI TRANǓ @ LOUT + 1 @ ǒI OUT @ V IN @ f SWǓ @ ǒt ON ) t OFFǓ 2 (eq. 22) www.onsemi.com 18 (eq. 28) NCP3020A, NCP3020B, NCV3020A, NCV3020B where: t ON + Q GD I G1 + Q GD ǒV BST * V THǓńǒR HSPU ) R GǓ IG1: output current from the high−side gate drive (HSDR) IG2: output current from the low−side gate drive (LSDR) ƒSW: switching frequency of the converter. NCP3020A is 300 kHz and NCP3020B is 600 kHz VBST: gate drive voltage for the high−side drive, typically 7.5 V. QGD: gate charge plateau region, commonly specified in the MOSFET datasheet VTH: gate−to−source voltage at the gate charge plateau region QOSS: MOSFET output gate charge specified in the data sheet QRR: reverse recovery charge of the low−side or synchronous MOSFET, specified in the datasheet RDS(on)_CONTROL: on resistance of the high−side, or control, MOSFET RDS(on)_SYNC: on resistance of the low−side, or synchronous, MOSFET NOLLH: dead time between the LSDR turning off and the HSDR turning on, typically 85 ns NOLHL: dead time between the HSDR turning off and the LSDR turning on, typically 75 ns (eq. 29) and: t OFF + Q GD I G2 + Q GD ǒV BST * V THǓńǒR HSPD ) R GǓ (eq. 30) Next, the MOSFET output capacitance losses are caused by both the control and synchronous MOSFET but are dissipated only in the control MOSFET. P DS + 1 @ Q OSS @ V IN @ f SW 2 (eq. 31) Finally the loss due to the reverse recovery time of the body diode in the synchronous MOSFET is shown as follows: P RR + Q RR @ V IN @ f SW (eq. 32) The low−side or synchronous MOSFET turns on into zero volts so switching losses are negligible. Its power dissipation only consists of conduction loss due to RDS(on) and body diode loss during the non−overlap periods. P D_SYNC + P COND ) P BODY Once the MOSFET power dissipations are determined, the designer can calculate the required thermal impedance for each device to maintain a specified junction temperature at the worst case ambient temperature. The formula for calculating the junction temperature with the package in free air is: (eq. 33) Conduction loss in the low−side or synchronous MOSFET is described as follows: 2 P COND + ǒI RMS_SYNCǓ @ R DS(on)_SYNC (eq. 34) where: I RMS_SYNC + I OUT @ Ǹ ǒ ǒ 12 ǓǓ ( 1 * D) @ 1 ) ra 2 T J + T A ) P D @ R qJA TJ: Junction Temperature TA: Ambient Temperature PD: Power Dissipation of the MOSFET under analysis RqJA: Thermal Resistance Junction−to−Ambient of the MOSFET’s package (eq. 35) The body diode losses can be approximated as: P BODY + V FD @ I OUT @ f SW @ ǒNOL LH ) NOL HLǓ (eq. 36) As with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. Variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e. worst case MOSFET RDS(on)). Vth Figure 33. MOSFET Switching Characteristics www.onsemi.com 19 NCP3020A, NCP3020B, NCV3020A, NCV3020B NOLHL NOLLH High−Side Logic Signal Low−Side Logic Signal td(on) tf RDSmax High−Side MOSFET RDS(on)min tr td(off) tr tf RDSmax Low−Side MOSFET RDS(on)min td(on) td(off) Figure 34. MOSFETs Timing Diagram response. The goal of the compensation circuit is to provide a loop gain function with the highest crossing frequency and adequate phase margin (minimally 45°). The transfer function of the power stage (the output LC filter) is a double pole system. The resonance frequency of this filter is expressed as follows: Another consideration during MOSFET selection is their delay times. Turn−on and turn−off times must be short enough to prevent cross conduction. If not, there will be conduction from the input through both MOSFETs to ground. Therefore, the following conditions must be met. t d(ON)_CONTROL ) NOL LH u t d(OFF)_SYNC ) t f_SYNC f P0 + (eq. 37) and t (ON)_SYNC ) NOL HL u t d(OFF)_CONTROL ) t f _CONTROL 1 2 @ p @ ǸL @ C OUT (eq. 38) Parasitic Equivalent Series Resistance (ESR) of the output filter capacitor introduces a high frequency zero to the filter network. Its value can be calculated by using the following equation: The MOSFET parameters, td(ON), tr, td(OFF) and tf are can be found in their appropriate datasheets for specific conditions. NOLLH and NOLHL are the dead times which were described earlier and are 85 ns and 75 ns, respectively. f Z0 + Feedback and Compensation The NCP3020 is a voltage mode buck convertor with a transconductance error amplifier compensated by an external compensation network. Compensation is needed to achieve accurate output voltage regulation and fast transient 1 2 @ p @ C OUT @ ESR (eq. 39) The main loop zero crossover frequency f0 can be chosen to be 1/10 − 1/5 of the switching frequency. Table 2 shows the three methods of compensation. Table 2. COMPENSATION TYPES Zero Crossover Frequency Condition Compensation Type Typical Output Capacitor Type fP0 < fZ0 < f0 < fS/2 Type II Electrolytic, Tantalum fP0 < f0 < fZ0 < fS/2 Type III Method I Tantalum, Ceramic fP0 < f0 < fS/2 < fZ0 Type III Method II Ceramic www.onsemi.com 20 NCP3020A, NCP3020B, NCV3020A, NCV3020B Compensation Type II This compensation is suitable for electrolytic capacitors. Components of the Type II (Figure 35) network can be specified by the following equations: f Z1 + 0.75 @ f P0 (eq. 44) f Z2 + f P0 (eq. 45) f P2 + f Z0 (eq. 46) fS f P3 + (eq. 47) 2 Method II is better suited for ceramic capacitors that typically have the lowest ESR available: Figure 35. Type II Compensation R C1 + 2 @ p @ f 0 @ L @ V RAMP @ V OUT ESR @ V IN @ V ref @ gm 1 0.75 @ 2 @ p @ f P0 @ R C1 (eq. 41) C C2 + 1 p @ R C1 @ f S (eq. 42) R1 + V OUT * V ref V ref @ R2 sinq max Ǹ11 )* sin q max (eq. 48) f P2 + f 0 @ sin q max Ǹ11 *) sin q max (eq. 49) f Z1 + 0.5 @ f Z2 (eq. 50) f P3 + 0.5 @ f S (eq. 51) qmax is the desired maximum phase margin at the zero crossover frequency, ƒ0. It should be 45° − 75°. Convert degrees to radians by the formula: (eq. 40) C C1 + f Z2 + f 0 @ ǒ Ǔ q max + q max degress @ 2 @ p : Units + radians 360 (eq. 52) The remaining calculations are the same for both methods. R C1 u u (eq. 43) VRAMP is the peak−to−peak voltage of the oscillator ramp and gm is the transconductance error amplifier gain. Capacitor CC2 is optional. Compensation Type III 1 2 @ p @ f Z1 @ R C1 (eq. 54) C C2 + 1 2 @ p @ f P3 @ R C1 (eq. 55) R FB1 + R1 + R2 + (eq. 53) C C1 + C FB1 + Tantalum and ceramics capacitors have lower ESR than electrolytic, so the zero of the output LC filter goes to a higher frequency above the zero crossover frequency. This requires a Type III compensation network as shown in Figure 36. There are two methods to select the zeros and poles of this compensation network. Method I is ideal for tantalum output capacitors, which have a higher ESR than ceramic: 2 gm 2 @ p @ f 0 @ L @ V RAMP @ C OUT V IN @ R C1 1 (eq. 57) 2p @ C FB1 @ f P2 1 * R FB1 2 @ p @ C FB1 @ f Z2 V ref V OUT * V ref (eq. 56) (eq. 58) @ R1 (eq. 59) If the equation in Equation 60 is not true, then a higher value of RC1 must be selected. R1 @ R2 @ R FB1 R1 @ R FB1 ) R2 @ R FB1 ) R1 @ R2 Figure 36. Type III Compensation www.onsemi.com 21 u 1 (eq. 60) gm NCP3020A, NCP3020B, NCV3020A, NCV3020B TYPICAL APPLICATION CIRCUIT 9−18 V C IN−1/2 CIN−3/4 CIN−5 COMP RC C c1 VCC BST NCP3020A C BST HSDR RG Q1 RGS 3.3 uH 3.3 V VSW Q2 LSDR FB C c2 D1 RFB1 C FB R ISET GND R FB3 C OUT −1 C OUT −2/3 R FB2 Figure 37. Typical Application, VIN = 9 − 18 V, VOUT = 3.3 V, IOUT = 10 A Reference Designator Special Note Value CIN−1 470 mF CIN−2 470 mF CIN−3 22 mF CIN−4 22 mF CIN−5 1 mF CC1 33 pF CC2 8.2 nF CFB 1.8 nF COUT1 470 mF COUT2 22 mF COUT3 22 mF CBST 0.1 mF RC 4.75 kW RG 8.06 W RGS 1.0 kW RISET 22.1 kW RFB1 4.53 kW RFB2 1.0 kW RFB3 2.49 kW Q1 NTMFS4841N Q2 NTMFS4935 D1 BAT54 The NCP3020/NCV3020 are dedicated for current sensing across high−side MOSFET via VCC pin and VSW pin, as shown in Figure 26. Therefore, the VCC pin must connect to the VIN voltage, i.e., the drain of high−side MOSFET as shown in Figure 37 above. In other words, the NCP3020/NCV3020 does not support separated VCC voltage and VIN voltage, regardless any current limit setting in LSDR pin. Using a lower VCC voltage than the VIN voltage, such as VCC=12V and VIN=20V, may damage the NCP3020/NCV3020. Disconnecting the VCC pin supply, while VIN is still presented, risks the NCP3020/NCV3020 of being damaged as well. www.onsemi.com 22 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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