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NCP3063MNTXG

NCP3063MNTXG

  • 厂商:

    ONSEMI(安森美)

  • 封装:

    VDFN8

  • 描述:

    IC REG BUCK BST ADJ 1.5A 8DFN

  • 数据手册
  • 价格&库存
NCP3063MNTXG 数据手册
DATA SHEET www.onsemi.com 1.5 A, Step-Up/Down/ Inverting Switching Regulators MARKING DIAGRAMS 8 NCP3063, NCP3063B, NCV3063 1 SOIC−8 D SUFFIX CASE 751 The NCP3063 Series is a higher frequency upgrade to the popular MC34063A and MC33063A monolithic DC−DC converters. These devices consist of an internal temperature compensated reference, comparator, a controlled duty cycle oscillator with an active current limit circuit, a driver and a high current output switch. This series was specifically designed to be incorporated in Step−Down, Step−Up and Voltage−Inverting applications with a minimum number of external components. Features • • • • • • • • 8 NCP3063 COMPARATOR − + 1 TSD Q NCP 3063 ALYW G ORDERING INFORMATION 2 SET dominant R OSCILLATOR 0.2 V 3 See detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet. D L 47 mH CT COMPARATOR − R2 R1 2.4 kW NCP 3063x ALYW G (Note: Microdot may be in either location) S S + NCV3063 AWL YYWWG NCP3063x = Specific Device Code x=B A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G = Pb−Free Package Q 5 1 DFN−8 CASE 488AF R 12 V + Cin 220 mF NCP3063x AWL YYWWG 1 SET dominant Vin 1 1 • Step−Down, Step−Up and Inverting supply applications • High Power LED Lighting • Battery Chargers 0.15 W 6 V3063 ALYW G 1 PDIP−8 P, P1 SUFFIX CASE 626 Applications Rs 1 8 Operation to 40 V Input Low Standby Current Output Switch Current to 1.5 A Output Voltage Adjustable Frequency Operation of 150 kHz Precision 1.5% Reference New Features: Internal Thermal Shutdown with Hysteresis Cycle−by−Cycle Current Limiting Pb−Free Packages are Available 7 3063x ALYW G 1.25 V REFERENCE REGULATOR 3.9 kW CT 2.2 nF 4 Vout 3.3 V / 800 mA 470 mF Cout + Figure 1. Typical Buck Application Circuit © Semiconductor Components Industries, LLC, 2011 August, 2021 − Rev. 10 1 Publication Order Number: NCP3063/D NCP3063, NCP3063B, NCV3063 1 Switch Collector Switch Emitter 2 8 N.C. 7 Ipk Sense Timing Capacitor 3 6 GND 4 5 ÇÇ ÇÇ ÇÇ ÇÇ Switch Collector Switch Emitter Timing Capacitor VCC GND Comparator Inverting Input (Top View) EP Flag Ç Ç Ç Ç (Top View) NOTE: Figure 2. Pin Connections N.C. Ipk Sense VCC Comparator Inverting Input EP Flag must be tied to GND Pin 4 on PCB Figure 3. Pin Connections NCP3063 8 1 TSD N.C. Switch Collector SET dominant R S 7 Ipk Sense Q COMPARATOR − + S R 2 Q 0.2 V OSCILLATOR 6 3 Timing Capacitor CT +VCC COMPARATOR 1.25 V REFERENCE REGULATOR + 5 Switch Emitter SET dominant − 4 GND Comparator Inverting Input Figure 4. Block Diagram www.onsemi.com 2 NCP3063, NCP3063B, NCV3063 PIN DESCRIPTION Pin No. Pin Name 1 Switch Collector 2 Switch Emitter 3 Timing Capacitor Oscillator Input 4 GND 5 Comparator Inverting Input 6 VCC 7 Ipk Sense 8 N.C. Exposed Pad Exposed Pad Description Internal Darlington switch collector Internal Darlington switch emitter Timing Capacitor Ground pin for all internal circuits Inverting input pin of internal comparator Voltage Supply Peak Current Sense Input to monitor the voltage drop across an external resistor to limit the peak current through the circuit Pin Not Connected The exposed pad beneath the package must be connected to GND (Pin 4). Additionally, using proper layout techniques, the exposed pad can greatly enhance the power dissipation capabilities of the NCP3063. MAXIMUM RATINGS (measured vs. Pin 4, unless otherwise noted) Rating Symbol Value Unit VCC pin 6 VCC 0 to +40 V Comparator Inverting Input pin 5 VCII −0.2 to + VCC V Darlington Switch Collector pin 1 VSWC 0 to +40 V Darlington Switch Emitter pin 2 (transistor OFF) VSWE −0.6 to + VCC V Darlington Switch Collector to Emitter pin 1−2 VSWCE 0 to +40 V ISW 1.5 A Darlington Switch Current Ipk Sense Pin 7 Timing Capacitor Pin 3 VIPK −0.2 to VCC + 0.2 V VTCAP −0.2 to +1.4 V Symbol Value Unit POWER DISSIPATION AND THERMAL CHARACTERISTICS Rating PDIP−8 Thermal Resistance, Junction−to−Air RqJA SOIC−8 Thermal Resistance, Junction−to−Air Thermal Resistance, Junction−to−Case RqJA RqJC DFN−8 Thermal Resistance, Junction−to−Air RqJA Storage Temperature Range Maximum Junction Temperature 100 180 45 80 °C/W °C/W °C/W TSTG −65 to +150 °C TJ MAX +150 °C Operating Junction Temperature Range (Note 3) NCP3063 NCP3063B, NCV3063 TJ 0 to +70 −40 to +125 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Pin 1−8: Human Body Model 2000 V per AEC Q100−002; 003 or JESD22/A114; A115 Machine Model Method 200 V 2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. 3. The relation between junction temperature, ambient temperature and Total Power dissipated in IC is TJ = TA + Rq • PD 4. The pins which are not defined may not be loaded by external signals www.onsemi.com 3 NCP3063, NCP3063B, NCV3063 ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TJ = Tlow to Thigh [Note 5], unless otherwise specified) Characteristic Conditions Min Typ Max Unit Frequency (VPin 5 = 0 V, CT = 2.2 nF, TJ = 25°C) 110 150 190 kHz IDISCHG / ICHG Discharge to Charge Current Ratio (Pin 7 to VCC, TJ = 25°C) 5.5 6.0 6.5 − IDISCHG Capacitor Discharging Current (Pin 7 to VCC, TJ = 25°C) 1650 mA ICHG Capacitor Charging Current (Pin 7 to VCC, TJ = 25°C) 275 mA VIPK(Sense) Current Limit Sense Voltage (TJ = 25°C) (Note 6) Symbol OSCILLATOR fOSC 165 200 235 mV (ISW = 1.0 A, Pin 2 to GND, TJ = 25°C) (Note 7) 1.0 1.3 V (VCE = 40 V) 0.01 100 mA OUTPUT SWITCH (Note 7) VSWCE(DROP) Darlington Switch Collector to Emitter Voltage Drop IC(OFF) Collector Off−State Current COMPARATOR VTH REGLiNE ICII in Threshold Voltage Threshold Voltage Line Regulation Input Bias Current TJ = 25°C 1.250 V NCP3063 −1.5 +1.5 % NCP3063B, NCV3063 −2 +2 % (VCC = 5.0 V to 40 V) −6.0 2.0 6.0 mV (Vin = Vth) −1000 −100 1000 nA 7.0 mA TOTAL DEVICE ICC Supply Current (VCC = 5.0 V to 40 V, CT = 2.2 nF, Pin 7 = VCC, VPin 5 > Vth, Pin 2 = GND, remaining pins open) Thermal Shutdown Threshold 160 °C Hysteresis 10 °C 5. NCP3063: Tlow = 0°C, Thigh = +70°C; NCP3063B, NCV3063: Tlow = −40°C, Thigh = +125°C 6. The VIPK(Sense) Current Limit Sense Voltage is specified at static conditions. In dynamic operation the sensed current turn−off value depends on comparator response time and di/dt current slope. See the Operating Description section for details. 7. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible. 8. NCV prefix is for automotive and other applications requiring site and change control. www.onsemi.com 4 NCP3063, NCP3063B, NCV3063 450 190 400 180 FREQUENCY (kHz) FREQUENCY (kHz) 350 300 250 200 150 100 170 160 150 140 130 120 50 0 110 0 1 2 3 4 5 6 7 8 9 10 11 12 1314 1516 1718 1920 7 12 16 21 25 29 34 38 40 VCC, SUPPLY VOLTAGE (V) Figure 5. Oscillator Frequency vs. Oscillator Timing Capacitor Figure 6. Oscillator Frequency vs. Supply Voltage 1.25 VCC = 5.0 V IE = 1 A VCC = 5.0 V IC = 1 A 1.20 VOLTAGE DROP (V) 2.2 VOLTAGE DROP (V) 3 Ct, CAPACITANCE (nF) 2.4 2.0 1.8 1.6 1.4 1.15 1.10 1.05 1.2 1.0 −50 0 50 100 1.0 −50 150 0 50 100 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 7. Emitter Follower Configuration Output Darlington Switch Voltage Drop vs. Temperature Figure 8. Common Emitter Configuration Output Darlington Switch Voltage Drop vs. Temperature 1.5 2.0 1.9 1.4 VCC = 5.0 V TJ = 25°C 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 1.2 0.7 1.1 1.0 0.6 0.5 0 VCC = 5.0 V TJ = 25°C 1.3 VOLTAGE DROP (V) 1.8 VOLTAGE DROP (V) CT = 2.2 nF TJ = 25°C 0.5 1.0 1.5 0 0.5 1.0 IE, EMITTER CURRENT (A) IC, COLLECTOR CURRENT (A) Figure 9. Emitter Follower Configuration Output Darlington Switch Voltage Drop vs. Emitter Current Figure 10. Common Emitter Configuration Output Darlington Switch Voltage Drop vs. Collector Current www.onsemi.com 5 1.5 Vth, COMPARATOR THRESHOLD VOLTAGE (V) NCP3063, NCP3063B, NCV3063 0.30 Vipk(sense), CURRENT LIMIT SENSE VOLTAGE (V) 1.30 1.28 1.26 1.24 1.22 1.20 −40 −25 −10 5 20 35 50 65 80 95 110 125 0.28 0.26 0.24 0.22 0.20 0.18 0.16 0.14 0.12 0.10 −40 −25 −10 TJ, JUNCTION TEMPERATURE (°C) 5 20 ICC, SUPPLY CURRENT (mA) 5.5 5.0 4.5 4.0 3.5 CT = 2.2 nF Pin 5, 7 = VCC Pin 2 = GND 3.0 2.5 8.0 65 80 95 110 125 Figure 12. Current Limit Sense Voltage vs. Temperature 6.0 3.0 50 TJ, JUNCTION TEMPERATURE (°C) Figure 11. Comparator Threshold Voltage vs. Temperature 2.0 35 13 18 23 28 33 38 43 VCC, SUPPLY VOLTAGE (V) Figure 13. Standby Supply Current vs. Supply Voltage www.onsemi.com 6 NCP3063, NCP3063B, NCV3063 INTRODUCTION The NCP3063 is a monolithic power switching regulator optimized for dc to dc converter applications. The combination of its features enables the system designer to directly implement step−up, step−down, and voltage− inverting converters with a minimum number of external components. Potential applications include cost sensitive consumer products as well as equipment for industrial markets. A representative block diagram is shown in Figure 4. controlled by the oscillator, thus pumping up the output filter capacitor. When the output voltage level reaches nominal, the output switch next cycle turning on is inhibited. The feedback comparator will enable the switching immediately when the load current causes the output voltage to fall below nominal. Under these conditions, output switch conduction can be enabled for a partial oscillator cycle, a partial cycle plus a complete cycle, multiple cycles, or a partial cycle plus multiple cycles. (See AN920/D for more information). Operating Description Oscillator The NCP3063 is a hysteretic, dc−dc converter that uses a gated oscillator to regulate output voltage. In general, this mode of operation is somewhat analogous to a capacitor charge pump and does not require dominant pole loop compensation for converter stability. The Typical Operating Waveforms are shown in Figure 14. The output voltage waveform shown is for a step−down converter with the ripple and phasing exaggerated for clarity. During initial converter startup, the feedback comparator senses that the output voltage level is below nominal. This causes the output switch to turn on and off at a frequency and duty cycle The oscillator frequency and off−time of the output switch are programmed by the value selected for timing capacitor CT. Capacitor CT is charged and discharged by a 1 to 6 ratio internal current source and sink, generating a positive going sawtooth waveform at Pin 3. This ratio sets the maximum tON/(tON + tOFF) of the switching converter as 6/(6 + 1) or 0.857 (typical) The oscillator peak and valley voltage difference is 500 mV typically. To calculate the CT capacitor value for required oscillator frequency, use the equations found in Figure 15. An Excel based design tool can be found at www.onsemi.com on the NCP3063 product page. Feedback Comparator Output 1 0 1 IPK Comparator Output 0 Timing Capacitor, CT Output Switch On Off Nominal Output Voltage Level Output Voltage Startup Operation Figure 14. Typical Operating Waveforms www.onsemi.com 7 NCP3063, NCP3063B, NCV3063 Peak Current Sense Comparator Real Vturn−off on Rsc resistor With a voltage ripple gated converter operating under normal conditions, output switch conduction is initiated by the Voltage Feedback comparator and terminated by the oscillator. Abnormal operating conditions occur when the converter output is overloaded or when feedback voltage sensing is lost. Under these conditions, the Ipk Current Sense comparator will protect the Darlington output Switch. The switch current is converted to a voltage by inserting a fractional ohm resistor, RSC, in series with VCC and the Darlington output switch. The voltage drop across RSC is monitored by the Current Sense comparator. If the voltage drop exceeds 200 mV with respect to VCC, the comparator will set the latch and terminate output switch conduction on a cycle−by−cycle basis. This Comparator/Latch configuration ensures that the Output Switch has only a single on−time during a given oscillator cycle. Real Vturn−off on Rs Resistor Vipk(sense) Vturn_off + Vipk(sense) ) Rs @ (t_delay @ dińdt) Typical Ipk comparator response time t_delay is 350 ns. The di/dt current slope is growing with voltage difference on the inductor pins and with decreasing inductor value. It is recommended to check the real max peak current in the application at worst conditions to be sure that the max peak current will never get over the 1.5 A Darlington Switch Current max rating. Thermal Shutdown Internal thermal shutdown circuitry is provided to protect the IC in the event that the maximum junction temperature is exceeded. When activated, typically at 160°C, the Output Switch is disabled. The temperature sensing circuit is designed with 10°C hysteresis. The Switch is enabled again when the chip temperature decreases to at least 150°C threshold. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used as a replacement for proper heatsinking. I1 di/dt slope Io I through the Darlington Switch Output Switch t_delay The output switch is designed in a Darlington configuration. This allows the application designer to operate at all conditions at high switching speed and low voltage drop. The Darlington Output Switch is designed to switch a maximum of 40 V collector to emitter voltage and current up to 1.5 A. The VIPK(Sense) Current Limit Sense Voltage threshold is specified at static conditions. In dynamic operation the sensed current turn−off value depends on comparator response time and di/dt current slope. APPLICATIONS Figures 16 through 24 show the simplicity and flexibility of the NCP3063. Three main converter topologies are demonstrated with actual test data shown below each of the circuit diagrams. Figure 15 gives the relevant design equations for the key parameters. Additionally, a complete application design aid for the NCP3063 can be found at www.onsemi.com. Figures 25 through 31 show typical NCP3063 applications with external transistors. This solution helps to increase output current and helps with efficiency still keeping low cost bill of materials. Typical schematics of boost configuration with NMOS transistor, buck configuration with PMOS transistor and buck configuration with LOW VCE(sat) PNP are shown. Another advantage of using the external transistor is higher operating frequency which can go up to 250 kHz. Smaller size of the output components such as inductor and capacitor can be used then. www.onsemi.com 8 NCP3063, NCP3063B, NCV3063 (See Notes 9, 10, 11) ton toff Step−Down Step−Up Voltage−Inverting Vout ) VF Vin * VSWCE * Vout Vout ) VF * Vin Vin * VSWCE |Vout| ) VF Vin * VSWCE ton toff ton toff ton ton toff f ǒton ) 1Ǔ f ǒton ) 1Ǔ t f ǒton ) 1Ǔ t off t off CT 10 *6 CT + 381.6 @ fosc off * 343 @ 10 *12 ǒ Ǔ ǒ Ǔ IL(avg) Iout t Iout on ) 1 toff t Iout on ) 1 toff Ipk (Switch) DI IL(avg) ) L 2 DI IL(avg) ) L 2 DI IL(avg) ) L 2 RSC 0.20 Ipk (Switch) 0.20 Ipk (Switch) 0.20 Ipk (Switch) L * Vout ǒVin * VSWCE Ǔ ton DIL ǒVin *DIVLSWCEǓ ton ǒVin *DIVLSWCEǓ ton Vripple(pp) DIL Vout Ǹǒ 1 8 f CO VTH Ǔ ) (ESR) 2 2 [ ǒRR2 ) 1Ǔ ton Iout ) DIL @ ESR CO VTH 1 ǒRR2 ) 1Ǔ 1 [ ton Iout ) DIL @ ESR CO VTH ǒRR2 ) 1Ǔ 1 9. VSWCE − Darlington Switch Collector to Emitter Voltage Drop, refer to Figures 7, 8, 9 and 10. 10. VF − Output rectifier forward voltage drop. Typical value for 1N5819 Schottky barrier rectifier is 0.4 V. 11. The calculated ton/toff must not exceed the minimum guaranteed oscillator charge to discharge ratio. The Following Converter Characteristics Must Be Chosen: Vin − Nominal operating input voltage. Vout − Desired output voltage. Iout − Desired output current. DIL − Desired peak−to−peak inductor ripple current. For maximum output current it is suggested that DIL be chosen to be less than 10% of the average inductor current IL(avg). This will help prevent Ipk (Switch) from reaching the current limit threshold set by RSC. If the design goal is to use a minimum inductance value, let DIL = 2(IL(avg)). This will proportionally reduce converter output current capability. f − Maximum output switch frequency. Vripple(pp) − Desired peak−to−peak output ripple voltage. For best performance the ripple voltage should be kept to a low value since it will directly affect line and load regulation. Capacitor CO should be a low equivalent series resistance (ESR) electrolytic designed for switching regulator applications. Figure 15. Design Equations www.onsemi.com 9 NCP3063, NCP3063B, NCV3063 U201 8 N.C. SWC 7 SWE IPK 6 VCC TCAP 5 COMP GND R201 0R15 +VIN = +12 V 1 J201 C201 0.1 mF + C202 220 mF / 50 V 1 2 L201 +VOUT = +3.3 V / 800 mA 47 mH 1 3 4 C203 2.2 nF NCP3063 C206 D201 1N5819 0.1 mF J203 + C205 470 mF / 25 V 1 J202 GND R203 1 GND J204 3K9 ±1% R202 2K4 ±1% Figure 16. Typical Buck Application Schematic Value of Components Name Value Name Value L201 47 mH, Isat > 1.5 A R201 150 mW, 0.5 W D201 1 A, 40 V Schottky Rectifier R202 2.40 kW C202 220 mF, 50 V, Low ESR R203 3.90 kW C205 470 mF, 25 V, Low ESR C201 100 nF Ceramic Capacitor C203 2.2 nF Ceramic Capacitor C202 100 nF Ceramic Capacitor Test Results Test Condition Results Line Regulation Vin = 9 V to 12 V, Io = 800 mA 8 mV Load Regulation Vin = 12 V, Io = 80 mA to 800 mA 9 mV Output Ripple Vin = 12 V, Io = 40 mA to 800 mA ≤ 85 mVpp Efficiency Vin = 12 V, Io = 400 mA to 800 mA > 73% Short Circuit Current Vin = 12 V, Rload = 0.15 W 1.25 A 76 EFFICIENCY (%) 74 72 70 68 66 64 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OUTPUT LOAD (Adc) onsemi Figure 18. Efficiency vs. Output Current for the Buck Demo Board at Vin = 12 V, Vout = 3.3 V, TA = 255C Figure 17. Buck Demoboard Layout www.onsemi.com 10 NCP3063, NCP3063B, NCV3063 L101 R101 0R15 +VIN = +12 V 8 7 6 5 1 J101 C101 0.1 mF + C102 470 mF / 25 V 100 mH U101 N.C. SWC 1 SWE 2 IPK 3 VCC TCAP COMP GND 4 D101 C106 C103 0.1 mF 2.2 nF NCP3063 +VOUT = +24 V / 350 mA 1N5819 1 J103 + C105 330 mF / 50 V J104 1 J102 GND R103 1 GND R102 1K0 ±1% 18K0 ±1% Figure 19. Typical Boost Application Schematic Value of Components Name Value Name Value L101 100 mH, Isat > 1.5 A R101 150 mW, 0.5 W D101 1 A, 40 V Schottky Rectifier R102 1.00 kW C102 470 mF, 25 V, Low ESR R103 18.00 kW C105 330 mF, 50 V, Low ESR C101 100 nF Ceramic Capacitor C103 2.2 nF Ceramic Capacitor C106 100 nF Ceramic Capacitor Test Results Test Condition Results Line Regulation Vin = 9 V to 15 V, Io = 250 mA 2 mV Load Regulation Vin = 12 V, Io = 30 mA to 350 mA 5 mV Output Ripple Vin = 12 V, Io = 10 mA to 350 mA ≤ 350 mVpp Efficiency Vin = 12 V, Io = 50 mA to 350 mA > 85.5% 90 89 EFFICIENCY (%) 88 87 86 85 84 83 82 81 80 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 OUTPUT LOAD (Adc) onsemi Figure 21. Efficiency vs. Output Current for the Boost Demo Board at Vin = 12 V, Vout = 24 V, TA = 255C Figure 20. Boost Demoboard Layout www.onsemi.com 11 NCP3063, NCP3063B, NCV3063 U501 8 N.C. SWC 7 SWE IPK 6 VCC TCAP 5 COMP GND R501 0R15 +VIN = +5 V 1 J501 C501 0.1 mF + 1 2 3 4 NCP3063 C502 330 mF / 25 V J502 C503 L501 2.2 nF 22 mH D501 1N5819 VOUT = −12 V / 100 mA R503 1 1 J503 C506 1K96 ±1% GND R502 16K9 ±1% C505 + 470 mF / 35 V 0.1 mF 1 J504 GND Figure 22. Typical Voltage Inverting Application Schematic Value of Components Name Value Name Value L501 22 mH, Isat > 1.5 A R501 150 mW, 0.5 W D501 1 A, 40 V Schottky Rectifier R502 16.9 kW C502 330 mF, 25 V, Low ESR R503 1.96 kW C505 470 mF, 35 V, Low ESR C501 100 nF Ceramic Capacitor C503 2.2 nF Ceramic Capacitor C506 100 nF Ceramic Capacitor Test Results Test Condition Results Line Regulation Vin = 4.5 V to 6 V, Io = 50 mA 1.5 mV Load Regulation Vin = 5 V, Io = 10 mA to 100 mA 1.6 mV Output Ripple Vin = 5 V, Io = 0 mA to 100 mA ≤ 300 mVpp Efficiency Vin = 5 V, Io = 100 mA 49.8% Short Circuit Current Vin = 5 V, Rload = 0.15 W 0.885 A 52 EFFICIENCY (%) 50 48 46 44 42 40 38 36 0 20 40 60 80 100 OUTPUT LOAD (mAdc) onsemi Figure 24. Efficiency vs. Output Current for the Voltage Inverting Demo Board at Vin = +5 V, Vout = −12 V, TA = 255C Figure 23. Voltage Inverting Demoboard Layout www.onsemi.com 12 NCP3063, NCP3063B, NCV3063 VIN = 8 − 18 V/0.6 A R1 82m R2 1k L1 C5 IC1 NCP3063 8 N.C. SWC 1 7 SWE 2 IPK 6 TC 3 VCC 5 COMP GND 4 C3 C1 C2 R3 M18 330m 100n Q1 NTD18N06 D 6n8 R7 6 1G 470 2 4 5 3 D1 S IC2 BC846BPD 10n R5 1N5819 VOUT = 31 V/0.35 A 10m 24k C4 R4 1k R8 1k 1n2 C6 C7 + 100n 330m 0V GND Figure 25. Typical Boost Application Schematic with External NMOS Transistor 86 External transistor is recommended in applications where wide input voltage ranges and higher power is required. The suitable schematic with an additional NMOS transistor and its driving circuit is shown in the Figure 25. The driving circuit is controlled from SWE Pin of the NCP3063 through frequency compensated resistor divider R7/R8. The driver IC2 is onsemi low cost dual NPN/PNP transistor BC846BPD. Its NPN transistor is connected as a super diode for charging the gate capacitance. The PNP transistor works as an emitter follower for discharging the gate capacitor. This configuration assures sharp driving edge between 50 − 100 ns as well as it limits power consumption of R7/R8 divider down to 50 mW. The output current limit is balanced by resistor R3. The fast switching with low RDS(on) NMOS transistor will achieve efficiencies up to 85% in automotive applications. 84 EFFICIENCY (%) 82 80 78 76 74 72 70 ILOAD = 350 mA 6 8 10 12 14 16 18 20 INPUT VOLTAGE (V) Figure 26. Typical Efficiency for Application Shown in Figure 25. www.onsemi.com 13 NCP3063, NCP3063B, NCV3063 VIN = 8 − 19 V R1 Q2 NTGS4111P 50m T1 6 BC848CPD 2 R5 1k IC1 NCP3063 8 N.C. SWC 1 7 SWE 2 IPK 6 TC 3 VCC 5 COMP GND 4 R2 C1 + 330m C2 3 5 1 4 R6 22k 1k7 C5 R3 1k 100n VOUT = 3V3/3 A 10m L1 2n2 R8 470 C4 6n8 D1 1N5822 C6 100n 0V C7 + 330m GND Figure 27. Typical Buck Application Schematic with External PMOS Transistor Figure 27 shows typical buck configuration with external PMOS transistor. The principle of driving the Q2 gate is the same as shown in Figure 27. Resistor R6 connected between TC and SWE pin provides a pulsed feedback voltage. It is recommended to use this pulsed feedback approach on applications with a wide input voltage range, applications with the input voltage over +12 V or applications with tighter specifications on output ripple. The suitable value of resistor R6 is between 10k − 68k. The pulse feedback approach increases the operating frequency by about 20%. It also creates more regular switching waveforms with constant operating frequency which results in lower output ripple voltage and improved efficiency. The pulse feedback resistor value has to be selected so that the capacitor charge and discharge currents as listed in the electrical characteristic table, are not exceeded. Improper selection will lead to errors in the oscillator operation. The maximum voltage at the TC Pin cannot exceed 1.4 V when implementing pulse feedback. 100 95 EFFICIENCY (%) 90 85 VIN = 8 V 80 VIN = 18 V 75 70 65 60 0 0.5 1 1.5 2 3 2.5 OUTPUT LOAD (Adc) Figure 28. NCP3063 Efficiency vs. Output Current for Buck External PMOS at Vout = 3.3 V, f = 220 kHz, TA = 255C www.onsemi.com 14 NCP3063, NCP3063B, NCV3063 R1 VIN = 8 − 19 V Q1 L1 NSS35200 150m D2 R4 33 NSR0130 IC1 NCP3063 8 N.C. SWC 1 7 SWE 2 IPK 6 TC 3 VCC 5 COMP GND 4 R3 C1 + C2 100m 100n VOUT = 3V3/1 A 33m R5 33 1k7 C3 R2 1k 2n2 D1 1N5819 C5 100n C6 + 100m 0V GND Figure 29. Typical Buck Application Schematic with External Low VCE(sat) PNP Transistor 100 Typical application of the buck converter with external bipolar transistor is shown in the Figure 29. It is an ideal solution for configurations where the input and output voltage difference is small and high efficiency is required. NSS35200, the low VCE(sat) transistor from onsemi will be ideal for applications with 1 A output current, the input voltages up to 15 V and operating frequency 100 − 150 kHz. The switching speed could be improved by using desaturation diode D2. 95 EFFICIENCY (%) 90 85 80 75 70 65 60 55 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 OUTPUT LOAD (Adc) 0.8 0.9 1 Figure 30. NCP3063 Efficiency vs. Output Current for External Low VCE(sat) at Vin = +5 V, f = 160 kHz, TA = 255C www.onsemi.com 15 NCP3063, NCP3063B, NCV3063 R1 IC1 NCP3063 8 N.C. SWC 7 SWE IPK 6 TC VCC 5 COMP GND 1 2 3 L1 4 R5 22k R2 C1 10R C2 R3 R4 C3 C4 D1 4n7 0V 0V Figure 31. Typical Schematic of Buck Converter with RC Snubber and Pulse Feedback In some cases where there are oscillations on the output due to the input/output combination, output load variations or PCB layout a snubber circuit on the SWE Pin will help minimize the oscillation. Typical usage is shown in the Figure 31. C3 values can be selected between 2.2 nF and 6.8 nF and R4 can be from 10 W to 22 W. ORDERING INFORMATION Package Shipping† NCP3063PG PDIP−8 (Pb−Free) 50 Units / Rail NCP3063BPG PDIP−8 (Pb−Free) 50 Units / Rail NCP3063BMNTXG DFN−8 (Pb−Free) 4000 / Tape & Reel NCP3063DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel NCP3063BDR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel NCP3063MNTXG DFN−8 (Pb−Free) 4000 / Tape & Reel NCV3063PG PDIP−8 (Pb−Free) 50 Units / Rail NCV3063DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel NCV3063MNTXG DFN−8 (Pb−Free) 4000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NCV prefix is for automotive and other applications requiring site and change control. www.onsemi.com 16 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN8, 4x4 CASE 488AF−01 ISSUE C 1 SCALE 2:1 A B D PIN ONE REFERENCE 2X 0.15 C 2X 0.15 C 0.10 C 8X ÉÉ ÉÉ ÉÉ 0.08 C DETAIL A E OPTIONAL CONSTRUCTIONS EXPOSED Cu DETAIL B ÇÇÇÇ (A3) A A1 C D2 ÇÇÇÇ e 8X SEATING PLANE ÉÉÉ ÉÉÉ ÇÇÇ A3 A1 ALTERNATE CONSTRUCTIONS 8X MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.25 0.35 4.00 BSC 1.91 2.21 4.00 BSC 2.09 2.39 0.80 BSC 0.20 −−− 0.30 0.50 −−− 0.15 XXXXXX XXXXXX ALYWG G E2 5 DIM A A1 A3 b D D2 E E2 e K L L1 GENERIC MARKING DIAGRAM* L 4 ÇÇÇÇ 8 MOLD CMPD DETAIL B SIDE VIEW K ÇÇÇ ÇÇÇ ÉÉÉ TOP VIEW 1 NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. DETAILS A AND B SHOW OPTIONAL CONSTRUCTIONS FOR TERMINALS. L L L1 NOTE 4 DETAIL A DATE 15 JAN 2009 b XXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW SOLDERING FOOTPRINT* 2.21 8X *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 0.63 4.30 2.39 PACKAGE OUTLINE 8X 0.35 0.80 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON15232D DFN8, 4X4, 0.8P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PDIP−8 CASE 626−05 ISSUE P DATE 22 APR 2015 SCALE 1:1 D A E H 8 5 E1 1 4 NOTE 8 b2 c B END VIEW TOP VIEW WITH LEADS CONSTRAINED NOTE 5 A2 A e/2 NOTE 3 L SEATING PLANE A1 C D1 M e 8X SIDE VIEW b 0.010 eB END VIEW M C A M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY. 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). DIM A A1 A2 b b2 C D D1 E E1 e eB L M INCHES MIN MAX −−−− 0.210 0.015 −−−− 0.115 0.195 0.014 0.022 0.060 TYP 0.008 0.014 0.355 0.400 0.005 −−−− 0.300 0.325 0.240 0.280 0.100 BSC −−−− 0.430 0.115 0.150 −−−− 10 ° MILLIMETERS MIN MAX −−− 5.33 0.38 −−− 2.92 4.95 0.35 0.56 1.52 TYP 0.20 0.36 9.02 10.16 0.13 −−− 7.62 8.26 6.10 7.11 2.54 BSC −−− 10.92 2.92 3.81 −−− 10 ° NOTE 6 GENERIC MARKING DIAGRAM* STYLE 1: PIN 1. AC IN 2. DC + IN 3. DC − IN 4. AC IN 5. GROUND 6. OUTPUT 7. AUXILIARY 8. VCC XXXXXXXXX AWL YYWWG XXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98ASB42420B PDIP−8 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 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