DATA SHEET
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Constant Current Step-Up/
Step-Down/Inverting
Switching Regulator for
HB-LEDs
MARKING
DIAGRAMS
8
1
SOIC−8
D SUFFIX
CASE 751−07
1.5 A
3065
ALYWG
G
1
V3065
ALYWG
G
1
NCP3065, NCV3065
The NCP3065 is a monolithic switching regulator designed to
deliver constant current for powering high brightness LEDs. The
device has a very low feedback voltage of 235 mV (nominal) which is
used to regulate the average current of the LED string. In addition, the
NCP3065 has a wide input voltage up to 40 V to allow it to operate
from 12 Vac or 12 Vdc supplies commonly used for lighting
applications as well as unregulated supplies such as Lead Acid
batteries. The device can be configured in a controller topology with
the addition of an external transistor to support higher LED currents
beyond the 1.5 A rated switch current of the internal transistor. The
NCP3065 switching regulator can be configured in Step−Down
(Buck) and Step−Up (Boost) topologies with a minimum number of
external components.
Features
•
•
•
•
•
•
•
•
•
•
Integrated 1.5 A Switch
Input Voltage Range from 3.0 V to 40 V
Low Feedback Voltage of 235 mV
Cycle−by−Cycle Current Limit
No Control Loop Compensation Required
Frequency of Operation Adjustable up to 250 kHz
Operation with All Ceramic Output Capacitors or No Output Capacitance
Analog and Digital PWM Dimming Capability
Internal Thermal Shutdown with Hysteresis
Automotive Version Available
8
1
NCP3065
AWL
YYWWG
NCV3065
AWL
YYWWG
NCP
3065
ALYW G
G
NCV
3065
ALYW G
G
PDIP−8
P, P1 SUFFIX
CASE 626
1
DFN−8
MN SUFFIX
CASE 488 AF
A
L, WL
Y, YY
W, WW
G or G
=
=
=
=
=
Assembly Location
Wafer Lot
Year
Work Week
Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
Applications
•
•
•
•
Automotive and Marine Lighting
High Power LED Driver
Constant Current Source
Low Voltage LED Lighting
(Landscape, Path, Solar, MR16 Replacement)
+LED
Rs
0.15 W
Vin
NCP3065
NC SWC
Ipk
SWE
CT
Vin
COMP GND
R
D
Cout
22 mF
LED
Cluster
D
−LED
Vth = 0.235 V
Cin
220 mF
D
L
CT
2.2 nF
Rsense
0.68 W
Figure 1. Typical Buck Application Circuit
© Semiconductor Components Industries, LLC, 2011
October, 2021 − Rev. 5
1
Publication Order Number:
NCP3065/D
NCP3065, NCV3065
1
Switch Collector
Switch Emitter
2
8
N.C.
7
Ipk Sense
Timing Capacitor
3
6
GND
4
5
ÇÇ
ÇÇ
ÇÇ
ÇÇ
Switch Collector
Switch Emitter
Timing Capacitor
VCC
GND
Comparator
Inverting
Input
(Top View)
EP Flag
Ç
Ç
Ç
Ç
(Top View)
Figure 2. Pin Connections
N.C.
Ipk Sense
VCC
Comparator
Inverting
Input
Figure 3. Pin Connections
NCP3065
8
1
TSD
N.C.
Switch Collector
SET dominant
R
S
7
Ipk Sense
Q
COMPARATOR
−
+
S
R
2
Switch Emitter
Q
SET dominant
0.2 V
OSCILLATOR
6
3
Timing Capacitor
CT
+VCC
COMPARATOR
0.235 V
REFERENCE
REGULATOR
+
−
5
4
GND
Comparator Inverting Input
Figure 4. Block Diagram
PIN DESCRIPTION
Pin No.
Pin Name
1
Switch Collector
2
Switch Emitter
3
Timing Capacitor
4
GND
5
Comparator
Inverting Input
6
VCC
7
Ipk Sense
8
N.C.
Description
Internal Darlington switch collector
Internal Darlington switch emitter
Timing Capacitor Oscillator Input, Timing Capacitor
Ground pin for all internal circuits
Inverting input pin of internal comparator
Voltage supply
Peak Current Sense Input to monitor the voltage drop across an external resistor to limit the peak
current through the circuit
Pin not connected
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NCP3065, NCV3065
MAXIMUM RATINGS (measured vs. pin 4, unless otherwise noted)
Symbol
Value
Unit
VCC (Pin 6)
VCC
0 to +40
V
Comparator Inverting Input (Pin 5)
VCII
−0.2 to +VCC
V
Darlington Switch Collector (Pin 1)
VSWC
0 to +40
V
Darlington Switch Emitter (Pin 2) (Transistor OFF)
VSWE
−0.6 to +VCC
V
Darlington Switch Collector to Emitter (Pins 1−2)
VSWCE
0 to +40
V
Darlington Switch Current
ISW
1.5
A
Ipk Sense (Pin 7)
VIPK
−0.2 to VCC + 0.2
V
VTCAP
−0.2 to +1.4
V
PDIP−8
Thermal Resistance Junction−to−Air
RqJA
100
SOIC−8
Thermal Resistance Junction−to−Air
RqJA
180
DFN−8
Thermal Resistance Junction−to−Air
Thermal Resistance Junction−to−Case
RqJA
RqJC
78
14
Storage Temperature Range
TSTG
−65 to +150
°C
TJ(MAX)
+150
°C
Rating
Timing Capacitor (Pin 3)
Power Dissipation and Thermal Characteristics
Maximum Junction Temperature
Operating Junction Temperature Range (Note 3)
NCP3065, NCV3065
TJ
−40 to +125
°C/W
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Pin 1−8: Human Body Model 2000 V per AEC Q100−002; 003 or JESD22/A114; A115
Machine Model Method 200 V
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
3. The relation between junction temperature, ambient temperature and Total Power dissipated in IC is TJ = TA + Rq • PD
4. The pins which are not defined may not be loaded by external signals
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3
NCP3065, NCV3065
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TJ = −40°C to +125°C, unless otherwise specified)
Conditions
Symbol
Min
Typ
Max
Unit
(VPin 5 = 0 V, CT = 2.2 nF,
TJ = 25°C)
fOSC
110
150
190
kHz
Discharge to Charge Current Ratio
(Pin 7 to VCC, TJ = 25°C)
IDISCHG /
ICHG
5.5
6.0
6.5
−
Capacitor Discharging Current
(Pin 7 to VCC, TJ = 25°C)
IDISCHG
1650
mA
Capacitor Charging Current
(Pin 7 to VCC, TJ = 25°C)
ICHG
275
mA
Current Limit Sense Voltage
(TJ = 25°C) (Note 6)
VIPK(Sense)
(ISW = 1.0 A,
TJ = 25°C) (Note 5)
Characteristic
OSCILLATOR
Frequency
165
185
235
mV
VSWCE(DROP)
1.0
1.3
V
(VCE = 40 V)
IC(OFF)
0.01
100
mA
TJ = 25°C
VTH
235
mV
±5
%
OUTPUT SWITCH (Note 5)
Darlington Switch Collector to
Emitter Voltage Drop
Collector Off−State Current
COMPARATOR
Threshold Voltage
TJ = 0 to +85°C
Threshold Voltage Line Regulation
Input Bias Current
TJ = −40°C to +125°C
VTH
−10
+10
%
(VCC = 3.0 V to 40 V)
REGLiNE
−6.0
6.0
mV
(Vin = Vth)
ICII in
−1000
1000
nA
(VCC = 5.0 V to 40 V,
CT = 2.2 nF, Pin 7 = VCC,
VPin 5 > Vth, Pin 2 = GND,
remaining pins open)
ICC
7.0
mA
−100
TOTAL DEVICE
Supply Current
Thermal Shutdown Threshold
160
°C
Hysteresis
10
°C
5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible.
6. The VIPK(Sense) Current Limit Sense Voltage is specified at static conditions. In dynamic operation the sensed current turn−off value depends
on comparator response time and di/dt current slope. See the Operating Description section for details.
7. NCV prefix is for automotive and other applications requiring site and change control.
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NCP3065, NCV3065
450
190
400
180
FREQUENCY (kHz)
FREQUENCY (kHz)
350
300
250
200
150
100
170
160
150
140
130
120
50
0
110
0 1 2 3 4 5 6 7 8 9 10 11 12 1314 1516 1718 1920
7
12
16
21
25
29
34
38 40
VCC, SUPPLY VOLTAGE (V)
Figure 5. Oscillator Frequency vs. Oscillator
Timing Capacitor
Figure 6. Oscillator Frequency vs. Supply
Voltage
1.25
VCC = 5.0 V
IE = 1 A
VCC = 5.0 V
IC = 1 A
1.20
VOLTAGE DROP (V)
2.2
VOLTAGE DROP (V)
3
Ct, CAPACITANCE (nF)
2.4
2.0
1.8
1.6
1.4
1.15
1.10
1.05
1.2
1.0
−50
0
50
100
1.0
−50
150
0
50
100
150
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Emitter Follower Configuration Output
Darlington Switch Voltage Drop vs. Temperature
Figure 8. Common Emitter Configuration Output
Darlington Switch Voltage Drop vs. Temperature
1.5
2.0
1.9
1.4
VCC = 5.0 V
TJ = 25°C
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.2
0.7
1.1
1.0
0.6
0.5
0
VCC = 5.0 V
TJ = 25°C
1.3
VOLTAGE DROP (V)
1.8
VOLTAGE DROP (V)
CT = 2.2 nF
TJ = 25°C
0.5
1.0
1.5
0
0.5
1.0
IE, EMITTER CURRENT (A)
IC, COLLECTOR CURRENT (A)
Figure 9. Emitter Follower Configuration Output
Darlington Switch Voltage Drop vs. Emitter Current
Figure 10. Common Emitter Configuration
Output Darlington Switch Voltage Drop vs.
Collector Current
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5
1.5
0.25
0.30
Vipk(sense), CURRENT LIMIT SENSE
VOLTAGE (V)
Vth, COMPARATOR THRESHOLD VOLTAGE (V)
NCP3065, NCV3065
0.245
0.24
0.235
0.23
0.225
0.22
−50 −30 −10
10
30
50
70
90
110 130 150
0.28
0.26
0.24
0.22
0.20
0.18
0.16
0.14
0.12
0.10
−40 −25 −10
TJ, JUNCTION TEMPERATURE (°C)
5
20
ICC, SUPPLY CURRENT (mA)
5.5
5.0
4.5
4.0
3.5
CT = 2.2 nF
Pin 5, 7 = VCC
Pin 2 = GND
3.0
2.5
8.0
65
80
95
110 125
Figure 12. Current Limit Sense Voltage vs.
Temperature
6.0
3.0
50
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Comparator Threshold Voltage vs.
Temperature
2.0
35
13
18
23
28
33
38
43
VCC, SUPPLY VOLTAGE (V)
Figure 13. Standby Supply Current vs. Supply Voltage
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NCP3065, NCV3065
INTRODUCTION
comparator value, the output switch cycle is inhibited. When
the load current causes the output voltage to fall below the
nominal value feedback comparator enables switching
immediately. Under these conditions, the output switch
conduction can be enabled for a partial oscillator cycle, a
partial cycle plus a complete cycle, multiple cycles, or a
partial cycle plus multiple cycles.
The NCP3065 is a monolithic power switching regulator
optimized for LED Driver applications. Its flexible
architecture enables the system designer to directly
implement a step−up or step−down topology with a
minimum number of external components for driving LEDs.
A representative block diagram is shown in Figure 4.
OPERATING DESCRIPTION
The NCP3065 operates as a fixed oscillator frequency
output voltage ripple gated regulator. In general, this mode
of operation is somewhat analogous to a capacitor charge
pump and does not require dominant pole loop
compensation for converter stability. The typical operating
waveforms are shown in Figure 14. The output voltage
waveform shown is for a step−down converter with the
ripple and phasing exaggerated for clarity. During initial
converter startup, the feedback comparator senses that the
output voltage level is below nominal. This causes the
output switch to turn on and off at a frequency and duty cycle
controlled by the oscillator, thus pumping up the output filter
capacitor. When the feedback voltage level reaches nominal
Feedback Comparator Output
Oscillator
The oscillator frequency and off−time of the output switch
are programmed by the value of the timing capacitor CT.
Capacitor CT is charged and discharged by a 1 to 6 ratio
internal current source and sink, generating a positive going
sawtooth waveform at Pin 3. This ratio sets the maximum
tON/(tON+tOFF) of the switching converter as 6/(6+1) or
85.7% (typical). The oscillator peak and valley voltage
difference is 500 mV typically. To calculate the CT capacitor
value for required oscillator frequency, use the equations
found in Figure 22. An online NCP3065 design tool can be
found at www.onsemi.com, which adds in selecting
component values.
1
0
1
IPK Comparator Output
0
Timing Capacitor, CT
Output Switch
On
Off
Nominal Output Voltage Level
Output Voltage
Startup
Operation
Figure 14. Typical Operating Waveforms
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NCP3065, NCV3065
Peak Current Sense Comparator
LED Dimming
Under normal conditions, the output switch conduction is
initiated by the Voltage Feedback comparator and
terminated by the oscillator. Abnormal operating conditions
occur when the converter output is overloaded or when
feedback voltage sensing is lost. Under these conditions, the
Ipk Current Sense comparator will protect the Darlington
output Switch. The switch current is converted to a voltage
by inserting a fractional ohm resistor, RSC, in series with
VCC and the Darlington output switch. The voltage drop
across RSC is monitored by the Current Sense comparator.
If the voltage drop exceeds 200 mV (nom) with respect to
VCC, the comparator will set the latch and terminate the
output switch conduction on a cycle−by−cycle basis. This
Comparator/Latch configuration ensures that the Output
Switch has only a single on−time during a given oscillator
cycle.
The COMP pin of the NCP3065 is used to provide
dimming capability. In digital input mode the PWM input
signal inhibits switching of the regulator and reduces the
average current through the LEDs. In analog input mode a
PWM input signal is RC filtered and the resulting voltage is
summed with the feedback voltage thus reduces the average
current through the LEDs. Figure 15 illustrated the linearity
of the digital dimming function with a 200 Hz digital PWM.
For further information on dimming control refer to
application note AND8298.
Vipk(sense)
Io
24 Vin, Vf = 3.6 V
600
500
12 Vin, Vf = 3.6 V
400
I1
di/dt slope
24 Vin, Vf = 7.2 V
700
ILED (mA)
Real
Vturn−off on
Rs Resistor
800
300
I through the
Darlington
Switch
200
100
t_delay
0
0
10
20
30
40
50
60
70
80
90 100
DUTY CYCLE (%)
The VIPK(Sense) Current Limit Sense Voltage threshold is
specified at static conditions. In dynamic operation the
sensed current turn−off value depends on comparator
response time and di/dt current slope.
Real Vturn−off on Rsc resistor
Figure 15.
No Output Capacitor Operation
A constant current buck regulator such as the NCP3065
focuses on the control of the current through the load, not the
voltage across it. The switching frequency of the NCP3065
is in the range of 100−250 kHz which is much higher than
the human eye can detect. This allows us to relax the ripple
current specification to allow higher peak to peak values.
This is achieved by configuring the NCP3065 in a
continuous conduction buck configuration with low peak to
peak ripple thus eliminating the need for an output filter
capacitor. The important design parameter is to keep the
peak current below the maximum current rating of the LED.
Using 15% peak to peak ripple results in a good compromise
between achieving max average output current without
exceeding the maximum limit. This saves space and reduces
part count for applications that require a compact footprint.
(Example: See Figure 17) See application note AND8298
for more information.
Vturn_off + Vipk(sense) ) Rsc @ (t_delay @ dińdt)
Typical Ipk comparator response time t_delay is 350 ns.
The di/dt current slope is dependent on the voltage
difference across the inductor and the value of the inductor.
Increasing the value of the inductor will reduce the di/dt
slope.
It is recommended to verify the actual peak current in the
application at worst conditions to be sure that the max peak
current will never get over the 1.5 A Darlington Switch
Current max rating.
Thermal Shutdown
Internal thermal shutdown circuitry is provided to protect
the IC in the event that the maximum junction temperature
is exceeded. When activated, typically at 165°C, the
Darlington Output Switch is disabled. The temperature
sensing circuit is designed with some hysteresis. The
Darlington Switch is enabled again when the chip
temperature decreases under the low threshold. This feature
is provided to prevent catastrophic failures from accidental
device overheating. It is not intended to be used as a
replacement for proper heatsinking.
Output Switch
The output switch is designed in a Darlington
configuration. This allows the application designer to
operate at all conditions at high switching speed and low
voltage drop. The Darlington Output Switch is designed to
switch a maximum of 40 V collector to emitter voltage and
current up to 1.5 A.
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NCP3065, NCV3065
APPLICATIONS
Figures 16 through 24 show the simplicity and flexibility
of the NCP3065. Two main converter topologies are
demonstrated with actual test data shown below each of the
circuit diagrams.
(See Notes 8, 9, 10)
ton
toff
Figure 16 gives the relevant design equations for the key
parameters. Additionally, a complete application design aid
for the NCP3065 can be found at www.onsemi.com.
Step−Down
Step−Up
Vout ) VF
Vin * VSWCE * Vout
Vout ) VF * Vin
Vin * VSWCE
ton
toff
ton
toff
ton
f ǒton ) 1Ǔ
f ǒton ) 1Ǔ
t
t
off
off
CT
*6
CT + 381.6 @ 10 * 343 @ 10 *12
fosc
ǒ
Ǔ
IL(avg)
Iout
t
Iout on ) 1
toff
Ipk (Switch)
DI
IL(avg) ) L
2
DI
IL(avg) ) L
2
RSC
0.20
Ipk (Switch)
0.20
Ipk (Switch)
L
* Vout
ǒVin * VSWCE
Ǔ ton
DIL
ǒVin *DIVLSWCEǓ ton
Vripple(pp)
DIL
Vout
I out
Ǹǒ
1
8 f CO
VTH
Ǔ ) (ESR)
2
2
ǒRR2 ) 1Ǔ
[
ton Iout
) DIL @ ESR
CO
VTH
1
V refńR sense
ǒRR2 ) 1Ǔ
1
V refńR sense
8. VSWCE − Darlington Switch Collector to Emitter Voltage Drop, refer to Figures 7, 8, 9 and 10.
9. VF − Output rectifier forward voltage drop. Typical value for 1N5819 Schottky barrier rectifier is 0.4 V.
10. The calculated ton/toff must not exceed the minimum guaranteed oscillator charge to discharge ratio.
Figure 16. Design Equations
The Following Converter Characteristics Must Be Chosen:
Vin − Nominal operating input voltage.
Vout − Desired output voltage.
Iout − Desired output current.
DIL − Desired peak−to−peak inductor ripple current. For maximum output current it is suggested that DIL be chosen to be
less than 10% of the average inductor current IL(avg). This will help prevent Ipk (Switch) from reaching the current limit threshold
set by RSC. If the design goal is to use a minimum inductance value, let DIL = 2(IL(avg)). This will proportionally reduce
converter output current capability.
f − Maximum output switch frequency.
Vripple(pp) − Desired peak−to−peak output ripple voltage. For best performance the ripple voltage should be kept to a low
value since it will directly affect line and load regulation. Capacitor CO should be a low equivalent series resistance (ESR)
electrolytic designed for switching regulator applications.
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NCP3065, NCV3065
NTF2955
Q4
MMBT3904LT1G
Q5
R15
6x 1R0 ±1%R
0R10
R1
J2
R2
R3
R4
R5
R6
R7
1206 1206 1206 1206 1206 1206 1206
1
+VIN
J3
C4
U1
8 N.C. SWC 1
7
SWE 2
IPK
6
3
VCC TCAP
5 COMP GND 4
+
D2
+VAUX
R8
CT
D1
R14
NU
R9
Q1
C1
1208 0.1 mF
C3
1.8 nF
C5
BC807−LT1G
470 mH
15 k
+
C6
NU
J5
1
R10
0805
10 k
100 pF
1k
R13
NU
Q2
R12
RSENSE ±1%
J6
R11
1
ON/OFF
J6
R11
1
+LED
MBRS140LT3G
1
GND
J4
1
J1
1
L1
NCP3065
SOIC8
C2
220 mF / 50 V
0.1 mF
MMSD4148
1k
−LED
J7
1
GND
BC817−LT1G
Figure 17. Buck Demo Board with External Switch Application Schematic
ON/OFF
This design illustrates the NCP3065 being used as a PFET
controller, the design has been optimized for continuous
current operation with low ripple which allows the output
filter capacitor to be eliminated. Figure 20 illustrates the
efficiency with 1 and 2 LEDs and output currents of 350 mA
and 700 mA. Additional data and design information can be
found of this design in Application Note AND8298.
Value of Components
Name
Value
Name
Value
C1, C4
100 nF, Ceramic Capacitor, 1206
Q5
MMBT3904LT1G, SOT23
C2
220 mF, 50 V, Electrolytic Capacitor
R1
100 mW, 0.5 W
C3
1.8 nF, Ceramic Capacitor, 0805
R8
15 k, resistor 0805
C5
100 pF, Ceramic Capacitor, 0805
R9
10 kW, resistor 0805
D1
1 A, 40 V Schottky Rectifier
R10, R15
1 kW, resistor 0805
D2
MMSD4148
R11
1.2 kW, resistor 0805
L1
470 mH, DO5022P−474ML Coilcraft Inductor
R12
RSENSE ±1%, 1206
Q4
NTF2955, P−MOSFET, SOT223
U1
NCP3065, SOIC8
NOTE: RSENSE is used to select LED output current, for 350 mA use 680 mW, for 700 mA use 330 mW and for 1000 mA use 220 mW
Test Results (without output capacitor)
Test
Condition
Results
Line Regulation
Vin = 9 V to 19 V, Io = 350 mA
12 mA
Load Regulation
Vin = 12 V, Io = 350 mA, Vo = 3 V to 8 V
13 mA
Output Ripple
Vin = 9 V to 19 V, Io = 350 mA
< 15% IO
Efficiency
Vin = 12 V, Io = 350 mA, VOUT = 3 to 8 V
> 75%
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NCP3065, NCV3065
88
EFFICIENCY (%)
84
VOUT = 7.2 V, No Output Cap
80
76
72
68
VOUT = 3.6 V, No Output Cap
64
60
4
8
12
16
20
24
28
32
36
VIN, INPUT VOLTAGE (V)
Figure 19. Efficiency vs. Input Voltage for the 1.5 A
Buck Demo Board at Iout = 700 mA, TA = 255C,
Without Output Capacitor
Figure 18. 1.5 A Buck Demoboard Layout
88
88
84
84
VOUT = 7.2 V, Output Cap 100 mF
EFFICIENCY (%)
EFFICIENCY (%)
80
76
72
68
64
VOUT = 3.6 V, Output Cap 100 mF
60
56
4
8
12
16
20
24
VOUT = 7.2 V, Output Cap 100 mF
80
76
72
VOUT = 3.6 V, Output Cap 100 mF
68
64
28
32
60
36
4
8
12
16
20
24
28
32
36
VIN, INPUT VOLTAGE (V)
VIN, INPUT VOLTAGE (V)
Figure 20. Efficiency vs. Input Voltage for the 1.5 A
Buck Demo Board at Iout = 350 mA, TA = 255C, with
100 mF Output Capacitor
Figure 21. Efficiency vs. Input Voltage for the 1.5 A
Buck Demo Board at Iout = 700 mA, TA = 255C, with
100 mF Output Capacitor
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11
NCP3065, NCV3065
L1
6x 1R0 ±1%R
0R15
R1
R2
R3
R4
R5
100 mH
R6
R7
J2
1
C5
+VIN
J4
+
C3
220 mF / 50 V
0.1 mF
1
U1
8 N.C. SWC
7
SWE
IPK
6
VCC TCAP
5 COMP GND
1
2
3
4
NCP3065
MBRS140LT3G
D1
C4
2.2 nF
J1
1
+LED
C2
+
C1
100 mF /
50 V
0.1 mF
R8
GND
GND
1k0
J6
1
R9
RSENSE
BC807−LT1G BC817−LT1G
J5
1
D2
−LED
+VAUX
Q1
Q2
R10
1
ON/OFF 1k2
J7
R10
1
1k2
ON/OFF
MM3Z36VT1G
R11
NU
J7
Figure 22. Boost Demo Board Application Schematic
Value of Components
Name
Value
Name
Value
C1
100 mF/50 V, Electrolytic Capacitor
Q2
BC817−LT1G, SOT23
C2, C5
100 nF, Ceramic Capacitor, 1206
R1
150 mW, resistor 0.5 W
C3
220 mF/50 V, Electrolytic Capacitor
R8
1 k, resistor 0805
C4
2.2 nF, Ceramic Capacitor, 0805
R9
Load current sense resistor, 1206
D1
MBRS140LT3G, Schottky diode
R10
1.2 k, resistor 0805
D2
MMSZ36VT1G, Zener diode
U1
NCP3065, SOIC8
L1
100 mH, DO3340P−104ML Coilcraft Inductor
Test Results
Test
J3
1
Condition
Results
Line Regulation
Vin = 10 V to 20 V, Vo = 22 V, IOAVG = 350 mA
25 mA
Output Ripple
Vin = 8 V to 20 V, Vo = 22 V, IOAVG = 350 mA
50 mA
Efficiency
Vin = 10 to 20 V, IOAVG = 350 mA
> 83 %
www.onsemi.com
12
NCP3065, NCV3065
95
93
EFFICIENCY (%)
91
89
87
85
83
81
79
77
75
8
10
12
14
16
18
20
VIN, INPUT VOLTAGE (V)
Figure 24. Efficiency vs. Input Voltage for the
Boost Demo Board at IOUT = 350 mA,
VOUT = 22 V (6xLED with VF = 3.6 V), TA = 255C
Figure 23. Boost Demoboard Layout
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13
22
NCP3065, NCV3065
MTB30P06V
Q4
MMBT3904LT1G
Q5
R15
6x 1R0 ±1%R
0R04
R1
J2
R2
R3
R4
R5
+VIN
J3
R6
U1
8 N.C. SWC 1
7
SWE 2
IPK
6
3
VCC TCAP
5 COMP GND 4
R7
1206 1206 1206 1206 1206 1206
1
C4
+
C7 +
1 mF / 50 V
C2
220 mF / 50 V
0.1 mF
+VAUX
Q1
Q2
R8
15 k
C3
1.8 nF
L1
C5
R9
1k
R16
0R15 ±1%
R13
NU
C6
J5
1
R10
R12
0R15 ±1%
J6
R11
1
1k2
ON/OFF 0805
J6
R11
1
1k2
ON/OFF 0805
+
220 mF /
50 V
100 pF
0805
10 k
0805
+LED
C1
1206 0.1 mF
D1
MBRS140LT3G
R14
NU
J1
1
PF0504.223NL
CT
NCP3065
SOIC8
0.1 mF
BC807−LT1G BC817−LT1G
D2
C8
1
GND
J4
1
MMSD4148
1k
−LED
J7
1
GND
Figure 25. Buck Demoboard with External Switch Application Schematic
Value of Components
Name
Value
Name
Value
C1
100 mF, 50 V, Electrolytic Capacitor
Q4
MTB30P06V, P−MOS transistor
C1, C4, C8
100 nF, Ceramic Capacitor, 1206
Q5
MMBT3904LT1G
C2, C6
220 mF, 50 V, Electrolytic Capacitor
R1
40 mW, Resistor 0.5 W
C3
2.2 nF, Ceramic Capacitor, 0805
R8
6k8, Resistor 0805
C5
100 pF, Ceramic Capacitor, 0805
R9
10k, Resistor 0805
C7
1 mF / 50 V, Ceramic Capacitor, 1206
R10
1k, Resistor 0805
D1
MBRS540LT3G, Schottky Diode
R11
1k2, Resistor 0805
D2
MMSD4148T1G, Diode
R12, R16
150 mW, Resistor 0.5 W
L1
22 mH
U1
NCP3065, SOIC8
Q2
BC817−LT1G, SOT23
Test Results
Test
Condition
Results
Line Regulation
Vin = 8 V to 19 V, Io = 3000 mA
< 6%
Output Ripple
Vin = 12 V, Io = 3000 mA
< 6%
Efficiency
Vin = 12 V, Io = 3000 mA
> 78%
Short Circuit Current
Vin = 12 V, Rload = 0.15 W
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14
NCP3065, NCV3065
EFFICIENCY (%)
90
88
86
84
82
80
78
76
74
72
70
68
66
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
VIN, INPUT VOLTAGE (v)
Figure 27. Efficiency vs. Input Voltage for the
3 A Buck Demo Board at IOUT = 3 A,
VOUT = 4 V, TA = 255C
Figure 26. 3 A Buck Demoboard Layout
ORDERING INFORMATION
Package
Shipping†
NCP3065MNTXG
DFN−8
(Pb−Free)
4000 Units / Tape & Reel
NCP3065PG
PDIP−8
(Pb−Free)
50 Units / Rail
NCP3065DR2G
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
NCV3065MNTXG
DFN−8
(Pb−Free)
4000 Units / Tape & Reel
NCV3065PG
PDIP−8
(Pb−Free)
50 Units / Rail
NCV3065DR2G
SOIC−8
(Pb−Free)
2500 Units / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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15
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8, 4x4
CASE 488AF−01
ISSUE C
1
SCALE 2:1
A
B
D
PIN ONE
REFERENCE
2X
0.15 C
2X
0.15 C
0.10 C
8X
ÉÉ
ÉÉ
ÉÉ
0.08 C
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
EXPOSED Cu
DETAIL B
ÇÇÇÇ
(A3)
A
A1
C
D2
ÇÇÇÇ
e
8X
SEATING
PLANE
ÉÉÉ
ÉÉÉ
ÇÇÇ
A3
A1
ALTERNATE
CONSTRUCTIONS
8X
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.25
0.35
4.00 BSC
1.91
2.21
4.00 BSC
2.09
2.39
0.80 BSC
0.20
−−−
0.30
0.50
−−−
0.15
XXXXXX
XXXXXX
ALYWG
G
E2
5
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
GENERIC
MARKING DIAGRAM*
L
4
ÇÇÇÇ
8
MOLD CMPD
DETAIL B
SIDE VIEW
K
ÇÇÇ
ÇÇÇ
ÉÉÉ
TOP VIEW
1
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. DETAILS A AND B SHOW OPTIONAL CONSTRUCTIONS FOR TERMINALS.
L
L
L1
NOTE 4
DETAIL A
DATE 15 JAN 2009
b
XXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.10 C A B
0.05 C
NOTE 3
BOTTOM VIEW
SOLDERING FOOTPRINT*
2.21
8X
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.63
4.30 2.39
PACKAGE
OUTLINE
8X
0.35
0.80
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON15232D
DFN8, 4X4, 0.8P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP−8
CASE 626−05
ISSUE P
DATE 22 APR 2015
SCALE 1:1
D
A
E
H
8
5
E1
1
4
NOTE 8
b2
c
B
END VIEW
TOP VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
e/2
NOTE 3
L
SEATING
PLANE
A1
C
D1
M
e
8X
SIDE VIEW
b
0.010
eB
END VIEW
M
C A
M
B
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.355 0.400
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
9.02
10.16
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
NOTE 6
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. AC IN
2. DC + IN
3. DC − IN
4. AC IN
5. GROUND
6. OUTPUT
7. AUXILIARY
8. VCC
XXXXXXXXX
AWL
YYWWG
XXXX
A
WL
YY
WW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42420B
PDIP−8
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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