NCP308SN330T1G

Low Quiescent Current, Programmable Delay Time, Supervisory Circuit NCP308, NCV308 The NCP308 series is one of the ON Semiconductor Supervisory circuit IC families. It is optimized to monitor system voltages from 0.405 V to 5.5 V, asserting an active low open−drain RESET output, together with Manual Reset (MR) Input. The part comes with both fixed and externally adjustable versions. www.onsemi.com MARKING DIAGRAMS Features • Wide Supply Voltage Range 1.6 to 5.5 V • Very Low Quiescent Current 1.6 mA • Fixed Threshold Voltage Versions for Standard Voltage Rails • • • • • • • • • 1 Including 0.9 V, 1.2 V, 1.25 V, 1.5 V, 1.8 V, 1.9 V, 2.5 V, 2.8 V, 3.0 V, 3.3 V, 5.0 V Adjustable Version with Low Threshold Voltage 0.405 V (min) High Threshold Voltage Accuracy: 0.31% typ Support Manual Reset Input ( MR) Open−Drain RESET Output (Push−pull Output upon Request) Flexible Delay Time Programmability: 1.25 ms to 10 s Temperature Range: −40°C to +125°C Small TSOP−6 and WDFN6 2 x 2 mm, Pb−Free packages NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These are Pb−Free Devices Typical Applications • • • • • TSOP−6 CASE 318G XXXAYWG G 1 WDFN6 CASE 511BR 1 XX M G XXX, XX= Specific Device Code A =Assembly Location Y = Year W = Work Week M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the ordering information section on page 9 of this data sheet. DSP or Microcontroller Applications Notebook/Desktop Computers PDAs/Hand−Held Products Portable/Battery−Powered Products FPGA/ASIC Applications VIN VIN VDD NCP308XXADJ VDD RESET Rpullup VDD RESET RESET DSP/ Processor SENSE 1 nF (Optional) Rpullup RESET R1 R2 VDD MR MR CT GND DSP/ Processor SENSE CT MR (Optional) Figure 1. Typical Application Circuit for Adjustable Versions © Semiconductor Components Industries, LLC, 2014 December, 2020 − Rev. 9 MR CT GND CT (Optional) Figure 2. Typical Application Circuit for Fixed Versions 1 Publication Order Number: NCP308/D NCP308, NCV308 VDD VDD NCP308SNADJ/NCP308MTADJ Adjustable Versions VDD VDD 90k CT 90k NCP308SNXXX/NCP308MTXXX Fixed Versions CT MR MR − SENSE RESET Control Logic and Timer + − SENSE R1 Vref Vref GND GND R2 RESET Control Logic and Timer + Figure 3. Functional Block Diagrams of Adjustable and Fixed Versions 1 RESET 6 VDD GND 2 5 SENSE MR 3 4 CT VDD 1 6 RESET SENSE 2 5 GND CT 3 4 MR Figure 4. Pin Connections Diagram (Top View) Table 1. PIN OUT DESCRIPTION Pin Number Name TSOP−6 WDFN6 VDD 6 1 Supply Voltage. A 0.1uF ceramic capacitor placed close to this pin is helpful for transient and parasitic. SENSE 5 2 Sense Input, this is the voltage to be monitored. If the voltage at this terminal drops below the threshold voltage VIT, then RESET is asserted. SENSE does not necessary monitor VDD, it can monitor any voltage lower than VDD. CT 4 3 Reset Delay Time Setting Pin. Connecting this pin to VDD through a 40 kW to 200 kW resistor or leaving it open results in fixed reset delay times. Connecting this pin to a ground referenced capacitor (≥ 100 pF) gives a user−programmable reset delay time. See the Setting Reset Delay Time section for more information. MR 3 4 Manual Reset input, MR low asserts RESET. MR is internally tied to VDD by a 90 kW pull−up Resistor. RESET 1 6 RESET Output, is an Active low open drain N−Channel MOSFET output, it is driven to a low impedance state when RESET is asserted (either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low). RESET will keep low (asserted) for the reset delay time after both SENSE is above VIT and MR is set to a logic high. A pull−up resistor from 10kW to 1MW should be used on this pin. See Figure 5 for behavior of RESET depends on VDD, SENSE and MR conditions. GND 2 5 Ground terminal. Should be connected to PCB ground reference EXP PAD − Exposed Pad Description Exposed pad, under WDFN6 package, connect it to ground plane for better thermal dissipation. www.onsemi.com 2 NCP308, NCV308 Uncertain State VDD VDD(min) 0.0 V RESET tD SENSE tP2 tD VIT + VHYS VIT tP1 tD MR 0.7 VDD 0.3 VDD Figure 5. Timing Diagram Showing MR and SENSE Reset Timing Table 2. TRUTH TABLE MR SENSE > VIT RESET L N L L Y L H N L H Y H www.onsemi.com 3 NCP308, NCV308 Table 3. MAXIMUM RATINGS Symbol Value Unit Input voltage range, VDD Rating VDD −0.3 to + 6.0 V CT voltage range VCT, RESET, MR Current through CT pin ICT −0.3 to VDD +0.3 ≤ 6.0 10 V mA SENSE pin voltage −0.3 to + 8.0 V RESET pin current 5 mA Thermal Resistance Junction−to−Air TSOP−6 WDFN6 RqJA 305 220 °C/W Human Body Model (HBM) ESD Rating (Note 1) ESD HBM 2000 V Machine Model (MM) ESD Rating (Note 1) ESD MM 100 V ESD CDM 500 Charged Device Model (CDM) ESD Rating (Note 1) Latch up Current: (Note 2) All pins, except digital pins Digital pins (MR) ILU Storage Temperature Range Maximum Junction Temperature Moisture Sensitivity (Note 3) ±100 ±10 V mA TSTG −65 to + 150 °C TJ −40 to +150 °C MSL Level 1 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) +/−2.0 kV per JEDEC standard: JESD22−A114 Machine Model (MM) +/−100 V per JEDEC standard: JESD22−A115 Charged Device Model (CDM) 500 V per JEDEC standard: JESD22−C101. 2. Latch up Current per JEDEC standard: JESD78 class II. 3. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A. www.onsemi.com 4 NCP308, NCV308 Table 4. ELECTRICAL CHARACTERISTICS 1.6 V ≤ VDD ≤ 5.5 V, Rpullup = 100 kW, CLRESET = 50 pF, over operating temperature range (TJ = −40°C to +125°C), unless otherwise specified. Typical values are at TJ = +25°C. Parameter Symbol VDD Supply Voltage Range VDD(min) Minimum VDD Guaranteed RESET Output Valid (Note 4) IDD Supply Current (Current into VDD pin) VOL Low−level output voltage of RESET VIT% Negative going SENSE threshold voltage accuracy Conditions Min −40°C < TJ < +125°C 1.6 Typ Max Unit 5.5 V 0.5 0.8 V VDD = 3.3V, RESET not asserted MR, RESET, CT open 1.6 5.0 mA VDD = 5.5V, RESET not asserted MR, RESET, CT open 1.6 6.0 1.3V ≤ VDD < 1.6V, IOL = 0.4 mA 0.3 1.6V ≤ VDD ≤ 5.5V, IOL = 1.0 mA VHYS RMR ISENSE Hysteresis on VIT 0.4 −1.75 ±0.75 +1.75 TJ = +25°C −0.31 − 0.31 −20°C < TJ < +85°C −1.0 ±0.5 +1.0 1.6V≤VDD≤4.2V 1.0 3.0 4.2V≤VDD≤5.5V 1.75 3.75 MR Internal pull−up resistance Input current at SENSE pin V % %VIT 90 kW NCP308XXADJ VSENSE = VIT 10 nA Fixed versions VSENSE = 5.5 V 110 IOH RESET leakage Current CIN Input capacitance, any pin VRESET = 5.5 V, RESET not asserted 300 CT pin VIN = 0 V to VDD 5 Other pins VIN = 0 V to 5.5 V 5 nA pF VIL MR logic low input 0 0.3 VDD V VIH MR logic high input 0.7 VDD VDD V tw Input pulse width to assert RESET SENSE VIH = 1.05 VIT, VIL = 0.95 VIT 20 MR VIH = 0.7 VDD, VIL = 0.3 VDD 150 tD Reset delay time CT = Open CT = VDD CT = 100 pF CT = 180 nF (Guaranteed by design and characterization) 20 300 1.25 1200 ms tP1 Propagation delay from MR MR to RESET VIH = 0.7 VDD, VIL = 0.3 VDD 150 ns tP2 Propagation delay from SENSE SENSE to RESET VIH = 1.05 VIT, VIL = 0.95 VIT 20 ms 4. The lowest supply voltage (VDD) at which RESET becomes active. 5. NCP308XX: XX = MT (WDFN6 package) or SN (TSOP−6 package). www.onsemi.com 5 ms NCP308, NCV308 TYPICAL OPERATING CHARACTERISTICS 4.0 10000 3.5 3.0 1000 +125°C 2.0 +85°C 1.5 −40°C +85°C 10 −40°C 1.0 +25°C 0.5 1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VDD (V) 3.5 4.0 4.5 0 0.1 5.0 5.5 Figure 6. Supply Current vs. Input Voltage 20 15 10 5.0 0 −5.0 −10 −50 −30 −10 10 30 50 70 TEMPERATURE (°C) 90 110 10.0 (nF) 100.0 1000.0 100 10 1 0.1 130 0 Figure 8. Normalized RESET Timeout Period vs. Temperature 5 10 15 20 25 30 35 OVERDRIVE (%VIT) 40 45 50 Figure 9. Maximum Transient Duration at Sense vs. Sense Threshold Overdrive Voltage −30 −10 10 30 50 70 90 110 130 VOL LOW−LEVEL RESET VOLTAGE (V) 0.5 NORMALIZED VIT (%) 3.0 2.5 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 −2.5 −3.0 −50 1.0 Figure 7. RESET Timeout Period vs. CT TRANSIENT DURATION BELOW VIT (ms) NORMALIZED RESET TIMEOUT PERIOD (%) +125°C +25°C 100 (ms) IDD (mA) 2.5 0.4 VDD = 1.6 V 0.3 VDD = 5.5 V 0.2 VDD = 3.3 V 0.1 0.0 0.0 0.5 1.0 1.5 2.0 TEMPERATURE (°C) RESET CURRENT (mA) Figure 10. Normalized Sense Threshold Voltage (VIT) vs. Temperature Figure 11. Low−Level RESET Voltage vs. RESET Current www.onsemi.com 6 NCP308, NCV308 DETAILED DESCRIPTION SENSE Input The NCP308 microprocessor supervisory product family is designed to assert a RESET signal when either the SENSE pin voltage drops below VIT or the Manual Reset input (MR) is driven low. The RESET output remains asserted for a programmable delay time after both MR and SENSE voltages return above the respective thresholds. A broad range of voltage threshold and reset delay time options are available, allowing NCP308 series to be used in a wide range of applications. Reset threshold voltages can be factory−set from 0.82 V to 3.3 V or from 4.4 V to 5.0 V, while the NCP308XXADJ can be used for any voltage above 0.405 V using an external resistor divider. Flexible delay time can be easily got with CT pin according to Table 5: The SENSE input should be connected to the monitored voltage directly. If the voltage on this pin drops below VIT, then RESET is asserted. The comparator has a built−in hysteresis to prevent erratic reset operation. It is good practice to put a 1 nF to 10 nF bypass capacitor on the SENSE input to reduce its sensitivity to transients and layout parasitic. The NCP308XXADJ can be used to monitor any voltage rail down to 0.405 V by the circuit shown in Figure 12. The new VIT’ can be derived from resistor divider network of R1 and R2 by: V ITȀ + CT pin Configuration Delay Time (tD) CT = VDD 300 ms (fixed) CT = Open 20 ms (fixed) Connecting a capacitor between pin CT and GND (Capacitor CT value > 100 pF) 1.25 ms ~ 10 s, depends on capacitor value (Refer to the Setting Reset Delay Time Section) R2 V IT (eq. 1) VDD VIN Table 5. DELAY TIME SETTING TABLE ǒR1 ) 1Ǔ NCP308XXADJ VDD Rpullup RESET R1 SENSE 1 nF (Optional) R2 CT CT (Optional) MR MR GND Output The RESET output is typically connected to the RESET control pin of a microprocessor. For Open−Drain output versions, a pull−up resistor must be used to hold this line high when RESET is not asserted. The RESET output is active once VDD is over VDD(min), this voltage is much lower than most microprocessors’ functional voltage range. RESET remains high as long as SENSE is above its threshold (VIT) and the Manual Reset input (MR) is logic high. If either SENSE falls below VIT or MR is driven low, RESET is asserted. Once MR is again logic high and SENSE is above (VIT + VHYS), the RESET pin goes to a high impedance state after delay time (tD). The open−drain structure of RESET is capable to allow the reset signal for the microprocessor to have a voltage higher than VDD (up to 5.5 V). The pull−up resistor should be no smaller than 10 kW as a result of the finite impedance of the RESET line. Figure 12. Using NCP308XXADJ to Monitor a User−Defined Threshold Voltage Manual Reset Input (MR) The Manual Reset input (MR) allows a processor or other logic circuits to initiate a reset. A logic low on MR causes RESET to assert. After MR returns to a logic high and SENSE is above its reset threshold, RESET is de−asserted after the delay time set by CT pin. MR is internally tied to VDD by a 90 kW resistor so this pin can be left unconnected if MR will not be used. Figure 13 shows how MR can be used to monitor multiple system voltages (e.g. I/O supply voltage of some DSP/processors should be setup before core voltage, and DSP/processor can only start after both I/O and core voltages setup). www.onsemi.com 7 NCP308, NCV308 1.2 V 3.3 V Vcore VIO VDD VDD RESET RESET RESET DSP/ Processor SENSE MR SENSE CT CT MR GND NCP308XX120 GND NCP308XX330 Figure 13. Using MR to Monitor Multiple System Voltages Setting Reset Delay Time 3.3V The NCP308 has three options for setting the reset delay time as shown in Table 5. Figure 14 shows the configuration for a fixed 300 ms typical delay time by tying CT to VDD; a resistor from 40 kW to 200 kW must be used. Figure 15 shows a fixed 20 ms delay time by leaving the CT pin unconnected. Figure 16 shows a user−defined program time between 1.25 ms and 10 s by connecting a capacitor between CT pin and ground. Rpullup VDD SENSE 3.3 V MR Rpullup VDD MR RESET CT GND Figure 15. Delay Time Fixed to 20 ms when CT is Open 50k RESET 3.3 V SENSE MR CT Rpullup MR GND VDD Figure 14. Delay Time Fixed to 300 ms when CT Connected to VDD by Resistor SENSE RESET CT CT MR MR GND Figure 16. Delay Time Set by Capacitor The capacitor CT should be ≥ 100 pF for NCP308 to recognize that the capacitor is present. The capacitor value for a given delay time can be calculated using the following equation: www.onsemi.com 8 NCP308, NCV308 CT(nF) + ǒtD(s) * 0.5 10 −3(s)Ǔ 175 threshold overdrive, as shown in the Maximum Transient Duration at Sense vs. Sense Threshold Overdrive Voltage graph (Figure 9) in Typical Operating Characteristics section. (eq. 2) Parasitic capacitances of CT pin should be considered to avoid reset delay time deviation or error. Immunity to Sense Pin Voltage Transients NCP308 is relatively immune to short negative transients on SENSE pin. Sensitivity to transients is dependent on ORDERING INFORMATION Status (Note 6) Threshold Voltage (VIT) Nominal Monitored Voltage NCP308SNADJT1G Active 0.405 V ADJ NCV308SNADJT1G* Active 0.405 V Adjustable Version NCP308SN090T1G Active 0.84 V 0.9 V 090 NCP308SN120T1G Active 1.12 V 1.2 V 120 NCP308SN125T1G Active 1.16 V 1.25 V 125 NCP308SN150T1G Active 1.40 V 1.5 V 150 NCP308SN180T1G Active 1.67 V 1.8 V 180 NCP308SN190T1G Active 1.77 V 1.9 V 190 NCP308SN250T1G Active 2.33 V 2.5 V 250 NCP308SN280T1G Active 2.61 V 2.8 V 280 NCP308SN300T1G Active 2.79 V 3.0 V 300 NCP308SN330T1G Active 3.07 V 3.3 V 330 NCV308SN330T1G* Active 3.07 V 3.3 V 33A NCP308SN500T1G Active 4.65 V 5.0 V 500 NCP308MTADJTBG Active 0.405 V Adjustable Version AA NCP308MT090TBG Active 0.84 V 0.9 V AC NCP308MT120TBG Active 1.12 V 1.2 V AD NCP308MT125TBG Active 1.16 V 1.25 V AE NCP308MT150TBG Active 1.40 V 1.5 V AF NCP308MT180TBG Active 1.67 V 1.8 V AG NCP308MT190TBG Active 1.77 V 1.9 V AH NCP308MT250TBG Active 2.33 V 2.5 V AJ NCP308MT280TBG Active 2.61 V 2.8 V AK NCP308MT300TBG Active 2.79 V 3.0 V AL NCP308MT330TBG Active 3.07 V 3.3 V AM NCP308MT500TBG Active 4.65 V 5.0 V AN Device Marking Package Shipping† VDJ TSOP−6 (Pb−Free) 3000 / Tape & Reel WDFN6 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. 6. The marketing status are defined as below: Active: Products in production and recommended for new designs; Under Request: Device has been announced but is not in production. Samples may or may not be available. www.onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE V 1 SCALE 2:1 D H ÉÉ ÉÉ 6 E1 1 NOTE 5 5 2 L2 4 GAUGE PLANE E 3 L b SEATING PLANE C DETAIL Z e DIM A A1 b c D E E1 e L L2 M c A 0.05 M DATE 12 JUN 2012 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. A1 DETAIL Z MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10° − STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 2: PIN 1. EMITTER 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. BASE 2 6. COLLECTOR 2 STYLE 3: PIN 1. ENABLE 2. N/C 3. R BOOST 4. Vz 5. V in 6. V out STYLE 4: PIN 1. N/C 2. V in 3. NOT USED 4. GROUND 5. ENABLE 6. LOAD STYLE 5: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 6: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 7: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. N/C 5. COLLECTOR 6. EMITTER STYLE 8: PIN 1. Vbus 2. D(in) 3. D(in)+ 4. D(out)+ 5. D(out) 6. GND STYLE 9: PIN 1. LOW VOLTAGE GATE 2. DRAIN 3. SOURCE 4. DRAIN 5. DRAIN 6. HIGH VOLTAGE GATE STYLE 10: PIN 1. D(OUT)+ 2. GND 3. D(OUT)− 4. D(IN)− 5. VBUS 6. D(IN)+ STYLE 11: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1/GATE 2 STYLE 12: PIN 1. I/O 2. GROUND 3. I/O 4. I/O 5. VCC 6. I/O STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN 1 STYLE 14: PIN 1. ANODE 2. SOURCE 3. GATE 4. CATHODE/DRAIN 5. CATHODE/DRAIN 6. CATHODE/DRAIN STYLE 15: PIN 1. ANODE 2. SOURCE 3. GATE 4. DRAIN 5. N/C 6. CATHODE STYLE 16: PIN 1. ANODE/CATHODE 2. BASE 3. EMITTER 4. COLLECTOR 5. ANODE 6. CATHODE STYLE 17: PIN 1. EMITTER 2. BASE 3. ANODE/CATHODE 4. ANODE 5. CATHODE 6. COLLECTOR GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 XXXAYWG G 1 6X 3.20 XXX A Y W G 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB14888C TSOP−6 1 IC 0.95 XXX MG G = Specific Device Code =Assembly Location = Year = Work Week = Pb−Free Package STANDARD XXX = Specific Device Code M = Date Code G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WDFN6 2x2, 0.65P CASE 511BR ISSUE C DATE 01 DEC 2021 GENERIC MARKING DIAGRAM* 1 XX M XX = Specific Device Code M = Date Code *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON55829E WDFN6 2X2, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com ◊ TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative