NCP3127AGEVB

NCP3127 2 A Synchronous PWM Switching Converter The NCP3127 is a flexible synchronous PWM Switching Buck Regulator. The NCP3127 is capable of producing output voltages as low as 0.8 V. The NCP3127 also incorporates voltage mode control. Switching frequency is internally set. The NCP3127 is currently available in an SOIC−8 package. http://onsemi.com Features • • • • • • • • • • MARKING DIAGRAM 8 4.5 V to 13.2 V Operating Input Voltage Range 80 mW High−Side and Low−Side Switch Output Voltage Adjustable to 0.8 V 2 A Continuous Output Current Fixed 350 kHz PWM Operation 1.0% Initial Output Accuracy 75% Max Duty Ratio Over−Load Protection Programmable Current Limit This is a Pb−Free Device 1 SOIC−8 NB AL SUFFIX CASE 751 3127 A L Y W G Typical Application • • • • • 8 3127 ALYW G 1 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS Set Top Boxes DVD Drives and HDD LCD Monitors and TVs Cable Modems Telecom / Networking / Datacom Equipment NCP3127 1 PGND VSW FB ISET COMP VIN AGND BST (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 23 of this data sheet. 100 BST VIN VSW 3.3 V PGND NCP3127 ISET COMP 95 EFFICIENCY (%) 4.5 V − 13.2 V FB1 AGND 5V 90 85 80 75 70 65 April, 2011 − Rev. 2 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 OUTPUT CURRENT (A) Figure 1. Typical Application Circuit © Semiconductor Components Industries, LLC, 2011 0 Figure 2. Efficiency (VIN = 12 V) vs. Load Current 1 Publication Order Number: NCP3127/D NCP3127 CIRCUIT DESCRIPTION BST VIN + − − + UVLO POR 10 mA VREF Fault + OLP Latch − + 0.8 V FB VOCTH + Fault PWM Comp − R PWM OUT − Q S COMP VSW Counter DtoA Clock Ramp Count Latch & Logic − + + + − − 2V OSC VCC VREG OSC + 0.7 V − Fault AGND Figure 3. NCP3127 Block Diagram ISET PGND Table 1. PIN DESCRIPTION Pin Pin Name Description 1 PGND 2 FB nverting input to the Operational Transconductance Amplifier (OTA). The FB pin in conjunction with the external compensation, serves to stabilize and achieve the desired output voltage with voltage mode compensation. 3 COMP COMP pin is used to compensate the OTA which stabilizes the operation of the converter stage. Place compensation components as close to the converter as possible. 4 AGND The AGND pin serves as small−signal ground. All small−signal ground paths should connect to the AGND pin at a single point, avoiding any high current ground returns. 5 BST Supply rail for the floating top gate driver. To form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to BST pin). Connect a capacitor (CBST) between this pin and the VSW pin. Typical values for CBST range from 1 nF to 10 nF. Ensure that CBST is placed near the IC. 6 VIN The VIN pin powers the internal control circuitry and is monitored by an undervoltage comparator. The VIN pin is also connected to the internal power NMOSFET switches. The VIN pin has high dI/dt edges and must be decoupled to PGND pin close to the pin of the device. 7 ISET Current set pin and bottom gate MOSFET driver. Place a resistor to ground to set the current limit of the converter. 8 VSW The VSW pin is the connection of the drain and source of the internal N−MOSFETs. The VSW pin swings from VIN when the high side switch is on to small negative voltages when the low side switch is on with high dV/dt transitions. The PGND pin is the high current ground pin for the low−side MOSFET and the drivers. The pin should be soldered to a large copper area to reduce thermal resistance. http://onsemi.com 2 NCP3127 Table 2. MAXIMUM RATINGS Rating Symbol Min Max Unit VIN −0.3 15 V VBST −0.3 30 V Bootstrap Supply Voltage vs Ground (spikes ≤ 50 ns) VBST spike −0.3 35 V Bootstrap Pin Voltage vs VSW Main Supply Voltage Input Bootstrap Supply Voltage vs GND VBST − VSW −0.3 15 V High Side Switch Max DC Current IVSW 0 3.5 V VSW Pin Voltage VSW −0.7 35 V Switch Pin voltage (spikes < 50 ns) VSWtr −5.0 40 V VFB −0.3 5.5 < VCC V VCOMP/DIS −0.3 5.5 < VCC V VISET −0.3 15 < VCC V VISET Spike −2 15 < VCC V FB Pin Voltage COMP/DISABLE Low Side Driver Pin Voltage Low Side Driver Pin Voltage (spikes v 200 ns) Rating Symbol Rating Unit RqJA 110 183 °C/W Thermal Resistance, Junction−to−Case RqJC 170 °C/W Storage Temperature Range Tstg −55 to 150 °C Junction Operating Temperature TJ −40 to +125 °C Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free RF 260 peak °C Thermal Resistance, Junction−to−Ambient (Note 2) (Note 3) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The maximum package power dissipation limit must not be exceeded. T J(max) * T A PD + R qJA 2. The value of qJA is measured with the device mounted on 1 in2 FR−4 board with 1 oz. copper, in a still air environment with TA = 25°C. The value in any given application depends on the user’s specific board design. 3. The value of qJA is measured with the device mounted on minimum footprint, in a still air environment with TA = 25°C. The value in any given application depends on the user’s specific board design. 4. 60−180 seconds minimum above 237°C. http://onsemi.com 3 NCP3127 Table 3. ELECTRICAL CHARACTERISTICS (−40°C < TJ < 125°C; VIN = 12 V, BST−VSW = 12 V, BST = 12 V, VSW = 24 V, for min/max values unless otherwise noted.) Conditions Min Max Unit Input Voltage Range VIN − GND 4.5 13.2 V Boost Voltage Range VBST − GND 4.5 26.5 V VFB = 1.0 V, No Switching, VIN = 13.2 V 1.0 − 10.0 mA − 4.0 − mA VFB = 1.0 V, No Switching, VIN = 13.2 V 0.1 − 1.0 mA VIN UVLO Threshold VIN Rising Edge 3.8 − 4.3 V VIN UVLO Hysteresis − − 430 − mV VFB Feedback Voltage, Control Loop in Regulation TJ = 0 to 25°C, 4.5 V < VCC < 13.2 V −40°C v TJ v 125°C, 4.5 v VCC v 13.2 V 0.792 0.784 0.800 0.800 0.808 0.816 mV Oscillator Frequency TJ = 0 to 25°C, 4.5 V < VCC < 13.2 V −40°C v TJ v 125°C, 4.5 v VCC v 13.2 V 300 290 350 350 400 410 kHz 0.8 1.1 1.4 V Minimum Duty Ratio − 5.5 − % Maximum Duty Ratio 70 75 80 % Transconductance 3.0 − 5 ms Open Loop DC Gain 55 70 − dB 80 80 125 125 200 200 mA − 0.16 1.0 mA 0.3 0.4 0.5 V 3.0 − 15 ms Characteristic Typ SUPPLY CURRENT Quiescent Supply Current Shutdown Supply Current Boost Quiescent Current UNDER VOLTAGE LOCKOUT SWITCHING REGULATOR Ramp−Amplitude Voltage PWM COMPENSATION Output Source Current Output Sink Current VFB < 0.8 V VFB > 0.8 V Input Bias Current ENABLE Enable Threshold SOFT−START Delay to Soft−Start SS Source Current VFB < 0.8 V − 10.5 − mA Switch Over Threshold VFB = 0.8 V − 100 − % of Vref Sourced from ISET pin, before SS − 10 − mA OC Switch−Over Threshold − 700 − mV Fixed OC Threshold − 375 OVER−CURRENT PROTECTION OCSET Current Source mV PWM OUTPUT STAGE High−Side Switch On−Resistance VIN = 12 V (Note 5) VIN = 5 V (Note 5) 80 105 140 175 mW Low−Side Switch On−Resistance VIN = 12 V (Note 5) VIN = 5 V (Note 5) 80 105 140 175 mW 5. Guaranteed by design. http://onsemi.com 4 NCP3127 TYPICAL CHARACTERISTICS 25 5.0 23 4.0 VCC = 12 V 3.5 3.0 VCC = 5 V 2.5 21 19 17 15 13 0 20 40 60 80 9 100 120 140 VCC = 5 V 0 30 40 50 60 Figure 4. ICC vs. Temperature Figure 5. Input Current Switching vs. Temperature 70 808 806 Vref, REFERENCE (mV) 12 11 10 9 804 802 800 798 796 794 0 10 20 30 40 50 60 TJ, JUNCTION TEMPERATURE (°C) 792 70 0 10 20 30 40 50 60 70 TJ, JUNCTION TEMPERATURE (°C) Figure 6. Soft−Start Sourcing Current vs. Temperature Figure 7. Reference Voltage (Vref) vs. Temperature 6.0 375 5.0 365 DUTY CYCLE (%) OLP THRESHOLD (mV) 20 TJ, JUNCTION TEMPERATURE (°C) 13 355 345 335 325 10 TJ, JUNCTION TEMPERATURE (°C) 14 8 VCC = 12 V 11 2.0 −60 −40 −20 SOFT−START SOURCING CURRENT (mA) INPUT CURRENT (mA) INPUT CURRENT (mA) 4.5 VCC = 12 V 4.0 VCC = 5 V 3.0 2.0 1.0 0 10 20 30 40 50 60 0 70 0 10 20 30 40 50 60 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 8. OLP Threshold vs. Temperature Figure 9. Minimum Active Duty Cycle vs. Temperature http://onsemi.com 5 70 NCP3127 TYPICAL CHARACTERISTICS 76 DUTY CYCLE (%) 75.5 VCC = 12 V 75 VCC = 5 V 74.5 74 73.5 73 0 10 20 30 40 50 60 70 TJ, JUNCTION TEMPERATURE (°C) Figure 10. Duty Cycle Maximum vs. Temperature 100 95 2.5 V 90 3.3 V 85 80 75 70 65 1.1 V 60 1.2 V 1.5 V 1.8 V 0 0.2 0.4 80 75 1.0 V 0.8 V 70 1.2 V 1.1 V 1.5 V 65 50 0.6 0.8 1 1.2 1.4 LOAD CURRENT (A) 1.6 1.8 2 0 Figure 11. Efficiency (VIN = 12 V) vs. Load Current 0.2 0.4 0.6 0.8 1 1.2 1.4 LOAD CURRENT (A) 1.8 2 2.5 1.2 V & 1.8 V 3.3 V 2 OUTPUT CURRENT (A) OUTPUT CURRENT (A) 1.6 Figure 12. Efficiency (VIN = 5 V) vs. Load Current 2.5 1.8 V 1.5 1.2 V 1 0.5 0 1.8 V 55 0.8 V 50 85 60 1.0 V 55 2.5 V Output 95 EFFICIENCY (%) EFFICIENCY (%) 90 100 5.0 V Output 25 35 45 55 65 75 2 1.5 3.3 V 1 0.5 0 85 5.0 V 25 35 45 55 65 75 TA, AMBIENT TEMPERATURE TA, AMBIENT TEMPERATURE Figure 13. Derating Curve 5 V/6 V Input Figure 14. Derating Curve 12 V Input http://onsemi.com 6 85 NCP3127 General COMP The NCP3127 is a PWM synchronous buck regulator intended to supply up to a 2 A load for DC−DC conversion from 5 V and 12 V buses. The NCP3127 is a regulator that has integrated high−side and low−side NMOSFETs switches. The output voltage of the converter can be precisely regulated down to 800 mV $1.0% when the VFB pin is tied to VOUT. The switching frequency is internally set to 350 kHz. A high gain operational transconductance amplifier (OTA) is used for voltage mode control of the power stage. Disable 2N7002E Gate Signal Enable COMP Duty Ratio and Maximum Pulse Width Limits Disable In steady state DC operation, the duty ratio will stabilize at an operating point defined by the ratio of the input to the output voltage. The device can achieve a 75% duty ratio. The NCP3127 has a preset off−time of approximately 150 ns, which ensures that the bootstrap supply is charged every switching cycle. The preset off time does not interfere with the conversion of 12 V to 0.8 V. Base Signal MMBT3904 Enable Figure 16. Recommended Disable Circuits Input Voltage Range (VIN and BST) The input voltage range for both VIN and BST is 4.5 V to 13.2 V with referenced to GND and VSW. Although BST is rated at 13.2 V with respect to VSW, it can also tolerate 26.5 V with respect to GND. Power Sequencing Power sequencing can be achieved with NCP3127 using two general purpose bipolar junction transistors or MOSFETs. An example of the power sequencing circuit using the external components is shown in Figure 17. External Enable/Disable Once the input voltage has exceeded the boost and UVLO threshold at 3 V and VIN threshold at 4 V, the COMP pin starts to rise. The VSW node is tri−stated until the COMP voltage exceeds 0.9 V. Once the 0.9 V threshold is exceeded, the part starts to switch and the part is considered enabled. When the COMP pin voltage is pulled below the 400 mV threshold, it disables the PWM logic, the top MOSFET is driven off, and the bottom MOSFET is driven on. In the disabled mode, the OTA output source current is reduced to 10 mA. When disabling the NCP3127 using the COMP / Disable pin, an open collector or open drain drive should be used as shown in Figure 16: VSW 1.0V VIN VSW NCP3127 FB1 NCP3127 FB1 COMP COMP 3.3 V Figure 17. Power Sequencing Input Voltage Shutdown Behavior Input voltage shutdown occurs when the IC stops switching because the input supply reaches UVLO threshold. Undervoltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when VCC is too low to support the internal rails and power the converter. For the NCP3127, the UVLO is set to permit operation when converting from an input voltage of 5 V. If the UVLO is tripped, switching stops, the internal SS is discharged, and all MOSFET gates are driven low. The VSW node enters a high impedance state and the output capacitors discharge through the load with no ringing on the output voltage. 0.9 V COMP BG External Soft−Start TG The NCP3127 features an external soft−start function, which reduces inrush current and overshoot of the output voltage. Soft−start is achieved by using the internal current Figure 15. Enable/Disable Driver State Diagram http://onsemi.com 7 NCP3127 source of 10 mA (typ), which charges the external integrator capacitor of the OTA. Figure 14 is a typical soft−start sequence. The sequence begins once VIN and VBST surpass their UVLO thresholds and OCP programming is complete. The current sourced out of the COMP pin continually increases the voltage until regulation is reached. Once the voltage reaches 400 mV logic is enabled. When the voltage exceeds 900 mV, switching begins. Current is sourced out of the COMP pin, placing the regulator into open loop operation until 800 mV is sensed at the FB pin. Once 800 mV is sensed at the FB pin, open loop operation ends and closed loop operation begins. In closed loop operation, the OTA is capable of sourcing and sinking 120 mA. 4.2 V IOCSET = Sourced current IOCth = Current trip threshold RDS(on) = On resistance of the low side MOSFET RSET = Current set resistor The RSET values range from 5 kW to 55 kW. If RSET is not connected, the device switches the OCP threshold to a fixed 375 mV value (3.57 A), an internal safety clamp on ISET is triggered as soon as ISET voltage reaches 700 mV, enabling the 375 mV fixed threshold and ending the OCP setting period. The current trip threshold tolerance is $25 mV. The accuracy is best at the highest set point (550 mV). The accuracy will decrease as the set point decreases. MOSFET tolerances with temperature and input voltage will vary the over current set threshold operating point. A graph of the typical current limit set thresholds at 4.5 V and 12 V is shown in Figure 19. 3.85 V VCC 0.9 V 4 COMP 3.5 OUTPUT CURRENT (A) VFB BG TG BG Comparator DAC Voltage 500 mV 50 mV BG Comparator Output Vout UVLO POR Current Soft−Start Normal Operation Delay Trip Set COMP Delay 3 2.5 2 1 0 5 NCP3127 overcurrent threshold can be set from 50 mV to 550 mV, by adding a resistor (RSET) between ISET and GND. During a short period of time following VIN rising over UVLO threshold, an internal 10 mA current (IOCSET) is sourced from the ISET pin, creating a voltage drop across RSET. The voltage drop is compared against a stepped internal voltage ramp. Once the internal stepped voltage reaches the RSET voltage, the value is stored internally until power is cycled. The overall time length for the OC setting procedure is approximately 9 ms. Connecting an RSET resistor between ISET and GND, the programmed threshold will be: R DS(on) ³ 2.0 A + 10 15 20 RSET (kW) 25 30 Figure 19. RSET Value for Output Current Overcurrent Threshold Setting I OCSET * R SET 5.0 V 1.5 0.5 UVLO Figure 18. Soft−Start Sequence I OCth + 12 V Current Limit Protection In case of an overload, the low−side (LS) FET will conduct large currents. The regulator will latch off, protecting the load and MOSFETs from excessive heat and damage. Low−side RDS(on) sense is implemented at the end of each LS−FET turn−on duration to sense the current. While the low side MOSFET is on, the VSW voltage is compared to the user set internally generated OCP trip voltage. If the VSW voltage is lower than OCP trip voltage, an overcurrent condition occurs and a counter counts consecutive current trips. If the counter reaches 7, the PWM logic and both HS−FET and LS−FET are turned off. The regulator has to go through a Power On Reset (POR) cycle to reset the OCP fault as shown in Figure 20. 10 mA * 21 kW 105 mW (eq. 1) http://onsemi.com 8 NCP3127 Current − BG Flow VOCTH + BG Drive Low Side MOSFET Current PHASE 0V VOCTH Figure 20. Current Limit Trip APPLICATION SECTION Design Procedure VOUT, VIN, the Low Side Switch Voltage Drop VLSD, and the High Side Switch Voltage Drop VHSD. When starting the design of a buck regulator, it is important to collect as much information as possible about the behavior of the input and output before starting the design. ON Semiconductor has a Microsoft Excel® based design tool available online under the design tools section of the NCP3127 product page. The tool allows you to capture your design point and optimize the performance of your regulator based on your design criteria. F SW + 1 T (VIN) Output voltage (VOUT) Input ripple voltage (VINRIPPLE) 300 mV Output ripple voltage (VOUTRIPPLE) 40 mV Output current rating (IOUT) 2A Operating frequency (FSW) 350 kHz T ON T and (1 * D) + OFF T T D+ V OUT ) V LSD V 3.3 V [ D + OUT ³ 27.5% + V IN * V HSD ) V LSD V IN 12 V D FSW T TOFF TON VHSD VIN VLSD VOUT Example Value Input voltage D+ (eq. 3) (eq. 4) Table 4. DESIGN PARAMETERS Design Parameter (eq. 2) 10.8 V to 13.2 V 3.3 V = Duty cycle = Switching frequency = Switching period = High side switch off time = High side switch on time = High side switch voltage drop = Input voltage = Low side switch voltage drop = Output voltage Inductor Selection When selecting an inductor, the designer can employ a rule of thumb for the design where the percentage of ripple current in the inductor should be between 10% and 40%. When using ceramic output capacitors, the ripple current can be greater because the ESR of the output capacitor is smaller, thus a user might select a higher ripple current. However, The buck converter produces input voltage VIN pulses that are LC filtered to produce a lower DC output voltage VOUT. The output voltage can be changed by modifying the on time relative to the switching period T or switching frequency. The ratio of high side switch on time to the switching period is called duty ratio D. Duty ratio can also be calculated using http://onsemi.com 9 NCP3127 when using electrolytic capacitors, a lower ripple current will result in lower output ripple due to the higher ESR of electrolytic capacitors. The ratio of ripple current to maximum output current is given in Equation 5. ra + DI Iout IOUT = Output current IPK = Inductor peak current ra = Ripple current ratio A standard inductor should be found so the inductor will be rounded to 12 mH. The inductor should also support an RMS current of 2.01 A and a peak current of 2.28 A. The final selection of an output inductor has both mechanical and electrical considerations. From a mechanical perspective, smaller inductor values generally correspond to smaller physical size. Since the inductor is often one of the largest components in the regulation system, a minimum inductor value is particularly important in space constrained applications. From an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by Equation 9. (eq. 5) DI = Ripple current IOUT = Output current ra = Ripple current ratio Using the ripple current rule of thumb, the user can establish acceptable values of inductance for a design using Equation 6. L OUT + V OUT @ (1 * D) ³ I OUT @ ra @ F SW 12.21 mH + INDUCTANCE (mH) D FSW IOUT LOUT ra 2.0 A (eq. 6) 12 V @ (1 * 27.5%) 28% 350 kHz SlewRate LOUT + 13 16 37 40 Ipp + Figure 21. Inductance vs. Current Ripple Ratio Ǹ1 ) ra12 ³ IOUT IRMS ra Ǹ1 ) (eq. 7) 2 = Output current = Inductor RMS current = Ripple current ratio ǒ I PK + I OUT @ 1 ) Ǔ (eq. 9) ǒ 3.3 V (1 * 27.5%) 12 mH @ 350 kHz (eq. 10) D = Duty ratio FSW = Switching frequency Ipp = Peak−to−peak current of the inductor LOUT = Output inductance VOUT = Output voltage From Equation 10 it is clear that the ripple current increases as LOUT decreases, emphasizing the trade−off between dynamic response and ripple current. The power dissipation of an inductor falls into two categories: copper and core losses. The copper losses can be further categorized into DC losses and AC losses. A good first order approximation of the inductor losses can be made using the DC resistance as shown below: 2 32% 2 V OUT (1 * D) ³ L OUT @ F SW 0.57 A + When selecting an inductor, the designer must not exceed the current rating of the part. To keep within the bounds of the part’s maximum rating, a calculation of the RMS and peak inductor current is required. 2.01 A + 2.01 A * ³ LOUT = Output inductance VIN = Input voltage VOUT = Maximum output voltage Equation 9 implies that larger inductor values limit the regulator’s ability to slew current through the output inductor in response to output load transients. Consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. Reduced inductance to increase slew rates results in larger values of output capacitance to maintain tight output voltage regulation. In contrast, smaller values of inductance increase the regulator’s maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. The peak−to−peak ripple current for NCP3127 is given by the following equation: 19 22 25 28 31 34 CURRENT RIPPLE RATIO (%) I RMS + I OUT @ L OUT 12 V * 3.3 V A 0.72 + ms 12 mH = Duty ratio = Switching frequency = Output current = Output inductance = Ripple current ratio 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 10 V IN * V OUT Ǔ ra 28% ³ 2.28 A + 2.0 A @ 1 ) 2 2 (eq. 8) http://onsemi.com 10 NCP3127 LP _DC + I RMS 2 @ DCR ³ The ESL of capacitors depends on the technology chosen, but tends to range from 1 nH to 20 nH, where ceramic capacitors have the lowest inductance and electrolytic capacitors have the highest. The calculated contributing voltage ripple from ESL is shown for the switch on and switch off below: (eq. 11) 94 mW + 2.01 A 2 @ 23.27 mW IRMS = Inductor RMS current DCR = Inductor DC resistance LPCU_DC = Inductor DC power dissipation The core losses and AC copper losses will depend on the geometry of the selected core, core material, and wire used. Most vendors will provide the appropriate information to make accurate calculations of the power dissipation at which point the total inductor losses can be captured by the equation below: LP tot + LP CU_DC ) LP CU_AC ) LP Core ³ 104 mW + 94 mW ) 0 mW ) 10 mW LPCU_DC LPCU_AC LPCore V ESLON + V ESLOFF + CoESR COUT FSW IOUT ra (eq. 16) Co ESR ³ 50 mV + 1.0 A 50 mW (eq. 17) = Output capacitor Equivalent Series Resistance ITRAN = Output transient current DVOUT_ESR = Voltage deviation of VOUT due to the effects of ESR A minimum capacitor value is required to sustain the current during the load transient without discharging it. The voltage drop due to output capacitor discharge is given by the following equation: DV OUT*DIS + Ǔ 1 ³ 8 * F SW * C OUT ǒI TRANǓ 2 1.96 mV + (eq. 14) 8 * 350 kHz * 470 mF ESL * Ipp * F SW CoESR CoRMS = Output capacitor RMS current IOUT = Output current ra = Ripple current ratio The maximum allowable output voltage ripple is a combination of the ripple current selected, the output capacitance selected, the Equivalent Series Inductance (ESL), and Equivalent Series Resitance (ESR). The main component of the ripple voltage is usually due to the ESR of the output capacitor and the capacitance selected, which can be calculated as shown in Equation 14: ǒ (eq. 15) 27.5% DV OUT*ESR + I TRAN ra 28% Co RMS + I OUT @ ³ 0.164 A + 2.0 A (eq. 13) Ǹ12 Ǹ12 28.9 mV + 3 * 28% * 50 mW ) 10 nH * 0.57 A * 350 kHz D = Duty ratio ESL = Capacitor inductance FSW = Switching frequency Ipp = Peak−to−peak current The output capacitor is a basic component for the fast response of the power supply. For the first few microseconds of a load transient, the output capacitor supplies current to the load. Once the regulator recognizes a load transient, it adjusts the duty ratio, but the current slope is limited by the inductor value. During a load step transient, the output voltage initially drops due to the current variation inside the capacitor and the ESR (neglecting the effect of the ESL). The important factors to consider when selecting an output capacitor are DC voltage rating, ripple current rating, output ripple voltage requirements, and transient response requirements. The output capacitor must be rated to handle the ripple current at full load with proper derating. The RMS ratings given in datasheets are generally for lower switching frequency than used in switch mode power supplies, but a multiplier is usually given for higher frequency operation. The RMS current for the output capacitor can be calculated below: 1 ³ ³ (1 * D ) 10 nH * 0.57 A * 350 kHz 2.75 mV + ǒ1 * 27.5% Ǔ (eq. 12) Output Capacitor Selection ǒ D 7.25 mV + = Inductor DC power dissipation = Inductor AC power dissipation = Inductor core power dissipation V ESR_C + I OUT * ra * Co ESR ) ESL * Ipp * F SW Ǔ COUT DMAX ITRAN LOUT VIN VOUT DVOUT_DIS = Output capacitor ESR = Output capacitance = Switching frequency = Output current = Ripple current ratio http://onsemi.com 11 = = = = = = = 2 D MAX C OUT L OUT ǒVIN * V OUTǓ ǒ1 A Ǔ 2 75% 2 470 mF 12 mH ³ (eq. 18) ǒ12 V * 3.3 VǓ Output capacitance Maximum duty ratio Output transient current Output inductor value Input voltage Output voltage Voltage deviation of VOUT due to the effects of capacitor discharge NCP3127 Starting with the high−side MOSFET, the power dissipation can be approximated from: In a typical converter design, the ESR of the output capacitor bank dominates the transient response. Please note that DVOUT−DIS and DVOUT−ESR are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the ESL). P D_HS + P COND ) P SW_TOT PCOND = Conduction power losses PSW_TOT = Total switching losses PD_HS = Power losses in the high side MOSFET The first term in Equation 21 is the conduction loss of the high−side MOSFET while it is on. Input Capacitor Selection The input capacitor has to sustain the ripple current produced during the on time of the upper MOSFET, so it must have a low ESR to minimize the losses. The RMS value of the input ripple current is: Iin RMS + I OUT ǸD (1 * D) ³ 0.89 A + 2.0 A * Ǹ27.5% * (1 * 27.5%) 2 P COND + ǒI RMS_HSǓ @ R DS(on)_HS I RMS_HS + I OUT @ Ǹ ǒ D@ 1) Ǔ ra 2 12 (eq. 23) IRMS_HS = High side MOSFET RMS current IOUT = Output current D = Duty ratio ra = Ripple current ratio The second term from Equation 21 is the total switching loss and can be approximated from the following equations. 2 7.98 mW + 10 mW * ǒ0.89 AǓ (eq. 22) IRMS_HS = RMS current in the high−side MOSFET RDS(on)_HS = On resistance of the high−side MOSFET Pcond = Conduction power losses Using the ra term from Equation 5, IRMS becomes: (eq. 19) D = Duty ratio IINRMS = Input capacitance RMS current IOUT = Load current The equation reaches its maximum value with D = 0.5. Loss in the input capacitors can be calculated with the following equation: P CIN + CIN ESR * ǒIIN RMSǓ ³ (eq. 21) (eq. 20) 2 CINESR = Input capacitance Equivalent Series Resistance IINRMS = Input capacitance RMS current PCIN = Power loss in the input capacitor Due to large di/dt through the input capacitors, electrolytic or ceramics should be used. If a tantalum must be used, it must be surge protected, otherwise, capacitor failure could occur. P SW_TOT + P SW ) P DS ) P RR (eq. 24) PDS = High side MOSFET drain source losses PRR = High side MOSFET reverse recovery losses PSW = High side MOSFET switching losses PSW_TOT = High side MOSFET total switching losses The first term for total switching losses from Equation 24 are the losses associated with turning the high−side MOSFET on and off and the corresponding overlap in drain voltage and current. Power MOSFET Dissipation MOSFET power dissipation, package size, and the thermal environment drive power supply design. Once the dissipation is known, the thermal impedance can be calculated to prevent the specified maximum junction temperatures from being exceeded at the highest ambient temperature. Power dissipation has two primary contributors: conduction losses and switching losses. The high−side MOSFET will display both switching and conduction losses. The switching losses of the low side MOSFET will not be calculated as it switches into nearly zero voltage and the losses are insignificant. However, the body diode in the low−side MOSFET will suffer diode losses during the non−overlap time of the gate drivers. P SW + P TON ) P TOFF (eq. 25) + 1 @ ǒI OUT @ V IN @ F SWǓ @ ǒt RISE ) t FALLǓ 2 FSW IOUT tFALL tRISE VIN PSW PTON PTOFF http://onsemi.com 12 = Switching frequency = Load current = MOSFET fall time = MOSFET rise time = Input voltage = High side MOSFET switching losses = Turn on power losses = Turn off power losses NCP3127 When calculating the rise time and fall time of the high side MOSFET it is important to know the charge characteristic shown in Figure 22. FSW = Switching frequency PRR = High side MOSFET reverse recovery losses QRR = Reverse recovery charge VIN = Input voltage The low−side MOSFET turns on into small negative voltages so switching losses are negligible. The low−side MOSFET’s power dissipation only consists of conduction loss due to RDS(on) and body diode loss during the non−overlap periods. Vth P D_LS + P COND ) P BODY (eq. 30) PBODY = Low side MOSFET body diode losses PCOND = Low side MOSFET conduction losses PD_LS = Low side MOSFET losses Conduction loss in the low−side MOSFET is described as follows: 2 P COND + ǒI RMS_LSǓ @ R DS(on)_LS Figure 22. MOSFET Switching Characteristics t RISE + Q GD I G1 IG1 Q GD ǒV BST * V THǓńǒR HSPU ) R GǓ (eq. 26) Q GD I G2 + Q GD ǒVBST * V THǓńǒR HSPD ) R GǓ ǒ ǒ ǓǓ 2 (1 * D) @ 1 ) ra 12 (eq. 32) P BODY + V FD @ I OUT @ F SW @ ǒNOL LH ) NOL HLǓ (eq. 33) FSW IOUT NOLHL (eq. 27) NOLLH PBODY VFD = Switching frequency = Load current = Dead time between the high−side MOSFET turning off and the low−side MOSFET turning on, typically 50 ns = Dead time between the low−side MOSFET turning off and the high−side MOSFET turning on, typically 50 ns = Low−side MOSFET body diode losses = Body diode forward voltage drop Control Dissipation The control portion of the IC power dissipation is determined by the formula below: (eq. 28) P C + I CC COSS = MOSFET output capacitance at 0V FSW = Switching frequency PDS = MOSFET drain to source charge losses VIN = Input voltage Finally, the loss due to the reverse recovery time of the body diode in the low−side MOSFET is shown as follows: P RR + Q RR @ V IN @ F SW Ǹ D = Duty ratio IOUT = Load current IRMS_LS = RMS current in the low side ra = Ripple current ratio The body diode losses can be approximated as: IG2 = Output current from the low−side gate drive QGD = MOSFET gate to drain gate charge RG = MOSFET gate resistance RHSPD = Drive pull down resistance tFALL = MOSFET fall time VBST = Boost voltage VTH = MOSFET gate threshold voltage Next, the MOSFET output capacitance losses are caused by both the high−side and low−side MOSFETs, but are dissipated only in the high−side MOSFET. 2 P DS + 1 @ C OSS @ V IN @ F SW 2 = RMS current in the low side = Low−side MOSFET on resistance = High side MOSFET conduction losses I RMS_LS + I OUT @ = Output current from the high−side gate drive = MOSFET gate to drain gate charge = Drive pull up resistance = MOSFET gate resistance = MOSFET rise time = Boost voltage = MOSFET gate threshold voltage QGD RHSPU RG tRISE VBST VTH t FALL + + IRMS_LS RDS(on)_LS PCOND (eq. 31) V IN (eq. 34) ICC = Control circuitry current draw PC = Control power dissipation VIN = Input voltage Once the IC power dissipations are determined, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case (eq. 29) http://onsemi.com 13 NCP3127 ambient temperature. The formula for calculating the junction temperature with the package in free air is: T J + T A ) P D @ R qJA FSW = Switching frequency FESR = Output capacitor ESR zero frequency If the criteria is not met, the compensation network may not provide stability and the output power stage must be modified. Figure 23 shows a pseudo Type III transconductance error amplifier. (eq. 35) PD RqJA = Power dissipation of the IC = Thermal resistance junction to ambient of the regulator package TA = Ambient temperature TJ = Junction temperature As with any power design, proper laboratory testing should be performed to ensure the design will dissipate the required power under worst case operating conditions. Variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e., worst case MOSFET RDS(on)). ZIN CF IEA CC To create a stable power supply, the compensation network around the transconductance amplifier must be used in conjunction with the PWM generator and the power stage. Since the power stage design criteria is set by the application, the compensation network must correct the over all system response to ensure stability. The output inductor and capacitor of the power stage form a double pole at the frequency as shown in Equation 36: F LC + 2p ǸL OUT 2.119 kHz + C OUT Gm CP R2 2p Ǹ12 mH RC VREF Figure 23. Pseudo Type III Transconductance Error Amplifier The compensation network consists of the internal OTA and the impedance networks ZIN (R1, R2, RF, and CF) and external ZFB (RC, CC, and CP). The compensation network has to provide a closed loop transfer function with the highest 0 dB crossing frequency to have fast response and the highest gain in DC conditions to minimize the load regulation issues. A stable control loop has a gain crossing with −20 dB/decade slope and a phase margin greater than 45°. Include worst−case component variations when determining phase margin. To start the design, a resistor value should be chosen for R2 from which all other components can be chosen. A good starting value is 10 kW. The NCP3127 allows the output of the DC−DC regulator to be adjusted down to 0.8 V via an external resistor divider network. The regulator will maintain 0.8 V at the feedback pin. Thus, if a resistor divider circuit was placed across the feedback pin to VOUT, the regulator will regulate the output voltage proportional to the resistor divider network in order to maintain 0.8 V at the FB pin. ³ (eq. 36) 1 470 mF COUT FLC = Output capacitor = Double pole inductor and capacitor frequency LOUT = Output inductor value The ESR of the output capacitor creates a “zero” at the frequency as shown in Equation 37: F ESR + 6.772 kHz + 2p 1 CO ESR C OUT ³ 1 2p 0.050 mW (eq. 37) 470 mF COESR = Output capacitor ESR COUT = Output capacitor FLC = Output capacitor ESR frequency The two equations above define the bode plot that the power stage has created or open loop response of the system. The next step is to close the loop by considering the feedback values. The closed loop crossover frequency should be greater than the FLC and less than 1/5 of the switching frequency, which would place the maximum crossover frequency at 70 kHz. Further, the calculated FESR frequency should meet the following: F ESR t F SW 5 RF ZFB Compensation Network 1 R1 VOUT R1 FB R2 Figure 24. Feedback Resistor Divider The relationship between the resistor divider network above and the output voltage is shown in Equation 39: (eq. 38) http://onsemi.com 14 NCP3127 R2 + R1 @ ǒ V REF Ǔ The compensation components for the Pseudo Type III Transconductance Error Amplifier can be calculated using the method described below. The method serves to provide a good starting place for compensation of a power supply. The values can be adjusted in real time using the compensation tool comp calc, available for download at ON Semiconductor’s website. The value of the feed through resistor should always be at least 2X the value of R2 to minimize error from feed through noise. Using the 2X assumption, RF will be set to 20 kW and the feed through capacitor can be calculated as shown below: (eq. 39) V OUT * V REF R1 = Top resistor divider R2 = Bottom resistor divider VOUT = Output voltage VREF = Regulator reference voltage The most frequently used output voltages and their associated standard R1 and R2 values are listed in Table 5. Table 5. OUTPUT VOLTAGE SETTINGS VO (V) R1 (kW) R2 (kW) 0.8 1.0 Open 1.0 2.55 10 1.1 3.83 10.2 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.6 10 5.0 52.3 10 http://onsemi.com 15 NCP3127 CF + ǒR 1 ) R 2Ǔ ǒR 1 ) R F ) R 2 2p 239 pF + RF ) R2 R 1Ǔ f cross (eq. 40) ǒ31.6 kW ) 10 kWǓ ǒ31.6 kW 2p CF fcross R1 R2 RF 20 kW ) 10 kW 20 kW ) 10 kW 31.6 kWǓ 30 kHz = Feed through capacitor = Crossover frequency = Top resistor divider = Bottom resistor divider = Feed through resistor The cross over of the overall feedback occurs at FPO: F PO + ǒR1 ) RFǓ 2 ǒCFǓ ƪǒR1 ) RFǓ ǒ2pǓ 2 16.86 kHz + CF FLC FPO R1 R2 RF VIN Vramp R2 ) R1 V ramp R Fƫ ǒRF ) R1Ǔ FLC V IN (eq. 41) ǒ31.6 kW ) 20 kWǓ ǒ2pǓ 2 2 ǒ239 pFǓ ƪǒ31.6 kW ) 20 kWǓ 20 kW ) 10 kW 1.1 V 20 kWƫ = Feed through capacitor = Frequency of the output inductor and capacitor = Pole frequency = Top of resistor divider = Bottom of resistor divider = Feed through resistor = Input voltage = Peak−to−peak voltage of the ramp The cross over combined compensation network can be used to calculate the transconductance output compensation network as follows: CC + R2 1 F PO4p 57.5 nF + CC FPO gm R1 R2 ³ R2 R1 gm ³ (eq. 42) 1 10 kW 16.86 kHz 10 kW ) 31.6 kW 4 ms = Compensation capacitor = Pole frequency = Transconductance of amplifier = Top of resistor divider = Bottom of resistor divider http://onsemi.com 16 ǒ20 kW ) 31.6 kWǓ 2.119 kHz 12 V NCP3127 RC + 2 F LC CC 1 Ǹ ǒ 2 ń2 ) fcross CO ESR C OUTǓ (eq. 43) 2.9 kW + CC COESR COUT fcross FLC RC 1 2 2.119 kHz 0.05 mW 470 mFǓ = Compensation capacitance = Output capacitor ESR = Output capacitance = Crossover frequency = Output inductor and capacitor frequency = Compensation resistor C P + C OUT CO ESR RC 1.288 nF + 470 mF COESR COUT CP RC ǒǸ2 ń2 ) 30 kHz 57.5 nF 2 p ³ (eq. 44) 0.05 mW 2.9 kW 2*p = Output capacitor ESR = Output capacitor = Compensation pole capacitor = Compensation resistor http://onsemi.com 17 NCP3127 Assuming an output capacitance of 470 mF in parallel with 22 mF with a crossover frequency of 35 kHz, the compensation values for common output voltages can be calculated as shown in Table 6: CP CC D ISS tSS Vramp Table 6. COMPENSATION VALUES Vin (V) Vout (V) Lout (mF) Cf (nF) Cc (nF) Rc (kW) Cp (nF) 12 0.8 4.7 NI 150 0.536 3.3 12 1.0 4.7 390 150 0.649 2.7 12 1.1 4.7 390 150 0.732 2.7 12 1.2 6.8 330 120 1.1 1.5 12 1.5 6.8 330 120 1.27 1.5 12 1.8 8.2 270 120 1.82 1.2 12 2.5 10.0 220 120 2.87 1.0 12 3.3 12.0 1000 100 3.16 0.680 12 5.0 15.0 1000 100 4.02 0.560 5 0.8 4.7 NI 150 1.27 1.5 5 1.0 4.7 390 150 1.62 1.2 5 1.1 5.6 390 150 1.91 1.0 5 1.2 5.6 330 150 2.15 0.82 5 1.5 6.8 330 150 2.74 0.68 5 1.8 8.2 270 150 4.42 0.56 5 2.5 10.0 220 150 5.36 0.39 V 900 mV Vcomp Vout Figure 25. Soft−Start Ramp The delay from the charging of the compensation network to the bottom of the ramp is considered tssdelay. The total delay time is the addition of the current set delay and tssdelay, which in this case is 6 ms and 7.64 ms respectively, for a total of 13.64 ms. Calculating Input Inrush Current The input inrush current has two distinct stages: input charging and output charging. The input charging of a buck stage is usually not controlled, and is limited only by the input RC network, and the output impedance of the upstream power stage. If the upstream power stage is a perfect voltage source, then the input charge inrush current can be depicted as shown in Figure 26 and calculated as: Calculating Soft−Start Time To calculate the soft−start delay and soft−start time, the following equations can be used. t SSdelay + ǒC P ) C CǓ 7.64 ms + 0.9 V I SS ³ (eq. 45) ǒ1.28 nF ) 83.6 nFǓ IPK 0.9 V 10 mA CP = Compensation pole capacitor CC = Compensation capacitor ISS = Soft−start current The time the output voltage takes to increase from 0 V to a regulated output voltage is tss as shown in Equation 46: t SS + ǒC P ) C CǓ 2.57 ms + = Compensation pole capacitor = Compensation capacitor = Duty ratio = Soft−start current = Soft−start interval = Peak−to−peak voltage of the ramp D Figure 26. Input Charge Inrush Current I ICinrush_PK1 + V ramp I SS (eq. 46) ǒ1.28 nF ) 83.6 nFǓ 27.5% 120 A + 1.1 V 10 mA http://onsemi.com 18 12 0.1 V IN CIN ESR (eq. 47) NCP3127 I ICinrush_RMS1 + V IN CIN ESR 0.316 102 mA + 12 V 0.1 W 0.316 ȡ ȧ ȧ1 * Ȣ eƪ 5 t NCP3127 OR ȣ ȧ ƫȤ (eq. 48) Figure 27. Load Connected to the Output Stage 13.64 ms 0.1W 330 mF 0.1 W If the load is resistive in nature, the output current will increase with soft−start linearly which can be quantified in Equation 50. 330 mF 13.64 ms I CLR_RMS + CIN = Output capacitor CINESR = Output capacitor ESR tDELAY_TOTAL = Total delay interval = Input voltage VIN Once the tDELAY_TOTAL has expired, the buck converter starts to switch and a second inrush current can be calculated: I OCinrush_RMS + ǒC OUT ) C LOADǓ t SS Load C IN t DELAY_TOTAL 1 Inrush Current DELAY_TOTAL CINESR CIN CIN ESR ȡ ȧ1 * Ȣ eƪ 5 1 ȣ ȧ ƫȧȤ V OUT D ) I CL Ǹ3 1 Ǹ3 V OUT R OUT I CR_PK + V OUT R OUT (eq. 50) 191 mA + ROUT VOUT ICLR_RMS ICR_PK D (eq. 49) COUT = Total converter output capacitance CLOAD = Total load capacitance D = Duty ratio of the load = Applied load at the output ICL IOCinrush_RMS = RMS inrush current during start−up tSS = Soft−start interval VOUT = Output voltage From the above equation, it is clear that the inrush current is dependant on the type of load that is connected to the output. Two types of load are considered in Figure 27: a resistive load and a stepped current load. http://onsemi.com 19 1 Ǹ3 3.3 V 10 W 330 mA + = Output resistance = Output voltage = RMS resistor current = Peak resistor current 3.3 V 10 W NCP3127 Layout Considerations 3.3 V As in any high frequency switching regulator, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. The interconnecting impedances should be minimized by using wide short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. For optimal performance, the NCP3127 should have a layout similar to the one shown in Figure 30. An important note is that the input voltage to the NCP3127 should have local decoupling to PGND. The recommended decoupling for input voltage is a 1 mF general purpose ceramic capacitor and a 0.01 mF COG ceramic capacitor placed in parallel. Output Voltage Output Current tss Figure 28. Resistive Load Current Alternatively, if the output has an under voltage lockout, turns on at a defined voltage level, and draws a consistent current, then the RMS connected load current is: Ǹ V OUT * V OUT_TO 492 mA + IOUT VOUT VOUT_TO V OUT Ǹǒ PGND I OUT ǒ3.3 V * 2.5 VǓ 3.3 V Ǔ CC (eq. 51) BST AGND VIN 1A CP RC COMP RF ISET FB VSW R1 PGND COG 0.01 uF = Output current = Output voltage = Output voltage load turn on CF R2 1 .0 uF RISET I CLI+ Top AGND 3.3 V 1.0 V PGND Output Voltage CC RC ÎÎ CP BST AGND ÎÎÎÎÎ Î ÎÎÎÎÎ Î ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ COMP RF R2 R1 Output Current t PGND VIN ISET VSW COG 0.01 uF 1 .0 uF RISET ÎÎ ÎÎ AGND CF FB Bottom Single Point Grounding Figure 30. Recommended Layout tss Figure 29. Voltage Enable Load Current If the inrush current is higher than the steady state input current during max load, then an input fuse should be rated accordingly using I2t methodology. The typical applications are shown in Figures 31 and NO TAG for output electrolytic and ceramic bulk capacitors, respectively. http://onsemi.com 20 NCP3127 BST VIN C3 470uF 16V C1 10uF 16V D1 U1 NCP3127 C2 NI 16V 4 3 2 1 Vin AGND BST COMP VIN FB ISET PGND VSW GND_IN CC 68n 50V R3 5 6 7 8 RSET 21k RC 2.94k VSW MMSD4148T1G CBST 10nF 50V 20R C11 0.01uF 25V C10 1uF 25V CP COMP 820pF 50V VOUT LOUT 10uH C9 1nF 25V R9 100R R4 20R C8 CF 1.2nF 10V NI R1 21.5k RCR NI CHF 820pF 50V JX C4 22uF 6.3V RF 20k FB C5 NI C6 NI 6.3V C7 470uF 16V Vout GND GND R2 10k Figure 31. Standard Application 12 V to 2.5 V 2 A BST VIN C1 10uF 16V 4 3 2 1 Vin AGND BST COMP VIN FB ISET PGND VSW GND_IN R3 5 6 7 8 RSET 21k RC 392 CC 330n 50V D1 U1 NCP3127 C2 10uF 16V VSW 20R C11 0.01uF 25V C10 1uF 25V CP COMP NI 50V MMSD4148T1G CBST 10nF 50V C9 1nF 25V R9 100R VOUT LOUT 8.2uH R4 20R C8 CF 1nF 10V NI R1 12.7k RCR 150m JX C4 22uF 6.3V RF 3.01k FB R2 10.2k Figure 32. Ceramic Capacitor Application 12 V to 1.8 V 2 A http://onsemi.com 21 C5 47uF 6.3V CHF 820pF 50V Vout GND GND NCP3127 Figure 33. Application Bottom Layout (TOP) Figure 34. Application Top Layout (TOP) http://onsemi.com 22 NCP3127 Table 7. NCP3127 APPLICATION BILL OF MATERIALS Item Reference Qty Description Value Tolerance FootPrint Manufacturer Manufacturer Part Name 1 C11 1 SMT Ceramic Capacitor 0.01 mF 5% 0603 TDK C1608C0G1E103J 2 CF 1 SMT Ceramic Capacitor 1.2 nF 5% 0603 AVX 0603ZC122JAT4A 3 C10 1 SMT Ceramic Capacitor 1 mF 10% 0603 AVX 06033D105KAT2A 4 CC 1 SMT Ceramic Capacitor 68n 5% 0603 AVX 06035C683JAT2A 5 CHF CP 2 SMT Ceramic Capacitor 820 pF 5% 0603 AVX 06035A821JAT2A 6 C8 1 SMT Ceramic Capacitor NI 7 CBST 1 SMT Ceramic Capacitor 10 nF $20% 0805 AVX 08055C681MAT2A 8 C9 1 SMT Ceramic Capacitor 1 nF 20% 0805 AVX 08053C102MAT2A 9 C1 1 SMT Ceramic Capacitor 10 mF $10% 1210 AVX 1210YD106KAT2A 10 C4 1 SMT Ceramic Capacitor 22 mF $10% 1210 AVX 12106Z226MAT2A 11 C2 1 SMT Ceramic Capacitor NI 1210 12 C5 1 SMT Ceramic Capacitor NI 1210 13 C3 C7 2 Surface Mount E−Cap 470 mF $20% (8.30 x 8.30) mm Panasonic EEE−FP1C471AP 14 C6 1 Surface Mount E−Cap NI $20% (10.3 x 10.3) mm United Chemicon EMZA160ADA471MHA0G 15 D1 1 Switching Diode 1 A, 100 V SOD−123 ON Semiconductor MMSD4148T1G 16 LOUT 1 INDUCTOR, SM 10 mH 20% (12.3 x 12.3) mm Coilcraft MSS1278−103ML 17 U1 1 Synchronous PWM 285 kHz, 0.8 V NA SOIC−8 ON Semiconductor NCP3127 Switching Converter 0603 18 RCR 1 SMT Resistor NI 19 R2 1 Resistor 10k $1.0% 1206 0603 Vishay / Dale CRCW060310K0FKEA 20 RC 1 Resistor 2.94k $1.0% 0603 Vishay / Dale CRCW06032K94FKEA 21 R3−4 2 Resistor 20R $1.0% 0603 Vishay / Dale CRCW060320R0FKEA 22 RF 1 Resistor 20k $1.0% 0603 Vishay / Dale CRCW060320K0FKEA 23 R1 1 SMT Resistor 21.5k $1.0% 0603 Vishay / Dale CRCW060321K5FKEA 24 RSET 1 Resistor 21k $1.0% 0603 Vishay / Dale CRCW060321K0FKEA ORDERING INFORMATION Device NCP3127ADR2G Package Shipping† SOIC−8 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Microsoft Excel is a registered trademark of Microsoft Corporation. http://onsemi.com 23 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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