NCP3135MNTXG

NCP3135 Integrated Synchronous Buck Converter 5A NCP3135 is a fully integrated synchronous buck converter for 3.3 V and 5 V step−down applications. It can provide up to 5 A DC load and 6 A instantaneous load current. NCP3135 supports high efficiency, fast transient response and provides power good indicator. The control scheme includes two operation modes: FCCM and automatic CCM/DCM. In automatic CCM/DCM mode, the controller can smoothly switch between CCM and DCM, where converter runs at reduced switching frequency with much higher efficiency. NCP3135 is available in 3 mm x 3 mm QFN−16 pin package. Features • • • • • • • • • • • • • • • • • High Efficiency in both CCM and DCM High Operation Frequency at 1.1 MHz Support MLCC Output Capacitor Small Footprint, 3 mm x 3 mm, 16−pin QFN Package Up to 5 A Continuous Output Current 6 A Instantaneous Load Current 2.9 V to 5.5 V Wide Conversion Voltage Range Output Voltage Range from 0.6 V to 0.84 X Vin Internal 1 ms Soft−Start Automatic Power−Saving Mode Voltage Mode Control Support Pre-bias Start−up Functionality Output Discharge Operation Over−Temperature Protection Built−in Over−Voltage, Under−Voltage and Over-Current Protection Power Good Indicator This is a Pb−Free Device www.onsemi.com 1 QFN16 3 x 3, 0.5P CASE 485DA SUGGESTED PIN ARRANGEMENT PGND PGND VIN VIN 16 • 5 V Step Down Rail • 3.3 V Step Down Rail 14 13 EN 1 12 VDD NC 2 11 AGND PGD 3 10 FB VBST 4 9 NCP3135 5 6 7 8 SW SW SW PS COMP MARKING DIAGRAM 3135 ALYWG G 3135 A L Y W G Applications 15 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 12 of this data sheet. © Semiconductor Components Industries, LLC, 2015 August, 2019 − Rev. 1 1 Publication Order Number: NCP3135/D NCP3135 VIN VBST UVLO OSC NC Ramp Control Logic & PWM Logic PS SS EN DRVH SW COMP VREF + + E/A − FB Power Good, UVP, OVP, UVLO, Overtemperature and Vout discharge PGD DRVL PGND OCP UVLO VDD AGND Figure 1. Block Diagram Table 1. PIN DESCRIPTION Pin No. Symbol Description 1 EN Logic control to enabling the switcher. Internally pulled up to VDD with a 1.35 MW resistor 2 NC Not connected 3 PGD Open drain power good output 4 VBST Gate drive voltage for high side FET. Connect capacitor from this pin to SW 5, 6, 7 SW Switch node between high−side MOSFET and low−side MOSFET 8 PS Mode configuration pin (with 10 mA current): Pulled high or floating (internally pulled high): Forced Continuous Conduction Mode Connect with resistor equal to or lower than (≤)174 kW to GND: Automatic CCM/DCM 9 COMP 10 FB 11 AGND 12 VDD Power supply input for control circuitry 13, 14 VIN Power input for power conversion and gate driver supply 15, 16 PGND Output of the error amplifier Feedback pin. Connect to resistor divider to set up the desired output voltage Analog ground Power ground www.onsemi.com 2 NCP3135 L1 Vin = 2.9 V X 5.5 V C5 C6 R6 C4 13 VIN 12 VDD C8 14 VIN 5 6 7 SW SW SW C7 Vin R7 VBST 4 11 AGND C9 NCP3135 EN R5 2 NC PGD 3 1 EN FB 10 8 PS PGND 15 PGND 16 COMP 9 PGD R3 C2 R4 C1 Vout R1 R2 C3 Figure 2. NCP3135 Single Voltage Rail for VIN and VDD L1 Vin = 2.9 V X 5.5 V C5 C6 C4 VDD = 3.3 V C8 13 VIN 12 VDD 14 VIN 5 6 7 SW SW SW C7 Vin R7 VBST 4 11 AGND C9 NCP3135 EN R5 2 NC PGD 3 1 EN FB 10 8 PS PGND 15 PGND 16 COMP 9 PGD R3 C2 R4 C1 R1 R2 C3 Figure 3. NCP3135 Dual Voltage Rail for VIN and VDD www.onsemi.com 3 Vout NCP3135 Table 2. ABSOLUTE MAXIMUM RATINGS Value Min Max Units VIN, VDD, PS, EN −0.3 6.5 V VBST −0.3 17 VBST (with respect to SW) −0.3 6.5 FB −0.3 3.7 DC −1 6.5 Pulse < 20 ns, E = 5 mJ −3 10 Rating Input Voltage Range Output Voltage Range Symbol SW High−side FET and Low−side FET drain− source voltage DC 6.5 AC, Pulse < 50 ns 7.5 PGD −0.3 6.5 COMP −0.3 6.5 PGND −0.3 0.3 Operation Ambient Temperature TA −40 125 Storage Temperature TS −55 150 Junction Temperature TJ −40 Electrostatic Discharge Human Body Model (HBM) 2000 Charged Device Model (CDM) 500 Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds V °C 150 V 300 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 3. RECOMMENDED OPERATION RATINGS Value Max Units VIN 2.9 5.5 V VDD 2.9 5.5 VBST −0.1 13.5 VBST (with respect to SW) −0.1 6 EN −0.1 3.5 FB, PS Rating Symbol Input Voltage Range Output Voltage Range Min Nom −0.1 3.5 SW −1 6.5 PGD −0.1 6 COMP −0.1 3.5 PGND −0.1 0.1 −40 125 Junction Temperature range, TJ V °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Table 4. THERMAL INFORMATION Rating Junction−to−Ambient Thermal Resistance (Note 1) 1. The maximum package power dissipation limit must not be exceeded. PD + T J(MAX) * T A R qJA www.onsemi.com 4 Value Units 45 °C/W NCP3135 Table 5. ELECTRICAL CHARACTERISTICS (VDD = VIN = 3.3 V and VDD = VIN = 5.0 V, TA = TJ = −40°C to 125°C. Typical values are at TA = 25°C, PGND = GND unless otherwise noted) Parameter Symbol Test Conditions Min Typ Max Units 5.5 V POWER SUPPLY VIN operation voltage VIN VIN UVLO threshold Nominal input voltage range 2.9 Ramp up; EN = ‘HI’ VIN UVLO hysteresis VDD internal bias voltage Nominal 3.3 V input voltage range VDD UVLO threshold Ramp up; EN = ‘HI’ 2.8 V 130 mV 2.9 VDD UVLO hysteresis 5.5 V 2.8 V 75 mV VOLTAGE MONITOR Pull−down voltage with 4 mA sink current Power good low voltage 200 400 mV −2.0 0 2.0 mA Feedback lower voltage limit 80 83 86 %Vref Feedback higher voltage limit 114 117 120 %Vref Power good high leakage current Power good threshold Power good high delay tPGDELAY Minimum Vin voltage for valid PGD at start up Measured at Vin with 1 mA (or 2 mA) sink current on PGD pin at start up Output over-voltage protection threshold at FB Over-voltage blanking time tOVPDLY Time from FB higher than 20% of Vref to OVP fault Output under-voltage protection threshold at FB Under-voltage blanking time tUVPDLY 400 ms 1 V 114 117 120 %Vref 1.0 1.7 2.5 ms 80 83 86 %Vref Time from FB lower than 20% of Vref to UVP fault 11 EN = ‘HI’, no switching 2.2 ms SUPPLY CURRENT (TJ = +255C) VDD quiescent current IVDD 3.5 mA VDD shutdown supply current IVDD_SD EN = ‘LO’ 8.0 mA Vin shutdown supply current IQSHDN EN = ‘LO’, Vin = 5 V 3.5 mA 606 mV FEEDBACK VOLTAGE & ERROR AMPLIFIER Reference voltage at FB VREF −40°C < TA < 85°C 594 600 Unity gain bandwidth (Note 1) 14 MHz Open loop gain (Note 1) 80 dB FB pin leakage current Output sourcing and sinking current (Note 1) 100 Ccomp = 20 pF Slew rate (Note 1) nA 5 mA 5 V/ ms OVER CURRENT PROTECTION & ZERO CROSSING Over-current limit on high−side FET When Iout exceeds this threshold for 4 consecutive cycles. Vin = 3.3 V, Vout = 1.5 V with 1 mH inductor, TA = +25°C 6.9 7.2 One time over-current latch off on the low−side FET Immediately shut down when sensed current reach this value. Vin = 3.3 V, Vout = 1.5 V with 1 mH inductor, TA = +25°C 7.0 8.1 Zero crossing comparator internal offset (Note 1) PGND−SWN, Automatic CCM/DCM mode −4.5 −3.0 www.onsemi.com 5 8.1 A A −1.5 mV NCP3135 Table 5. ELECTRICAL CHARACTERISTICS (VDD = VIN = 3.3 V and VDD = VIN = 5.0 V, TA = TJ = −40°C to 125°C. Typical values are at TA = 25°C, PGND = GND unless otherwise noted) Parameter Symbol Test Conditions Min Typ Max Units 1.1 1.18 1.30 V EN hysteresis 0.18 0.24 V EN input pull up resistor 1.35 MW 2.2 V LOGIC PINS: I/O VOLTAGE AND CURRENT EN high threshold voltage PS mode threshold voltage Level 1 to Level 2 PS source 10 mA pull−up current when enabled 8 10 12 mA 1 mA INTERNAL BST DIODE VBST = 6.6 V, Vin = 3.3 V, TA = 25°C Reverse−bias leakage current SOFT STOP Output discharge on−resistance EN = 0, VIN = 3.3 V, Vout = 0.5 V 20 W Rising from Vss = 0 V to Vss = 0.6 V 1.0 ms TIMERS: SOFT START Soft start ramp−up time tSS Delay after EN asserting EN = ‘HI’ Switching frequency control Forced CCM mode 0.2 0.99 ms 1.1 1.21 MHz 100 140 ns PWM Minimum OFF time FCCM mode or Automatic CCM/DCM mode PWM ramp amplitude (Note1) 2.9 V < VIN < 5.5 V Maximum duty cycle, FCCM mode or Automatic CCM/DCM mode FsW = 1.1 MHz, 0°C < TA < 85°C VIN/4 84% 89% 130 140 V THERMAL SHUTDOWN Thermal shutdown threshold (Note 1) Thermal shutdown hysteresis (Note 1) 40 150 °C °C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Guaranteed by design, no production test www.onsemi.com 6 NCP3135 TYPICAL CHARACTERISTICS 98 98 96 96 94 VOUT = 2.5 V EFFICIENCY (%) EFFICIENCY (%) 94 92 1.8 V 90 1.5 V 88 1.2 V 86 84 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 80 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Figure 4. Efficiency at Auto CCM/DCM Mode Vin = 3.3 V Figure 5. Efficiency at FCCM Mode Vin = 3.3 V 98 96 VOUT = 3.3 V 2.5 V 92 1.8 V 90 1.5 V 88 1.2 V 86 1.0 V 84 VOUT = 3.3 V 94 EFFICIENCY (%) EFFICIENCY (%) 1.0 V OUTPUT CURRENT (A) 94 2.5 V 92 1.8 V 90 1.5 V 88 1.2 V 86 1.0 V 84 82 82 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 80 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Figure 6. Efficiency at Auto CCM/DCM Mode Vin = 5.0 V Figure 7. Efficiency at FCCM Mode Vin = 5.0 V 1.50 0.50 0.45 0.40 OUTPUT VOLTAGE CHANGE (%) OUTPUT VOLTAGE CHANGE (%) 1.2 V 86 OUTPUT CURRENT (A) 96 Vin = 3.3 V FCCM and Vin = 3.3 V Auto CCM/DCM 0.35 0.30 Vin = 5 V Auto CCM/DCM 0.25 0.20 0.15 0.10 0.05 0 1.5 V 88 82 98 80 1.8 V 90 84 1.0 V 82 80 VOUT = 2.5 V 92 Vin = 5 V FCCM 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1.25 1.5 V, 0 A, Auto CCM/DCM 0.75 0.50 1.5 V, 5 A, Auto CCM/DCM 1.5 V, 0 A, FCCM 0.25 0 5.0 1.5 V, 5 A, FCCM 1.00 2.9 3.4 3.9 4.4 4.9 OUTPUT CURRENT (A) INPUT VOLTAGE (V) Figure 8. Load Regulation (output current vs. output voltage) Figure 9. Line Regulation (input voltage vs. output voltage) www.onsemi.com 7 5.4 NCP3135 TYPICAL CHARACTERISTICS 1000 10,000 SWITCHING FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) 10,000 FCCM Auto CCM/DCM 100 Vin = 3.3 V Vout = 1.5 V 10 0.01 0.1 1 Auto CCM/DCM 100 Vin = 5.0 V Vout = 1.5 V 10 10 FCCM 1000 0.01 0.1 1 10 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Figure 10. Switching Frequency vs. Output Current at Vin = 3.3 V Figure 11. Switching Frequency vs. Output Current at Vin = 5.0 V EN EN Vout Vout PGD PGD Figure 12. Soft Start−up at Auto CCM/DCM Mode Vin = 3.3 V, No Load Figure 13. Soft Start−up at Auto CCM/DCM Mode Vin = 3.3 V, 5 A Load EN EN Vout PGD Vout Pre−bias = 0.5 V PGD Figure 14. Pre−bias Start−up at Auto CCM/DCM Mode Vin = 3.3 V, No Load Figure 15. Soft Stop at Auto CCM/DCM Mode Vin = 3.3 V, No Load www.onsemi.com 8 NCP3135 TYPICAL CHARACTERISTICS Figure 16. Switching Node Waveform at Auto CCM/DCM Mode Vin = 3.3 V, 5 A Load Figure 17. Switching Node Waveform at Auto CCM/DCM Mode Vin = 3.3 V, No Load Figure 18. Switching Node Waveform at Auto CCM/DCM Mode Vin = 5.0 V, 5 A Load Figure 19. Switching Node Waveform at Auto CCM/DCM Mode Vin = 5.0 V, No Load www.onsemi.com 9 NCP3135 DETAILED DESCRIPTION Overview NCP3135 provides two operation modes to fit various application requirements. The automatic CCM/DCM mode operation provides reduced power loss and increases the efficiency at light load. The adaptive power control architecture enables smooth transition between light load and heavy load while maintaining fast response to load transients. NCP3135 is a low input voltage 5 A high performance synchronous buck converter with two integrated N−MOSFETs. NCP3135’s output voltage range is from 0.6 V to 0.84 x Vin and it has wide input voltage range from 2.9 V to 5.5 V. The features of NCP3135 include supporting pre−bias start−up to protect sensitive loads, cycle−by−cycle over−current limiting and short circuit protection, power good monitor, over voltage and under voltage protection, built in output discharge and thermal shutdown. Operation Mode NCP3135 offers two operation modes programmed by PS pin connections, see table below. Table 6. PS pin Connection Operation Mode Auto Skip at Light Load (≤)174 kW to GND Automatic CCM/DCM Yes Floating or pulled to VDD FCCM Soft Stop In forced continuous conduction mode (FCCM), the high−side FET is ON during the on−time and the low−side FET is ON during the off−time. The switching is synchronized to an internal clock thus the switching frequency is fixed. In Automatic CCM/DCM mode, the high−side FET is ON during the on−time and low−side FET is ON during the off−time until the inductor current reaches zero. An internal zero−crossing comparator detects the zero crossing of the inductor current from positive to negative. When the inductor current reaches zero, the comparator sends a signal to the logic circuitry and turns off the low−side FET. When the load is increased, the inductor current is always positive and the zero−crossing comparator does not send any zero−crossing signal. The converter enters into continuous conduction mode (CCM) when no zero−crossing is detected for two consecutive PWM pulses. In CCM mode, the switching synchronizes to the internal clock and the switching frequency is fixed. Soft−Stop or discharge mode is always on during faults or disable. In this mode, disable (EN) causes the output to be discharged through an internal 20 W transistor inside of SW terminal. The time constant of soft−stop is a function of output capacitance and the resistance of the discharge transistor. Automatic Power Saving Mode In Automatic CCM/DCM mode when the load current decreases, the converter will enter power saving mode operation. During power saving mode, the low−side MOSFET will turn off when the inductor current reaches zero. So the converter skips switching and operates with reduced frequency, which minimizes the quiescent current and maintains high efficiency. Forced Continuous Conduction Mode When PS pin is floating or pulled high, NCP3135 is operating in forced continuous conduction mode in both light load and heavy load conditions. In this mode, the switching frequency remains constant over the entire load range, making it suitable for applications that need tight regulation of switching frequency at a cost of lower efficiency at light load. Reference Voltage The NCP3135 incorporates 600 mV reference voltage with 1.0 % tolerance. Internal Soft−Start To limit the start−up inrush current, an internal soft start circuit is used to ramp up the reference voltage from 0 V to its final value linearly. The internal soft start time is 1.0 ms typically. www.onsemi.com 10 NCP3135 PROTECTIONS Under Voltage Lockout (UVLO) low−side FET exceeds 8.1 A, the over−current protection is enabled and immediately turns off both the high−side and the low−side FETs. The device is fully protected against over−current during both on−time and off−time. This protection is latched. There is under-voltage lock out protection (UVLO) for both VIN and VDD in NCP3135, which has a typical trip threshold voltage 2.8 V and trip hysteresis 75 mV for VDD and 130 mV for VIN. If UVLO is triggered, the device resets and waits for the voltage to rise up over the threshold voltage and restart the part. Please note this protection function DOES NOT trigger the fault counter to latch off the part. Pre−Bias Startup In some applications the controller will be required to start switching when its output capacitors are charged anywhere from slightly above 0 V to just below the regulation voltage. This situation occurs for a number of reasons: the converter’s output capacitors may have residual charge on them or the converter’s output may be held up by a low current standby power supply. NCP3135 supports pre−bias start up by holding low−side FETs off until soft start ramp reaches the FB pin voltage. Over Voltage Protection (OVP) When feedback voltage is above 17% (typical) of nominal voltage for over 1.7 ms blanking time, an OV fault is set. In this case, the converter de−asserts the PGD signal and performs the over−voltage protection function. The top gate drive is turned off and the bottom gate drive is turned on to discharge the output. The bottom gate drive will be turned off until VFB drops below the UVP threshold. The device enters a high−impedance state. This protection is latched. Thermal Shutdown The NCP3135 protects itself from over heating with an internal thermal monitoring circuit. When the die temperature goes beyond a threshold value 135°C, both the high−side and the low−side FETs turn off until the temperature falls 40°C below of the threshold value. Then the converter restarts. Under Voltage Protection (UVP) Output under−voltage protection works in conjunction with the current protection described in the Over−current Protection sections. An UVP circuit monitors the feedback voltage to detect under−voltage event. The under−voltage limit is 17% (typical) below of nominal voltage at FB pin. If the feedback voltage is below this threshold over 11 ms, an UV fault is set and both the high−side and the low−side FETs turn off. This protection is latched. Application Note For higher output voltage application cases (Vout = 3.3 V), choose the inductor value not to be lower than 1 mH to avoid over-current protection being triggered by inductor current ripple; For Vin = 5 V and Vout = 3.3 V case, add a voltage divider between Vin and EN to ensure that the part can start up without triggering UVP. Use Figure 20 as design reference for schematics. For other lower output voltage cases, it is not necessary to add this divider. Power Good Monitor (PGD) NCP3135 provides window comparator to monitor the output voltage at FB pin. When the output voltage is within ±17% of regulation voltage, the power good pin outputs a high signal. Otherwise, PGD stays low. The PGD pin is open drain 5 mA pull down output. During startup, PGD stays low until the feedback voltage is within the specified range for about 0.4 ms. If feedback voltage falls outside the tolerance band, the PG pin goes low after 10 ms delay. The PGD pin de−asserts as soon as the EN pin is pulled low or an under−voltage event on VDD is detected. VIN = 5 V 10 kW Over Current Protection (OCP) NCP3135 provides both high−side and low−side MOSFET current limiting. When the current through the high−side FET exceeds 7.5 A, the high−side FET turns off and the low−side FET turns on until next PWM cycle. An over−current counter is triggered and starts to increment each occurrence of an over−current event. Both the high−side and the low−side FETs turn off when the OC counter reaches four. The OC counter resets if the detected current is less than 7.5 A after an OC event. Another set of over−current circuitry monitors the current flowing through the low−side FET. If the current through the EN 3.6 kW PGND Figure 20. Voltage divider between VIN and EN for start−up in VIN = 5 V and VOUT = 3.3 V case www.onsemi.com 11 NCP3135 Layout Guidelines Use wide traces for the nodes conducting high current such as VIN, VOUT, PGND and SW. Place feedback and compensation network components close to the IC. Keep FB, COMP away from noisy signals such as SW, BST. Place VIN and VDD decoupling capacitors as close to the IC as possible. When laying out a power PCB for the NCP3135 there are several key points to consider. Use four vias to connect the thermal pad to power ground. Separate the power ground and analog ground planes; connect them together at a single point. Increase the thickness of PCB copper, it can help to lower the die temperature and improve the overall efficiency but meanwhile increase the cost of the board fabrication. ORDERING INFORMATION Device NCP3135MNTXG Marking Package Shipping† 3135 QFN16, 3 x 3, 0.5P (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN16 3x3, 0.5P CASE 485DA ISSUE A 1 SCALE 2:1 ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ D PIN ONE REFERENCE 2X B A DATE 22 SEP 2015 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L L1 DETAIL A E ALTERNATE CONSTRUCTIONS 0.10 C ÉÉÉ ÇÇÇ A3 2X 0.10 C EXPOSED Cu TOP VIEW A DETAIL B 0.05 C ÉÉÉ ÉÉÉ ÇÇÇ MOLD CMPD A3 A1 DETAIL B A3 ALTERNATE CONSTRUCTIONS 0.05 C NOTE 4 SIDE VIEW A1 C SEATING PLANE D2 16X 5 L 8X 0.10 C A B 16X 1 b 0.10 C A B 0.05 C K XXXXX XXXXX ALYWG G L2 9 E2 NOTE 3 16 e e/2 BOTTOM VIEW XXXXX A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. RECOMMENDED SOLDERING FOOTPRINT* 3.30 PACKAGE OUTLINE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 3.00 BSC 1.55 1.75 3.00 BSC 1.55 1.75 0.50 BSC 0.275 REF 0.30 0.50 0.00 0.15 0.09 REF GENERIC MARKING DIAGRAM* 0.10 C A B DETAIL A DIM A A1 A3 b D D2 E E2 e K L L1 L2 16X 0.61 1.78 1 1.78 3.30 16X 0.30 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON87551E QFN16, 3X3, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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