NCP3155A, NCP3155B
3 A Synchronous Buck
Regulator
The NCP3155 is a DC/DC synchronous switching regulator with
fully integrated power switches and full fault protection. The
switching frequency of 1 MHz and 500 kHz allows the use of small
filter components, which results in smaller board space and reduced
BOM cost. Available in a SOIC-8 package.
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8
Features
•
•
•
•
•
•
•
•
•
•
•
Input Voltage Range from 4.7 V to 24 V
Adjustable Output Voltage
1 MHz Operation (NCP3155A – 500 kHz)
Internally Programmed 1.2 ms Soft−Start (NCP3155A – 2.4 ms)
0.8 ± 1.0% Reference Voltage
48 mW HS−FET and 18 mW LS−FET
Current Limit Protection
Transconductance Amplifier with External Compensation
Input Undervoltage Lockout
Output Overvoltage and Undervoltage Detection
These are Pb−Free Devices
Set Top Boxes
DVD Drives and HDD
LCD Monitors and TVs
Cable Modems
Telecom/Networking/Datacom Equipment
4.7 V − 24 V
VIN
BST VSW
SOIC−8 NB
CASE 751
MARKING DIAGRAM
8
3155x
ALYW
G
1
3155x
A
L
Y
W
G
Typical Applications
•
•
•
•
•
1
= Specific Device Code
x = A or B
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
VOUT
PGND
VIN
VSW
BST
COMP
AGND
FB
ISET
(Top View)
PGND
NCP3155
ISET
COMP
FB1
ORDERING INFORMATION
AGND
Device
Figure 1. Typical Application Circuit
Package
Shipping†
NCP3155ADR2G
SOIC−8 2500 / Tape & Reel
(Pb−Free)
NCP3155BDR2G
SOIC−8 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2012
February, 2012 − Rev. 3
1
Publication Order Number:
NCP3155/D
NCP3155A, NCP3155B
BST
VIN
INTERNAL BIAS
POR/STARTUP
VC
ACTIVE
BOOST
THERMAL SD
OSCILLATOR
VIN
HSDRV
LEVEL
SHIFT
CLK/
DMAX/
SOFT
START
VSW
VIN
RAMP
1.5 V
GATE
DRIVE
LOGIC
CURRENT
LIMIT
SAMPLE &
HOLD
ISET
+
−
COMP
VC
REF
LSDRV
PGND
FB
+
−
+
−
ISET
OOV
OUV
AGND
Figure 2. NCP3155 Block Diagram
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Description
1
PGND
The PGND pin is the high current ground pin for the lower MOSFET and drivers which should be soldered to a
large copper area to reduce thermal resistance.
2
VIN
The VIN pin powers the internal control circuitry and is monitored by an undervoltage comparator. The VIN pin
is also connected to the internal power NMOS switch. It is also used in conjunction with the VSW pin to sense
current in the high side MOSFET. The VIN pin has high dI/dt edges and must be decoupled to PGND pin close
to the pin of the device.
3
BST
Supply rail for the floating top gate driver. Connect a capacitor (CBST) between this pin and the VSW pin. Typical values for CBST range from 1 nF to 100 nF.
4
COMP
Compensation pin. The comp pin is the output of the transconductance amplifier and the non−inverting input of
the PWM comparator. The comp pin in conjunction with the FB pin are used to compensate the voltage−control
feedback loop.
5
FB
Inverting input to the Operational Transconductance Amplifier (OTA). The FB pin in conjunction with the external compensation serves to stabilize and achieve the desired output voltage with voltage mode compensation.
6
AGND
7
ISET
Bottom gate MOSFET driver pin and the internal current set pin. Place a resistor to ground to set the current
limit of the converter.
8
VSW
The VSW pin is the connection of the drain and source of the internal N MOSFETS. The VSW pin swings from
VIN when the high side switch is on to small negative voltages when the low side switch is on with high dV/dt
transitions.
The AGND pin serves as small−signal ground. All small−signal ground paths should connect to the AGND pin
at a single point to avoid any high current ground returns.
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NCP3155A, NCP3155B
ABSOLUTE MAXIMUM RATINGS (measured vs. GND pin 8, unless otherwise noted)
Rating
Symbol
VMAX
VMIN
Unit
VCC
26.4
−0.3
V
BST−VSW
13.2
−0.3
V
High Side Drive Boost Pin
BST
45
−0.3
V
Switch Voltage Node
VSW
30
−0.6
V
COMP
5.5
−0.3
V
FB
6.0
−0.3
V
ISET
13.2
−0.3
V
Main Supply Voltage Input
Boost to VSW differential voltage
Transconductance Amplifier Output
Feedback
Current Limit Set
Operating Junction Temperature Range (Note 1)
Maximum Junction Temperature
Storage Temperature Range
Thermal Characteristics − SOIC−8 Package
Thermal Resistance Junction−to−Air
(Note 2)
(Note 3)
Lead Temperature Soldering (10 sec):
Reflow (SMD styles only) Pb−Free (Note 3)
TJ
−40 to +125
°C
TJ(MAX)
+150
°C
Tstg
−55 to +150
°C
RqJA
110
170
°C/W
RF
260 Peak
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The maximum package power dissipation limit must not be exceeded.
PD +
T J(max) * T A
R qJA
2. The value of qJA is measured with the device mounted on 1 in2 FR*4 board with 1 oz. copper, in a still air environment with TA = 25°C. The
value in any given application depends on the user’s specific board design.
3. The value of qJA is measured with the device mounted on minimum footprint, in a still air environment with TA = 25°C. The value in any given
application depends on the user’s specific board design.
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NCP3155A, NCP3155B
ELECTRICAL CHARACTERISTICS (−40°C < TJ < +125°C, VCC = 12 V, for min/max values unless otherwise noted)
Characteristic
Conditions
Min
−
4.7
VFB = 0.8 V, Switching, VCC = 4.7 V
−
VFB = 0.8 V, Switching, VCC = 24 V
−
VFB = 0.8 V, Switching, VCC = 4.7 V
−
VFB = 0.8 V, Switching, VCC = 24 V
UVLO Rising Threshold
UVLO Falling Threshold
Input Voltage Range
Typ
Max
Unit
24
V
11.1
−
mA
31.5
−
mA
16.5
−
mA
−
54.7
−
mA
VCC Rising Edge
4.0
4.3
4.7
V
VCC Falling Edge
3.5
3.9
4.3
V
SUPPLY CURRENT
VCC Supply Current
VCC Supply Current
NCP3155A
NCP3155B
UNDER VOLTAGE LOCKOUT
OSCILLATOR
Oscillator Frequency
Oscillator Frequency
NCP3155A
NCP3155B
Ramp−Amplitude Voltage
TJ = +25°C, 4.7 V v VCC v 24 V
415
500
585
kHz
TJ = −40°C to +125°C, 4.7 V v VCC v 24 V
400
500
600
kHz
TJ = +25°C, 4.7 V v VCC v 24 V
830
1000
1170
kHz
TJ = −40°C to +125°C, 4.7 V v VCC v 24 V
820
1000
1180
kHz
Vpeak − Valley
−
1.5
−
V
0.46
0.71
0.85
V
%
Ramp Valley Voltage
PWM
Minimum Duty Cycle
(Note 4)
Maximum Duty Cycle
Soft Start Ramp Time
NCP3155A
NCP3155B
VFB = VCOMP
−
7.0
−
80
84
−
%
−
−
2.4
1.2
−
−
ms
ERROR AMPLIFIER (GM)
Transconductance
0.9
1.3
1.9
mS
Open Loop dc Gain
(Notes 4 and 6)
−
70
−
dB
Output Source Current
VFB = 750 mV
45
70
100
mA
Output Sink Current
VFB = 850 mV
45
70
100
mA
−
0.5
500
nA
TJ = 25 C
4.7 V < VIN < 24 V, −40°C < TJ < +125°C
0.792
0.784
0.8
0.8
0.808
0.816
V
V
COMP High Voltage
VFB = 750 mV
4.0
4.4
5.0
V
COMP Low Voltage
VFB = 850 mV
−
72
250
mV
Feedback OOV Threshold
0.91
1.00
1.09
V
Feedback OUV Threshold
0.56
0.60
0.64
V
FB Input Bias Current
Feedback Voltage
OUTPUT VOLTAGE FAULTS
PWM OUTPUT STAGE
High−Side Switch On Resistance
VIN = 12 V
VIN = 4.7 V
−
−
48
65
63
85
mW
Low−Side Switch On Resistance
VIN = 12 V
VIN = 4.7 V
−
−
18
21
35
50
mW
OVERCURRENT
ISET Source Current
7
13.5
18
mA
RSET = 22.1 kW
−
298
−
mV
Thermal Shutdown
(Notes 4 and 7)
−
175
−
°C
Hysteresis
(Notes 4 and 7)
−
20
−
°C
Current Limit Set Voltage (Note 5)
THERMAL SHUTDOWN
4.
5.
6.
7.
Guaranteed by design.
The voltage sensed across the high side MOSFET during conduction.
This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal Ro of > 10 MW.
This is not a protection feature.
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NCP3155A, NCP3155B
TYPICAL PERFORMANCE CHARACTERISTICS
100
90
80
60
EFFICENCY (%)
1.2 V
70
1.5 V
50
40
30
NCP3155A, Vin = 12 V
Typical Application Circuit
Figure 45
20
10
0
0
0.5
Vout = 5.0 V
90
3.3 V
80
EFFICENCY (%)
100
Vout = 5.0 V
1
1.5
2
Iout, OUTPUT CURRENT (A)
3.3 V
70
1.2 V
60
50
1.5 V
40
30
NCP3155B, Vin = 12 V
Typical Application Circuit
Figure 45
20
10
2.5
0
3
0
0.5
Figure 3. Efficiency vs Output Current and
Output Voltage
100
5.1
5.08
5.06
Vin = 24 V
70
5.04
Vin = 18 V
60
VOUT (V)
EFFICENCY (%)
80
50
40
30
10
0
0
0.5
1
1.5
2
Iout, OUTPUT CURRENT (A)
2.5
Vin = 12 V
5.02
4.98
4.94
4.92
Vin = 18 V
NCP3155A, Vout = 5 V
Typical Application Circuit
Figure 45
4.9 0
3
Vin = 24 V
5
4.96
NCP3155A, Vout = 5 V
Typical Application Circuit
Figure 45
20
3
Figure 4. Efficiency vs Output Current and
Output Voltage
Vin = 12 V
90
1
1.5
2
2.5
Iout, OUTPUT CURRENT (A)
0.4
0.8
1.2
1.6
2.0
2.4
2.8
Iout, OUTPUT CURRENT (A)
Figure 5. Efficiency vs Output Current and Input
Voltage
Figure 6. Load Regulation vs Input Voltage
Input = 12 V, Output = 5.0 V, Load = 2 A,
CH3 (Purple) = VIN, (CH2) Green = VOUT, CH1 (Yellow) = VSW
CH3: 200 mVac/div; CH2: 50 mVac/div; CH1: 5.0 V/div
Time Scale: 2.0 ms/div; Figure 45
Input = 18 V, Output = 5.0 V, Load = 2 A,
CH3 (Purple) = VIN, (CH2) Green = VOUT, CH1 (Yellow) = VSW
CH3: 200 mVac/div; CH2: 50 mVac/div; CH1: 5.0 V/div
Time Scale: 2.0 ms/div; Figure 45
Figure 7. Switching Waveforms (NCP3155A)
Figure 8. Switching Waveforms (NCP3155A)
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NCP3155A, NCP3155B
TYPICAL PERFORMANCE CHARACTERISTICS
808
806
VFB (mV)
804
802
800
798
796
794
792
−40 −25 −10
Input = 12 V, Output = 1.8 V, Load = 2 A,
CH3 (Purple) = VIN, (CH2) Green = VOUT, CH1 (Yellow) = VSW
CH3: 200 mVac/div; CH2: 50 mVac/div; CH1: 5.0 V/div
Time Scale: 1.0 ms/div; Figure 46
fSW (kHz)
fSW (kHz)
1120
1100
1080
1060
1040
1020
1000
980
960
940
920
900
880
860
−40 −25 −10
1.5
4.5
1.48
4.4
1.46
4.3
1.44
4.2
1.42
4.1
1.38
3.8
3.7
1.32
3.6
20 35 50 65 80
TEMPERATURE (°C)
95
NCP3155B
Vin = 12 V − 24 V
Vin = 4.7 V
5
20 35 50 65 80
TEMPERATURE (°C)
95
110 125
UVLO Rising
3.9
1.34
5
110 125
4
1.36
1.3
−40 −25 −10
95
Figure 12. Switching Frequency vs Input
Voltage and Temperature
UVLO (V)
gm (mS)
Figure 11. Switching Frequency vs Input
Voltage and Temperature
1.4
20 35 50 65 80
TEMPERATURE (°C)
Figure 10. Feedback Reference Voltage vs
Temperature
Figure 9. Switching Waveforms (NCP3155B)
570
NCP3155A
560
550
540
530
520
510
Vin = 12 V − 24 V
500
490
Vin = 4.7 V
480
470
460
450
440
430
−40 −25 −10 5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
5
UVLO Falling
3.5
40
110 125
Figure 13. Transconductance vs Temperature
25
10
5
20 35 50 65 80
TEMPERATURE (°C)
95 110 125
Figure 14. Input Undervoltage vs Temperature
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NCP3155A, NCP3155B
TYPICAL PERFORMANCE CHARACTERISTICS
1000
950
1100
900
Output Overvoltage Threshold
1000
VALLEY VOLTAGE (mV)
THRESHOLD VOLTAGE (mV)
1200
900
800
700
Output Undervoltage Threshold
600
500
850
800
750
700
650
600
550
500
450
400
−40 −25 −10
5
20
35
50
65
80
95
110 125
400
−40 −25 −10
5
20
35
50
65
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. Output Protection vs Temperature
Figure 16. Ramp Valley Voltage vs Temperature
17
16
ISET (mA)
15
14
13
12
11
10
−40 −25 −10
5
20 35 50 65 80
TEMPERATURE (°C)
95
110 125
Figure 17. ISET Current vs Temperature
Input = 12 V, Output = 1.8 V, Load = 2 A,
CH3 (Purple) = VIN, (CH2) Green = VOUT, CH1 (Yellow) = VSW
CH3: 10 V/div; CH2: 2.0 V/div; CH1: 5.0 V/div
Time Scale: 1.0 ms/div; Figure 45
Figure 18. Startup Waveforms (NCP3155A)
Input = 12 V, Output = 1.8 V, Load = 2 A,
CH3 (Purple) = VIN, (CH2) Green = VOUT, CH1 (Yellow) = VSW
CH3: 10 V/div; CH2: 1.0 V/div; CH1: 5.0 V/div
Time Scale: 0.5 ms/div; Figure 46
Input = 12 V
(CH2) Green = VOUT, CH1 (Yellow) = VSW
CH2: 0.5 V/div; CH1: 5.0 V/div
Time Scale: 2.0 ms/div; Figure 45
Figure 19. Startup Waveforms (NCP3155B)
Figure 20. Current Limit Waveforms (NCP3155A)
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NCP3155A, NCP3155B
TYPICAL PERFORMANCE CHARACTERISTICS
110
100
90
Vin = 5.0 V
RDS(on) (mW)
80
70
60
Vin = 10 V − 24 V
50
40
30
20
10
0
Input = 12 V
(CH2) Green = VOUT, CH1 (Yellow) = VSW
CH2: 0.5 V/div; CH1: 5.0 V/div
Time Scale: 2.0 ms/div; Figure 46
40
25
25
3
OUTPUT CURRENT (A)
RDS(on) (mW)
3.5
Vin = 5.0 V
15
Vin = 10 V − 24 V
5
50
65
80
95
110 125
1.0 V < Vout < 1.8 V
3.3 V
2.5
2.5 V
2
Vout = 5.0 V
1.5
1
NCP3155A
5
20
35
50
65
80
95
0
25
110 125
30
35
40
45
50
55
60
65
70
75
TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 23. Low−Side MOSFET RDS(on) vs
Temperature
Figure 24. Derating Curve, 12 V Input
80
85
3.5
3.5
1.8 V
3
3
Vout = 5.0 V
3.3 V
2.5
OUTPUT CURRENT (A)
OUTPUT CURREENT (A)
35
0.5
0
−40 −25 −10
2.5 V
2
1.5
1
2
35
40
45
50
55
60
65
70
75
80
Vout = 5.0 V
3.3 V
1
NCP3155A
0
25
85
2.5 V
1.5
NCP3155A
30
12 V
2.5
0.5
0.5
0
25
20
Figure 22. High−Side MOSFET RDS(on) vs
Temperature
30
10
5
TEMPERATURE (°C)
Figure 21. Current Limit Waveforms (NCP3155B)
20
10
30
35
40
45
50
55
60
65
70
75
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 25. Derating Curve, 18 V Input
Figure 26. Derating Curve, 24 V Input
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80
85
NCP3155A, NCP3155B
TYPICAL PERFORMANCE CHARACTERISTICS
3.5
3.5
3
OUTPUT CURRENT (A)
1.0 to
1.2 V
Vout = 5.0 V
2.5
3.3 V
2.5 V
1.8 V
2
1.5
1
3.3 V
2.5 V
2
1.5
1
NCP3155B
0
25
1.8 V
Vout = 5.0 V
2.5
0.5
0.5
30
35
40
45
50
55
60
65
70
75
80
0
25
85
NCP3155B
30
35
40
45
50
55
60
65
70
75
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 27. Derating Curve, 12 V Input
Figure 28. Derating Curve, 18 V Input
3.5
2.5 V
3
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
3
2.5
12 V
Vout = 5.0 V
2
3.3 V
1.5
1
0.5
NCP3155B
0
25
30
35
40
45
50
55
60
65
70
75
TA, AMBIENT TEMPERATURE (°C)
Figure 29. Derating Curve, 24 V Input
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80
85
80
85
NCP3155A, NCP3155B
DETAILED DESCRIPTION
OVERVIEW
and low−side MOSFET gate drives to prevent cross
conduction of the power MOSFET’s.
The NCP3155A/B operates as a 500 kHz/1.0 MHz, voltage
mode, pulse width modulated, (PWM) synchronous buck
converter. It drives high−side and low−side N−channel power
MOSFETs. The NCP3155 incorporates an internal boost
circuit consisting of a boost clamp and boost diode to provide
supply voltage for the high side MOSFET gate driver. The
NCP3155 also integrates several protection features including
input undervoltage lockout (UVLO), output undervoltage
(OUV), output overvoltage (OOV), adjustable high−side
current limit (ISET and ILIM), and thermal shutdown (TSD).
The operational transconductance amplifier (OTA)
provides a high gain error signal from Vout which is
compared to the internal 1.5 V pk-pk ramp signal to set the
duty cycle converter using the PWM comparator. The high
side switch is turned on by the positive edge of the clock
cycle going into the PWM comparator and flip flop
following a non-overlap time. The high side switch is turned
off when the PWM comparator output is tripped by the
modulator ramp signal reaching a threshold level
established by the error amplifier. The gate driver stage
incorporates fixed non− overlap time between the high−side
POR and UVLO
The device contains an internal Power On Reset (POR) and
input Undervoltage Lockout (UVLO) that inhibits the internal
logic and the output stage from operating until VCC reaches its
respective predefined voltage levels (4.3 V typical).
Startup and Shutdown
Once VCC crosses the UVLO rising threshold the device
begins its startup process. Closed−loop soft−start begins
after a 400 ms delay wherein the boost capacitor is charged,
and the current limit threshold is set. During the 400 ms delay
the OTA output is set to just below the valley voltage of the
internal ramp. This is done to reduce delays and to ensure a
consistent pre−soft−start condition. The device increases the
internal reference from 0 V to 0.8 V in 32 discrete steps
while maintaining closed loop regulation at each step. Each
step contains 32 switching cycles. Some overshoot may be
evident at the start of each step depending on the voltage
loop phase margin and bandwidth. The total soft−start time
is 2.4 ms for the NCP3155A and 1.2 ms for the NCP3155B.
0.8 V Output Voltage
25 mV Steps
32 Voltage Steps
Internal Reference Voltage
Internal Ramp
OTA Output
0 .7V
0V
Figure 30. Soft−Start Details
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NCP3155A, NCP3155B
OOV and OUV
the output is considered “undervoltage” and the device will
initiate a restart. When the feedback pin voltage rises
between the reference voltages of comparator 1 and
comparator 2 (0.6 < VFB < 1.0), then the output voltage is
considered “Power Good.” Finally, if the feedback voltage
is greater than comparator 1 (VFB > 1.0 V), the output
voltage is considered “overvoltage,” and the device will
latch off. To clear a latch fault, input voltage must be
recycled. Graphical representation of the OOV and OUV is
shown in Figures 33 and 34.
The output voltage of the buck converter is monitored at
the feedback pin of the output power stage. Two
comparators are placed on the feedback node of the OTA to
monitor the operating window of the feedback voltage as
shown in Figures 31 and 32. All comparator outputs are
ignored during the soft−start sequence as soft−start is
regulated by the OTA and false trips would be generated.
After the soft−start period has ended, if the feedback is
below the reference voltage of comparator 2 (VFB < 0.6 V),
Soft Start Complete
Vref*125%
Comparator 1
Restart
LOGIC
FB
Latch off
Vref*75%
Comparator 2
Vref = 0.8 V
Figure 31. OOV and OUV Circuit Diagram
OOVP & Power Good = 0
Hysteresis = 5 mV
Voov = Vref * 125%
Power Not good High
Power Good = 1
Vref = 0.8 V
Power Good = 1
Hysteresis = 5 mV
OUVP & Power Good = 0
Figure 32. OOV and OUV Window Diagram
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Power Not Good Low
Vouv = Vref * 75%
NCP3155A, NCP3155B
1.0 V (vref *125%)
0.8 V (vref *100%)
0.6 V (vref *75%)
FB Voltage
Latch off
Reinitiate Softstart
Softstart Complete
Figure 33. Powerup Sequence and Overvoltage Latch
1.0 V (vref *125%)
0.8 V (vref *100%)
0.6 V (vref * 75%)
FB Voltage
Latch off
Reinitiate Softstart
Softstart Complete
Figure 34. Powerup Sequence and Undervoltage Soft−Start
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NCP3155A, NCP3155B
CURRENT LIMIT AND CURRENT LIMIT SET
ILimit block consists of a voltage comparator circuit which
compares the differential voltage across the VCC Pin and the
VSW Pin with a resistor settable voltage reference. The sense
portion of the circuit is only active while the HS MOSFET
is turned ON.
Overview
The NCP3155 uses the voltage drop across the High Side
MOSFET during the on time to sense inductor current. The
VIN
VCC
VSense
Ilim Out
Itrip Ref
Switch
Cap
VSW
CONTROL
Iset
13 uA
6
Vset
DAC /
COUNTER
ISET
RSet
PGND
Itrip Ref−63 Steps, 6.51 mV/step
Figure 35. Iset / ILimit Block Diagram
Current Limit Set
prior to Soft−Start, the DAC counter increments the
reference on the ISET comparator until it crosses the VSET
voltage and holds the DAC reference output to that count
value. This voltage is translated to the ILimit comparator
during the ISense portion of the switching cycle through the
switch cap circuit. See Figure 35. Exceeding the maximum
sense voltage results in no current limit. Steps 0 to 10 result
in an effective current limit of 0 mV.
The ILimit comparator reference is set during the startup
sequence by forcing a typically 13 mA current through the
low side gate drive resistor. The gate drive output will rise
to a voltage level shown in the equation below:
V set + I set * R set
(eq. 1)
Where ISET is 13 mA and RSET is the gate to source resistor
on the low side MOSFET.
This resistor is normally installed to prevent MOSFET
leakage from causing unwanted turn on of the low side
MOSFET. In this case, the resistor is also used to set the
ILimit trip level reference through the ILimit DAC. The Iset
process takes approximately 350 ms to complete prior to
Soft−Start stepping. The scaled voltage level across the ISET
resistor is converted to a 6 bit digital value and stored as the
trip value. The binary ILimit value is scaled and converted to
the analog ILimit reference voltage through a DAC counter.
The DAC has 63 steps in 6.51 mV increments equating to a
maximum sense voltage of 403 mV. During the Iset period
Current Sense Cycle
Figure 36 shows how the current is sampled as it relates
to the switching cycle. Current level 1 in Figure 36
represents a condition that will not cause a fault. Current
level 2 represents a condition that will cause a fault. The
sense circuit is allowed to operate below the 3/4 point of a
given switching cycle. A given switching cycle’s 3/4 Ton
time is defined by the prior cycle’s Ton and is quantized in
10 ns steps. A fault occurs if the sensed MOSFET voltage
exceeds the DAC reference within the 3/4 time window of
the switching cycle.
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13
NCP3155A, NCP3155B
Trip:
Vsense > Itrip Ref at 3/4 Point
No Trip:
Vsense < Itrip Ref at 3/4 Point
Itrip Ref
Vsense
¾
¾
Current Level 1
Ton−1
Ton−2
Current Level 2
3/4 Point Determined by
Prior Cycle
1/4
1/2
1/4
1/2
3/4
3/4
Ton−1
Ton
Each switching cycle’s Ton is counted in 10 nS time steps. The 3/4 sample time
value is held and used for the following cycle’s limit sample time
Figure 36. ILimit Trip Point Description
Soft−Start Current limit
VOUT = Output Voltage (V)
FSW = Switching Frequency (Hz)
During soft−start the ISET value is doubled to allow for
inrush current to charge the output capacitance. The DAC
reference is set back to its normal value after soft−start has
completed.
Boost Clamp Functionality
The boost circuit requires an external capacitor connected
between the BST and VSW pins to store charge for supplying
the high and low−side gate driver voltage. This clamp circuit
limits the driver voltage to typically 7.5 V when VIN > 9 V,
otherwise this internal regulator is in dropout and typically
VIN − 1.25 V.
The boost circuit regulates the gate driver output voltage
and acts as a switching diode. A simplified diagram of the
boost circuit is shown in Figure 37. While the switch node
is grounded, the sampling circuit samples the voltage at the
boost pin, and regulates the boost capacitor voltage. The
sampling circuit stores the boost voltage while the VSW is
high and the linear regulator output transistor is reversed
biased.
VSW Ringing
The ILimit block can lose accuracy if there is excessive
VSW voltage ringing that extends beyond the 1/2 point of the
high−side transistor on−time. Proper snubber design and
keeping the ratio of ripple current and load current in the
10−30% range can help alleviate this as well.
Current Limit
A current limit trip results in completion of one switching
cycle and subsequently half of another cycle Ton to account
for negative inductor current that might have caused
negative potentials on the output. Subsequently the power
MOSFETs are both turned off and a 4 soft−start time period
wait passes before another soft−start cycle is attempted.
VIN
Iave vs Trip Point
8.9V
The average load trip current versus RSET value is shown
the equation below:
I AveTRIP +
I set
R set
R DS(on)
*
ƪ
1 V IN * V OUT
4
L
ƫ
V OUT
1
V IN
F SW
Switch
Sampling
Circuit
BST
VSW
(eq. 2)
Where:
L = Inductance (H)
ISET = 13 mA
RSET = Gate to Source Resistance (W)
RDS(on) = On Resistance of the HS MOSFET (48 mW)
VIN = Input Voltage (V)
LSDR
Figure 37. Boost Circuit
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14
NCP3155A, NCP3155B
over several switching cycles is shown in Region 2 (Yellow).
The boost ripple frequency is dependent on the output
capacitance selected. The ripple voltage will not damage the
device or $12 V gate rated MOSFETs.
Conditions where maximum boost ripple voltage could
damage the device or $12 V gate rated MOSFETs can be
seen in Region 3 (Orange). Placing a boost capacitor that is
no greater than 3.3 nF on the boost pin limits the maximum
boost voltage < 12 V. The typical drive waveforms for
Regions 1, 2 and 3 (green, yellow, and orange) regions of
Figure 38 are shown in Figure 39.
Reduced sampling time occurs at high duty cycles where
the low side MOSFET is off for the majority of the switching
period. Reduced sampling time causes errors in the
regulated voltage on the boost pin. High duty cycle / input
voltage induced sampling errors can result in increased
boost ripple voltage or higher than desired DC boost voltage.
Figure 38 outlines all operating regions.
The recommended operating conditions are shown in
Region 1 (Green) where a 0.1 mF, 25 V ceramic capacitor
can be placed on the boost pin without causing damage to the
device or MOSFETS. Larger boost ripple voltage occurring
BOOST VOLTAGE LEVELS
Normal Operation
Increased Boost Ripple
Increased Boost Ripple
(Region 1)
(Still in Specification)
Capacitor Optimization
(Region 2)
Required (Region 3)
24
Region 3
22
22V
20
INPUT VOLTAGE
18
Region 1
16
Max
Duty
Cycle
Region 2
14
12
11.5V
10
71%
8
6
4
2
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
DUTY CYCLE
Figure 38. Safe Operating Area for Boost Voltage with a 0.1 mF Capacitor
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15
85
90
NCP3155A, NCP3155B
VIN
7.5V
VBOOST
7.5V
0V
Maximum
Normal
VIN
7.5V
VBOOST
7.5V
0V
Maximum
Normal
VIN
7.5V
VBOOST
7.5V
0V
Figure 39. Typical Waveforms for Region 1 (top), Region 2 (middle), and Region 3 (bottom)
To illustrate, a 0.1 mF boost capacitor operating at > 80% duty cycle and > 22.5 V input voltage will exceed the specifications
for the driver supply voltage. See Figure 40.
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16
NCP3155A, NCP3155B
Boost Voltage
18
Voltage Ripple
Maximum Allowable Voltage
Maximum Boost Voltage
16
14
Boost Voltage (V)
12
10
8
6
4
2
0
4.5
6.5
8.5
10.5
12.5
14.5
16.5
18.5
Input Voltage (V)
20.5
22.5
24.5
26.5
Figure 40. Boost Voltage at 80% Duty Cycle
Inductor Selection
D+
When selecting the inductor, it is important to know the
input and output requirements. Some example conditions
are listed below to assist in the process.
V OUT ) V LSD
V IN * V HSD ) V LSD
³ 27.5% +
Table 1. DESIGN PARAMETERS
Design Parameter
(VIN)
9 V to 16 V
Nominal Input Voltage
(VIN)
12 V
(VOUT)
3.3 V
Output Voltage
Input ripple voltage
300 mV
Output ripple voltage
(VOUTRIPPLE)
50 mV
Output current rating
(IOUT)
3A
Operating frequency
(Fsw)
500 kHz
D+
T ON
T
1
T
(* D Ǔ +
L+
+
T
12 V
DI
I OUT
(eq. 6)
V OUT
I OUT @ ra @ F SW
@ (1 * D) ³ 8.2 mH
3.3 V
3 A @ 20% @ 500 kHz
(eq. 7)
@ (1 * 27.5%)
The relationship between ra and L for this design example
is shown in Figure 41.
(eq. 3)
T OFF
(eq. 5)
The designer should employ a rule of thumb where the
percentage of ripple current in the inductor lies between
10% and 40%. When using ceramic output capacitors the
ripple current can be greater thus a user might select a higher
ripple current, but when using electrolytic capacitors a lower
ripple current will result in lower output ripple. Now,
acceptable values of inductance for a design can be
calculated using Equation 7.
A buck converter produces input voltage (VIN) pulses that
are LC filtered to produce a lower dc output voltage (VOUT).
The output voltage can be changed by modifying the on time
relative to the switching period (T) or switching frequency.
The ratio of high side switch on time to the switching period
is called duty cycle (D). Duty cycle can also be calculated
using VOUT, VIN, the low side switch voltage drop VLSD,
and the High side switch voltage drop VHSD.
F+
V IN
3.3 V
ra +
(VINRIPPLE)
V OUT
The ratio of ripple current to maximum output current
simplifies the equations used for inductor selection. The
formula for this is given in Equation 6.
Example Value
Input Voltage
[D+
(eq. 4)
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17
NCP3155A, NCP3155B
20
L, INDUCTANCE (mH)
18
16
18 V−In
14
I PP +
Vout = 3.3 V
10
8
9 V−In
6
4
2
0
10%
15%
20%
25%
VIN, (V)
30%
35%
40%
LP CU + I RMS 2 @ DCR
To keep within the bounds of the parts maximum rating,
calculate the RMS current and peak current.
+3A@
ǒ
I PK + I OUT @ 1 )
Ǹ1 ) ra12 ³ 3.01 A
2
Ǹ
Input Capacitor Selection
ǒ
(0.2)
ra
³ 3.3 A + 3 A @ 1 )
2
2
Ǔ
LP tot + LP CU_DC ) LP CU_AC ) LP Core (eq. 13)
(eq. 8)
(0.2) 2
1)
12
The input capacitor has to sustain the ripple current
produced during the on time of the upper MOSFET, so it
must have a low ESR to minimize the losses. The RMS value
of this ripple is:
Ǔ
(eq. 9)
An inductor for this example would be around 8.2 mH and
should support an rms current of 3.01 A and a peak current
of 3.3 A.
The final selection of an output inductor has both
mechanical and electrical considerations. From a
mechanical perspective, smaller inductor values generally
correspond to smaller physical size. Since the inductor is
often one of the largest components in the regulation system,
a minimum inductor value is particularly important in
space−constrained applications. From an electrical
perspective, the maximum current slew rate through the
output inductor for a buck regulator is given by Equation 10.
SlewRate LOUT +
V IN * V OUT
L OUT
³ 1.1
(eq. 12)
The core losses and ac copper losses will depend on the
geometry of the selected core, core material, and wire used.
Most vendors will provide the appropriate information to
make accurate calculations of the power dissipation then the
total inductor losses can be capture buy the equation below:
Figure 41. Ripple Current Ratio vs. Inductance
I RMS + I OUT @
(eq. 11)
L OUT @ F SW
Ipp is the peak to peak current of the inductor. From this
equation it is clear that the ripple current increases as LOUT
decreases, emphasizing the trade−off between dynamic
response and ripple current.
The power dissipation of an inductor consists of both
copper and core losses. The copper losses can be further
categorized into dc losses and ac losses. A good first order
approximation of the inductor losses can be made using the
DC resistance as they usually contribute to 90% of the losses
of the inductor shown below:
12 V−In
12
V OUT(1 * D)
Iin RMS + I OUT @ ǸD @ (1 * D)
(eq. 14)
D is the duty cycle, IinRMS is the input RMS current, and
IOUT is the load current.
The equation reaches its maximum value with D = 0.5.
Loss in the input capacitors can be calculated with the
following equation:
P CIN + ESR CIN @ ǒI IN*RMSǓ
2
(eq. 15)
PCIN is the power loss in the input capacitors and ESRCIN
is the effective series resistance of the input capacitance.
Due to large dI/dt through the input capacitors, electrolytic
or ceramics should be used. If a tantalum must be used, it
must by surge protected. Otherwise, capacitor failure could
occur.
12 V * 3.3 V
A
+
ms
8.2 mH
(eq. 10)
This equation implies that larger inductor values limit the
regulator’s ability to slew current through the output
inductor in response to output load transients. Consequently,
output capacitors must supply the load current until the
inductor current reaches the output load current level. This
results in larger values of output capacitance to maintain
tight output voltage regulation. In contrast, smaller values of
inductance increase the regulator’s maximum achievable
slew rate and decrease the necessary capacitance, at the
expense of higher ripple current. The peak−to−peak ripple
current for the NCP3155A is given by the following
equation:
Input Start−up Current
To calculate the input startup current, the following
equation can be used.
I INRUSH +
C OUT @ V OUT
t SS
(eq. 16)
Iinrush is the input current during startup, COUT is the total
output capacitance, VOUT is the desired output voltage, and
tSS is the soft start interval. If the inrush current is higher than
the steady state input current during max load, then the input
fuse should be rated accordingly, if one is used.
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NCP3155A, NCP3155B
Output Capacitor Selection
2
The important factors to consider when selecting an
output capacitor is dc voltage rating, ripple current rating,
output ripple voltage requirements, and transient response
requirements.
The output capacitor must be rated to handle the ripple
current at full load with proper derating. The RMS ratings
given in datasheets are generally for lower switching
frequency than used in switch mode power supplies but a
multiplier is usually given for higher frequency operation.
The RMS current for the output capacitor can be calculated
below:
Co RMS + I O @
ra
Ǹ12
DV OUT−DISCHG +
ǒ
(eq. 17)
Ǔ
1
8 @ F SW @ Co
ESL @ I PP @ F SW
V ESLOFF +
D
ESL @ I PP @ F SW
(1 * D )
DV OUT−CHG +
ǒI TRANǓ @ LOUT
(eq. 23)
C OUT @ V OUT
As with any power design, proper laboratory testing should
be performed to insure the design will dissipate the required
power under worst case operating conditions. Variables
considered during testing should include maximum ambient
temperature, minimum airflow, maximum input voltage,
maximum loading, and component variations.
(eq. 18)
Feedback and Compensation
The NCP3155 is a voltage mode buck convertor with a
transconductance error amplifier compensated by an
external compensation network. Compensation is needed to
achieve accurate output voltage regulation and fast transient
response. The goal of the compensation circuit is to provide
a loop gain function with the highest crossing frequency and
adequate phase margin (minimally 45°). The transfer
function of the power stage (the output LC filter) is a double
pole system. The resonance frequency of this filter is
expressed as follows:
(eq. 19)
(eq. 20)
The output capacitor is a basic component for the fast
response of the power supply. In fact, during load transient,
for the first few microseconds it supplies the current to the
load. The controller immediately recognizes the load
transient and sets the duty cycle to maximum, but the current
slope is limited by the inductor value.
During a load step transient the output voltage initially drops
due to the current variation inside the capacitor and the ESR
(neglecting the effect of the effective series inductance (ESL)).
DV OUT−ESR + DI TRAN @ ESR Co
(eq. 22)
2
The ESL of capacitors depends on the technology chosen
but tends to range from 1 nH to 20 nH where ceramic
capacitors have the lowest inductance and electrolytic
capacitors then to have the highest. The calculated
contributing voltage ripple from ESL is shown for the switch
on and switch off below:
V ESLON +
C OUT @ ǒV IN * V OUTǓ
In a typical converter design, the ESR of the output capacitor
bank dominates the transient response. It should be noted
that DVOUT−DISCHARGE and DVOUT−ESR are out of
phase with each other, and the larger of these two voltages
will determine the maximum deviation of the output voltage
(neglecting the effect of the ESL).
Conversely during a load release, the output voltage can
increase as the energy stored in the inductor dumps into the
output capacitor. The ESR contribution from Equation 18
still applies in addition to the output capacitor charge which
is approximated by the following equation:
The maximum allowable output voltage ripple is a
combination of the ripple current selected, the output
capacitance selected, the equivalent series inductance (ESL)
and ESR.
The main component of the ripple voltage is usually due to
the ESR of the output capacitor and the capacitance selected.
V ESR_C + I O @ ra @ ESR Co )
ǒI TRANǓ @ LOUT
f P0 +
1
2 @ p @ ǸL @ C OUT
(eq. 24)
Parasitic Equivalent Series Resistance (ESR) of the
output filter capacitor introduces a high frequency zero to
the filter network. Its value can be calculated by using the
following equation:
f Z0 +
(eq. 21)
A minimum capacitor value is required to sustain the
current during the load transient without discharging it. The
voltage drop due to output capacitor discharge is
approximated by the following equation:
1
2 @ p @ C OUT @ ESR
(eq. 25)
The main loop zero crossover frequency f0 can be chosen
to be 1/10 − 1/5 of the switching frequency. Table 2 shows
the three methods of compensation.
Table 2. COMPENSATION TYPES
Zero Crossover Frequency Condition
Compensation Type
Typical Output Capacitor Type
fP0 < fZ0 < f0 < fS/2
Type II
Electrolytic, Tantalum
fP0 < f0 < fZ0 < fS/2
Type III Method I
Tantalum, Ceramic
fP0 < f0 < fS/2 < fZ0
Type III Method II
Ceramic
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19
NCP3155A, NCP3155B
Compensation Type II
This compensation is suitable for electrolytic capacitors.
Components of the Type II (Figure 42) network can be
specified by the following equations:
f Z1 + 0.75 @ f P0
(eq. 30)
f Z2 + f P0
(eq. 31)
f P2 + f Z0
(eq. 32)
fS
f P3 +
(eq. 33)
2
Method II is better suited for ceramic capacitors that
typically have the lowest ESR available:
Figure 42. Type II Compensation
R C1 +
2 @ p @ f 0 @ L @ V RAMP @ V OUT
ESR @ V IN @ V ref @ gm
1
0.75 @ 2 @ p @ f P0 @ R C1
(eq. 27)
C C2 +
1
p @ R C1 @ f S
(eq. 28)
R1 +
V OUT * V ref
V ref
@ R2
sinq max
Ǹ11 )* sin
q max
(eq. 34)
f P2 + f 0 @
sin q max
Ǹ11 *) sin
q max
(eq. 35)
f Z1 + 0.5 @ f Z2
(eq. 36)
f P3 + 0.5 @ f S
(eq. 37)
qmax is the desired maximum phase margin at the zero
crossover frequency, ƒ0. It should be 45° − 75°. Convert
degrees to radians by the formula:
(eq. 26)
C C1 +
f Z2 + f 0 @
ǒ
Ǔ
q max + q max degress @ 2 @ p : Units + radians
360
(eq. 38)
The remaining calculations are the same for both methods.
R C1 u u
(eq. 29)
VRAMP is the peak−to−peak voltage of the oscillator ramp
and gm is the transconductance error amplifier gain.
Capacitor CC2 is optional.
Compensation Type III
1
2 @ p @ f Z1 @ R C1
(eq. 40)
C C2 +
1
2 @ p @ f P3 @ R C1
(eq. 41)
R FB1 +
R1 +
R2 +
(eq. 39)
C C1 +
C FB1 +
Tantalum and ceramics capacitors have lower ESR than
electrolytic, so the zero of the output LC filter goes to a
higher frequency above the zero crossover frequency. This
requires a Type III compensation network as shown in
Figure 43.
There are two methods to select the zeros and poles of this
compensation network. Method I is ideal for tantalum
output capacitors, which have a higher ESR than ceramic:
2
gm
2 @ p @ f 0 @ L @ V RAMP @ C OUT
V IN @ R C1
1
2p @ C FB1 @ f P2
(eq. 43)
1
* R FB1
2 @ p @ C FB1 @ f Z2
V
ref
V OUT * V ref
(eq. 42)
(eq. 44)
@ R1
(eq. 45)
If the equation in Equation 46 is not true, then a higher value
of RC1 must be selected.
R1 @ R2 @ R FB1
R1 @ R FB1 ) R2 @ R FB1 ) R1 @ R2
Figure 43. Type III Compensation
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20
u
1
(eq. 46)
gm
NCP3155A, NCP3155B
Output Current Derating
14
VOUT, OUTPUT VOLTAGE (V)
The NCP3155 has a wide input voltage and output voltage
capability. It also operates in a variety of thermal
environments. These thermal conditions limit the maximum
output current for a given input and output voltage.
Therefore, proper output current derating must be
considered, taking into account ambient temperature,
airflow, the input and output conditions, and the need for
increased reliability. Figures 24 − 29 show safe operating
conditions vs. output current for input voltages of 12 V,
18 V, and 24 V. These curves assumed 300 mm2 of 2 oz
copper. Sufficient cooling could also be provided to ensure
reliable operation. Finally, to maintain operation in the safe
operating areas shown in the curves, it is recommended to
use the NCP3155 with input to output conditions as shown
in Figure 44.
12
10
8
6
4
2
0
4
6
8
10
12
14
16
18
20
22
VIN, INPUT VOLTAGE (V)
Figure 44. Recommended Maximum Output
Voltage vs Input Voltage
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21
24
NCP3155A, NCP3155B
0.1m
10.8 – 24 V
VIN
VIN
150m
BST
22m
NCP3155A
8.2m
5V
VSW
VOUT
680p
PGND
47m
820p
47m
19.62k
1.5
649
ISET
FB1
COMP
1.8n
AGND
33p
24k
R1
18.2k
VOUT (V)
R1 (kW)
1.2
39.2k
1.5
22.1k
3.3
6.19k
5.0
3.74k
Figure 45. Typical Application Circuit
0.1m
9 − 16 V
VIN
VIN
150m
BST
22m
NCP3155B
4.7m
1.8 V
VSW
PGND
VOUT
680p
1.5
220m
2.2n
220m
6.21k
649
ISET
FB1
12n
COMP
AGND
220p
22.1k
4.99k
4.7k
Figure 46. Typical Application Circuit
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22
NCP3155A, NCP3155B
0.1m
10.8 − 14 V
VIN
VIN
150m
BST
22m
NCP3155B
4.7m
3.3 V
VSW
VOUT
680p
PGND
22m
560p
22m
19.62k
1.5
270
ISET
FB1
COMP
1.2n
AGND
10p
24k
6.19k
27k
Figure 47. Typical Application Circuit
0.1m
10 − 14 V
VIN
VIN
150m
BST
22m
NCP3155B
4.7m
3.3 V
VSW
PGND
VOUT
680p
1.5
220m
680p
10m
15.8k
580
ISET
FB1
8.2n
COMP
AGND
150p
22.1k
4.99k
6.8k
Figure 48. Typical Application Circuit
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23
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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