NCP3334
Voltage Regulator - High
Accuracy, Ultra Low Iq,
Adjustable, Low Dropout
500 mA
The NCP3334 is a high performance, low dropout regulator. With
accuracy of ±0.9% over line and load and ultra−low quiescent current
and noise it encompasses all of the necessary features required by
today’s consumer electronics. This unique device is guaranteed to be
stable without a minimum load current requirement and stable with
any type of capacitor as small as 1.0 mF. The NCP3334 offers reverse
bias protection.
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MARKING
DIAGRAM
8
SOIC−8
CASE 751
8
1
1
Features
•
•
•
•
•
•
•
•
•
•
•
•
High Accuracy Over Line and Load (±0.9% at 25°C)
Ultra−Low Dropout Voltage
Low Noise
Low Shutdown Current (0.07 mA)
Reverse Bias Protected
2.6 V to 12 V Supply Range
Thermal Shutdown Protection
Current Limitation
Requires Only 1.0 mF Output Capacitance for Stability
Stable with Any Type of Capacitor (including MLCC)
No Minimum Output Current Required for Stability
This is a Pb−Free Device
A
L
Y
W
G
GND
SD
IN
IN
October, 2019 − Rev. 2
1
8
NC
FB
OUT
OUT
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
PCMCIA Card
Cellular Phones
Camcoders and Cameras
Networking Systems, DSL/Cable Modems
Cable Set−Top Box
MP3/CD Players
DSP Supply
Displays and Monitors
© Semiconductor Components Industries, LLC, 2006
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
Applications
•
•
•
•
•
•
•
•
3334
ALYW
G
1
Publication Order Number:
NCP3334/D
NCP3334
OUT
3
4
Vin
Cin
1.0 mF
OUT
IN
FB
IN
6
5
7
+
Vout
+
Cout
1.0 mF
R2
GND
SD
2
CADJ
68 pF
R1
1
ON
OFF
Figure 1. Typical Adjustable Version Application Schematic
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Description
1
GND
2
SD
Shutdown pin. When not in use, this pin should be connected to the input pin.
3, 4
IN
Power Supply Input Voltage
5, 6
OUT
7
FB
Feedback pin; reference voltage = 1.25 V.
8
NC
Not Connected
Power Supply Ground
Regulated output voltage. Bypass to ground with Cout w 1.0 mF.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Input Voltage
Vin
−0.3 to +16
V
Output Voltage
Vout
−0.3 to Vin +0.3 or 10 V*
V
Shutdown Pin Voltage
Vsh
−0.3 to +16
V
Thermal Characteristics
Thermal Resistance, Junction−to−Air
RqJA
238
°C/W
Operating Junction Temperature Range
TJ
−40 to +150
°C
Storage Temperature Range
Tstg
−50 to+150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) JESD 22−A114−B
Machine Model (MM) JESD 22−A115−A
*Whichever is less. Reverse bias protection feature valid only if Vout − Vin ≤ 7.0 V.
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2
NCP3334
ELECTRICAL CHARACTERISTICS (Vout = 1.25 V (Vref) typical, Vin = 2.9 V, TA = −40°C to +85°C, unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
Reference Voltage Accuracy
Vin = 2.9 V to Vout + 4.0 V, IL = 0.1 mA to 500 mA, TA = 25°C
VREF
−0.9%
1.239
1.25
+0.9%
1.261
V
Reference Voltage Accuracy
Vin = 2.9 V to Vout + 4.0 V, IL = 0.1 mA to 500 mA, TA = 0°C to +85°C
VREF
−1.4%
1.233
1.25
+1.4%
1.268
V
Reference Voltage Accuracy (Note 1)
Vin = 2.9 V to Vout + 4.0 V, IL = 0.1 mA to 500 mA, TA = −40°C to +150°C
VREF
−1.5%
1.231
1.25
+1.5%
1.269
V
Line Regulation
Vin = 2.9 V to 12 V, IL = 0.1 mA
LineReg
0.04
mV/V
Load Regulation
Vin = 2.9 V, IL = 0.1 mA to 500 mA
LoadReg
0.04
mV/mA
Dropout Voltage, Vout = 2.5 V to 10 V
IL = 500 mA (Note 2)
IL = 300 mA
IL = 50 mA
IL = 0.1 mA
VDrop
Peak Output Current (Notes 1 and 2) (See Figure 6)
Ipk
Short Output Current (See Figure 6)
Vout ≤ 3.3 V
Vout > 3.3 V
340
230
110
10
500
Isc
Thermal Shutdown
TJSD
Ground Current
In Regulation
IL = 500 mA (Note 2)
IL = 300 mA (Note 2)
IL = 50 mA
IL = 0.1 mA
IGND
In Shutdown
VSD = 0 V
IGNDsh
Output Noise
IL = 500 mA, f = 10 Hz to 100 kHz, Cout = 10 mF
Vnoise
Shutdown
Threshold Voltage ON
Threshold Voltage OFF
VTHSD
SD Input Current, VSD = 0 V to 0.4 V or VSD = 2.0 V to Vin
Vin ≤ 5.4 V
Vin > 5.4 V
700
860
mA
990
900
1300
mA
160
In Dropout
Vin = Vout −0.1 V, IL = 0.1 mA
mV
°C
9.0
4.6
0.8
−
14
7.5
2.5
190
mA
−
500
mA
0.07
1.0
mA
38
2.0
mA
mVrms
0.4
V
V
ISD
0.07
1.0
5.0
mA
Output Current In Shutdown Mode, Vout = 0 V
IOSD
0.07
1.0
mA
Reverse Bias Protection, Current Flowing from the Output Pin to GND
(Vin = 0 V, Vout_forced = Vout (nom) ≤ 7 V) (Note 3)
IOUTR
1.0
mA
RECOMMENDED OPERATING CONDITIONS
Input Voltage
VIN
1. For output current capability for TJ < 0°C, please refer to Figure 8.
2. TA must be greater than 0°C.
3. Reverse bias protection feature valid only if Vout − Vin ≤ 7.0 V.
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3
2.6
12
V
NCP3334
400
12
350
250
200
150
50 mA
100
0
20
40
60
80
100
120
300 mA
4
TJ (°C)
0
80
TJ (°C)
Figure 2. Dropout Voltage vs. Temperature
Figure 3. Ground Current vs. Temperature
1.275
1000
1.270
900
1.265
800
1.260
700
1.255
1.250
1.245
1.240
20
40
60
100
120
140
Isc
Ipk
600
500
400
300
1.235
200
1.230
100
1.225
−40
50 mA
0
140
Ipk (mA), Isc (mA)
VOUT (V)
6
2
50
0
500 mA
8
300 mA
IGND (mA)
VDO (mV)
10
500 mA
300
0
−20
0
20
40
60
80
100
120
0
140
20
40
60
80
100
120
TJ (°C)
TJ (°C)
Figure 4. Output Voltage vs. Temperature
Figure 5. Peak and Short Current
vs. Temperature
140
100
Vout (V)
RR, RIPPLE REJECTION (dB)
0.97
Vout
90
80
70
50
500 mA
40
30
20
10
Vout = 2.5 V
Cout = 10 mF
TJ = 25°C
0
0.01
Ipk
Isc
Iout (mA)
(For specific values of Ipk and Isc, please refer to Figure 5)
50 mA
250 mA
60
0.1
1.0
10
F, FREQUENCY (kHz)
Figure 6. Output Voltage vs. Output Current
Figure 7. Ripple Rejection vs. Frequency
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4
100
NCP3334
0.8
15
0.7
Vin at Data Sheet Test Conditions,
25°C, 1 mF Capacitance
−10°C
0°C
0.5
MAXIMUM ESR (W)
IOUT, (A)
0.6
−40°C
0.4
−30°C
0.3
−20°C
0.2
10
Unstable Area
5.0
0.1
0
Stable Area
3.5 3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
0
2.6 2.5
0
100
200
300
400
VIN, (V)
OUTPUT CURRENT (mA)
Figure 8. Output Current Capability when set
at 2.5 V Vout
Figure 9. Stability with ESR vs. Iout
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5
500
NCP3334
APPLICATIONS INFORMATION
Reverse Bias Protection
Adjustable Operation
Reverse bias is a condition caused when the input voltage
goes to zero, but the output voltage is kept high either by a
large output capacitor or another source in the application
which feeds the output pin.
Normally in a bipolar LDO all the current will flow from
the output pin to input pin through the PN junction with
limited current capability and with the potential to destroy
the IC.
Due to an improved architecture, the NCP3334 can
withstand up to 7.0 V on the output pin with virtually no
current flowing from output pin to input pin, and only
negligible amount of current (tens of mA) flowing from the
output pin to ground for infinite duration.
Operation with output voltages in the range of 7 to 10 volts
requires that the output to input voltage differential be less
than 7 volts.
The output voltage can be set by using a resistor divider
as shown in Figure 1 with a range of 1.25 to 10 V. The
appropriate resistor divider can be found by solving the
equation below. The recommended current through the
resistor divider is from 10 mA to 100 mA. This can be
accomplished by selecting resistors in the kW range. As
result, the Iadj*R2 becomes negligible in the equation and
can be ignored.
Input Capacitor
The voltage dropout is measured at 97% of the nominal
output voltage.
ǒ
Ǔ
Vout + 1.25 * 1 ) R1 ) Iadj * R2
R2
(eq. 1)
Example:
For Vout = 2.9 V, can use R1 = 36 kW and R2 = 27 kW.
ǒ
1.25 * 1 )
Ǔ
36 kW
+ 2.91 V
27 kW
(eq. 2)
Dropout Voltage
An input capacitor of at least 1.0 mF, any type, is
recommended to improve the transient response of the
regulator and/or if the regulator is located more than a few
inches from the power source. It will also reduce the circuit’s
sensitivity to the input line impedance at high frequencies.
The capacitor should be mounted with the shortest possible
track length directly across the regulator’s input terminals.
Thermal Considerations
Internal thermal limiting circuitry is provided to protect the
integrated circuit in the event that the maximum junction
temperature is exceeded. This feature provides protection
from a catastrophic device failure due to accidental
overheating. This protection feature is not intended to be used
as a substitute to heat sinking. The maximum power that can
be dissipated, can be calculated with the equation below:
Output Capacitor
The NCP3334 remains stable with any type of capacitor
as long as it fulfills its 1.0 mF requirement. There are no
constraints on the minimum ESR and it will remain stable up
to an ESR of 5.0 W. Larger capacitor values will improve the
noise rejection and load transient response.
PD +
TJ(max) * TA
RqJA
(eq. 3)
For improved thermal performance, contact the factory
for the DFN package option. The DFN package includes an
exposed metal pad that is specifically designed to reduce the
junction to air thermal resistance, RqJA.
Noise Reduction
A 68 pF capacitor connected in parallel with R1 (see
Figure 1) is recommended to reduce output noise and
improve stability.
ORDERING INFORMATION
Package
Shipping†
NCP3334DADJG
SO−8
(Pb−Free)
98 Units / Rail
NCP3334DADJR2G
SO−8
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
The products described herein NCP3334, may be covered by one or more of the following U.S. patents; 5,920,184, 5,966,004, and 5,834,926. There may be
other patents pending.
Micro8 is a trademark of International Rectifier.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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