NCP3418APDR2

NCP3418, NCP3418A Dual Bootstrapped 12 V MOSFET Driver with Output Disable The NCP3418 and NCP3418A are dual MOSFET gate drivers optimized to drive the gates of both high−side and low−side power MOSFETs in a synchronous buck converter. Each of the drivers is capable of driving a 3000 pF load with a 25 ns propagation delay and a 20 ns transition time. With a wide operating voltage range, high or low side MOSFET gate drive voltage can be optimized for the best efficiency. Internal, adaptive nonoverlap circuitry further reduces switching losses by preventing simultaneous conduction of both MOSFETs. The floating top driver design can accommodate VBST voltages as high as 30 V, with transient voltages as high as 35 V. Both gate outputs can be driven low by applying a low logic level to the Output Disable (OD) pin. An Undervoltage Lockout function ensures that both driver outputs are low when the supply voltage is low, and a Thermal Shutdown function provides the IC with overtemperature protection. The NCP3418A is identical to the NCP3418 except that there is no internal charge pump diode. The NCP3418 is pin−to−pin compatible with Analog Devices ADP3418 with the following advantages: Features http://onsemi.com MARKING DIAGRAMS 8 8 1 SO−8 D SUFFIX CASE 751 1 8 8 1 SO−8 EP PD SUFFIX CASE 751AC 1 341x = Device Code x = 8 or 8A A = Assembly Location L = Wafer Lot Y = Year WW, W = Work Week G = Pb−Free Package 341x ALYW 341X AYWW G • • • • • • • • • • • • • Faster Rise and Fall Times Internal Charge Pump Diode Reduces Cost and Parts Count Thermal Shutdown for System Protection Integrated OVP Internal Pulldown Resistor Suppresses Transient Turn On of Either MOSFET Anti Cross−Conduction Protection Circuitry Floating Top Driver Accommodates Boost Voltages of up to 30 V One Input Signal Controls Both the Upper and Lower Gate Outputs Output Disable Control Turns Off Both MOSFETs Complies with VRM 10.x Specifications Undervoltage Lockout Thermally Enhanced Package Available Pb−Free Package is Available PIN CONNECTIONS BST IN OD VCC 1 8 DRVH SW PGND DRVL ORDERING INFORMATION Device NCP3418D NCP3418DR2 NCP3418ADR2 NCP3418ADR2G NCP3418PDR2 NCP3418APDR2 Package SO−8 SO−8 SO−8 SO−8 (Pb−Free) SO−8 EP SO−8 EP Shipping† 98 Units/Rail 2500/Tape & Reel 2500/Tape & Reel 2500/Tape & Reel 2500/Tape & Reel 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2006 1 May, 2006 − Rev. 12 Publication Order Number: NCP3418/D NCP3418, NCP3418A VCC 4 Not present in the NCP3418A 1 BST IN 2 8 100 k 7 Nonoverlap − + 1.5 V − + 120 k SW DRVH 4V 5 DRVL OD 3 6 PGND Figure 1. NCP3418/A Block Diagram PIN DESCRIPTION Pin 1 Symbol BST Description Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds this bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value is between 100 nF and 1.0 mF. An external diode will be needed with the NCP3418A. Logic−Level Input. This pin has primary control of the drive outputs. Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low. Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND. Output drive for the lower MOSFET. Power Ground. Should be closely connected to the source of the lower MOSFET. Switch Node. Connect to the source of the upper MOSFET. Output drive for the upper MOSFET. 2 3 4 5 6 7 8 IN OD VCC DRVL PGND SW DRVH http://onsemi.com 2 NCP3418, NCP3418A MAXIMUM RATINGS Rating Operating Ambient Temperature, TA Operating Junction Temperature, TJ (Note 1) Package Thermal Resistance: SO−8 Junction−to−Case, RqJC Junction−to−Ambient, RqJA (2−Layer Board) Package Thermal Resistance: SO−8 EP Junction−to−Ambient, RqJA (Note 2) Storage Temperature Range, TS Lead Temperature Soldering (10 sec): Reflow (SMD styles only) JEDEC Moisture Sensitivity Level Standard (Note 3) Lead Free (Note 4) SO−8 (240 peak profile) SO−8 (260 peak profile) SO−8 EP (240 peak profile) SO−8 EP (260 peak profile) Value 0 to 85 0 to 150 45 123 50 −65 to 150 240 peak 260 peak 1 1 1 3 Unit °C °C °C/W °C/W °C/W °C °C − Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Internally limited by thermal shutdown, 150°C min. 2. Rating applies when soldered to an appropriate thermal area on the PCB. 3. 60 − 180 seconds minimum above 183°C. 4. 60 − 180 seconds minimum above 237°C. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. MAXIMUM RATINGS Pin Symbol VCC BST SW DRVH DRVL IN OD PGND NOTE: Pin Name Main Supply Voltage Input Bootstrap Supply Voltage Input Switching Node (Bootstrap Supply Return) High−Side Driver Output Low−Side Driver Output DRVH and DRVL Control Input Output Disable Ground VMAX 15 V 30 V wrt/PGND 35 V v 50 ns wrt/PGND, 15 V wrt/SW 30 V BST + 0.3 V 35 V v 50 ns wrt/PGND, 15 V wrt/SW VCC + 0.3 V VCC + 0.3 V VCC + 0.3 V 0V VMIN −0.3 V −0.3 V wrt/SW −1.0 V DC −10 V< 200 ns −0.3 V wrt/SW −0.3 V DC −2.0 V < 200 ns −0.3 V −0.3 V 0V All voltages are with respect to PGND except where noted. http://onsemi.com 3 NCP3418, NCP3418A NCP3418−SPECIFICATIONS (Note 5) (VCC = 12 V, TA = 0°C to +85°C, TJ = 0°C to +125°C unless otherwise noted.). Parameter SUPPLY Supply Voltage Range Supply Current OD INPUT Input Voltage High Input Voltage Low Input Current Propagation Delay Time (Note 6) PWM INPUT Input Voltage High Input Voltage Low Input Current HIGH−SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times (Note 6) Propagation Delay (Notes 6 & 7) LOW−SIDE DRIVER Output Resistance, Sourcing Current Output Resistance, Sinking Current Transition Times Propagation Delay UNDERVOLTAGE LOCKOUT UVLO Hysteresis THERMAL SHUTDOWN Over Temperature Protection Hysteresis 5. 6. 7. 8. (Note 8) (Note 8) − 150 170 20 °C °C − (Note 8) − − 3.9 4.3 0.5 4.6 V V − − trDRVL tfDRVL tpdhDRVL tpdlDRVL VCC = 12 V (Note 8) VCC − VSW = 12 V (Note 8) CLOAD = 3.0 nF, See Figure 3 See Figure 3 − − − − − − 1.8 1.0 16 11 30 20 3.0 2.5 25 15 60 30 W W ns ns ns ns VBST − VSW = 12 V (Note 8) − VBST − VSW = 12 V (Note 8) VBST − VSW = 12 V, CLOAD = 3.0 nF, See Figure 3 VBST − VSW = 12 V − trDRVH tfDRVH tpdhDRVH tpdlDRVH − − − − − 1.0 18 10 30 25 2.5 25 15 60 45 W ns ns ns ns − 1.8 3.0 W − − − − − − 2.0 − −1.0 − − − − 0.8 +1.0 V V mA − − − See Figure 2 − − − tpdlOD tpdhOD 2.0 − −1.0 − − − − − 40 40 − 0.8 +1.0 60 60 V V mA ns ns − BST = 12 V, IN = 0 V VCC ISYS 4.6 − − 2.0 13.2 6.0 V mA Conditions Symbol Min Typ Max Unit All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). AC specifications are guaranteed by characterization, but not production tested. For propagation delays, “tpdh’’ refers to the specified signal going high; “tpdl’’ refers to it going low. GBD: Guaranteed by design; not tested in production. Specifications subject to change without notice. http://onsemi.com 4 NCP3418, NCP3418A OD tpdlOD tpdhOD 90% DRVH or DRVL 10% Figure 2. Output Disable Timing Diagram IN tpdlDRVL tfDRVL DRVL 90% 1.5 V 10% tpdhDRVH trDRVH 90% DRVH−SW 90% tfDRVH 10% tpdlDRVH trDRVL 90% 10% 10% tpdhDRVL SW 4V Figure 3. Nonoverlap Timing Diagram (timing is referenced to the 90% and 10% points unless otherwise noted) http://onsemi.com 5 NCP3418, NCP3418A APPLICATIONS INFORMATION IN IN DRVH DRVH DRVL DRVL Figure 4. DRVH Rise and DRVL Fall Times Figure 5. DRVH Fall and DRVL Rise Times 40 15 30 RISE TIME (ns) FALL TIME (ns) 10 trTG 20 trTG trBG 5 10 trBG 0 1 0 2 3 4 5 1 2 3 4 5 LOAD CAPACITANCE (nF) LOAD CAPACITANCE (nF) Figure 6. Rise Time vs. Load Capacitance Figure 7. Fall Time vs. Load Capacitance 60 50 40 30 20 10 0 0 TA = 25 °C VCC = 12 V Cload = 3.3 nF 200 400 600 800 1000 1200 SUPPLY CURRENT (mA) ICC IN FREQUENCY (kHz) Figure 8. VCC Supply Current vs. IN Frequency http://onsemi.com 6 NCP3418, NCP3418A APPLICATIONS INFORMATION Theory of Operation The NCP3418 and NCP3418A are single phase MOSFET drivers optimized for driving two N−channel MOSFETs in a synchronous buck converter topology. The NCP3418 features an internal diode, while the NCP3418A requires an external BST diode for the floating top gate driver. A single PWM input signal is all that is required to properly drive the high−side and the low−side MOSFETs. Each driver is capable of driving a 3.3 nF load at frequencies up to 500 kHz. Low−Side Driver The low−side driver is designed to drive a ground−referenced low RDS(on) N−Channel MOSFET. The voltage rail for the low−side driver is internally connected to the VCC supply and PGND. When the NCP3418 is enabled, the low−side driver’s output is 180_ out of phase with the PWM input. When the device is disabled, the low−side gate is held low. High−Side Driver threshold, DRVL will go high after a propagation delay (tpdhDRVL), turning the low−side MOSFET on. However, if SW does not fall below 4.0 V in 300 ns, the safety timer circuit will override the normal control scheme and drive DRVL high. This will help insure that if the high−side MOSFET fails to turn off it will not produce an over−voltage at the output. Similarly, to prevent cross conduction during the low−side MOSFET’s turn−off and the high−side MOSFET’s turn−on, the overlap circuit monitors the voltage at the gate of the low−side MOSFET through the DRVL pin. When the PWM signal goes high, DRVL will go low after a propagation delay (tpdlDRVL), turning the low−side MOSFET off. However, before the high−side MOSFET can turn on, the overlap protection circuit waits for the voltage at DRVL to drop below 1.5 V. Once this has occurred, DRVH will go high after a propagation delay (tpdhDRVH), turning the high−side MOSFET on. Application Information Supply Capacitor Selection The high−side driver is designed to drive a floating low RDS(on) N−channel MOSFET. The bias voltage for the high side driver is developed by a bootstrap circuit referenced to SW. The bootstrap capacitor should be connected between the BST and SW pins. The bootstrap circuit comprises an internal or external diode, D1 (in which the anode is connected to VCC), and an external bootstrap capacitor, CBST. When the NCP3418 is starting up, the SW pin is at ground, so the bootstrap capacitor will charge up to VCC through D1. When the PWM input goes high, the high−side driver will begin to turn on the high−side MOSFET by pulling charge out of CBST. As the high−side MOSFET turns on, the SW pin will rise to VIN, forcing the BST pin to VIN + VCC, which is enough gate−to−source voltage to hold the MOSFET on. To complete the cycle, the high−side MOSFET is switched off by pulling the gate down to the voltage at the SW pin. When low−side MOSFET turns on, the SW pin is held at ground. This allows the bootstrap capacitor to charge up to VCC again. The high−side driver’s output is in phase with the PWM input. When the device is disabled, the high side gate is held low. Safety Timer and Overlap Protection Circuit For the supply input (VCC) of the NCP3418, a local bypass capacitor is recommended to reduce noise and supply peak currents during operation. Use a 1.0 to 4.7 mF, low ESR capacitor. Multilayer ceramic chip (MLCC) capacitors provide the best combination of low ESR and small size. Keep the ceramic capacitor as close as possible to the VCC and PGND pins. Bootstrap Circuit The bootstrap circuit uses a charge storage capacitor (CBST) and the internal (or an external) diode. Selection of these components can be done after the high−side MOSFET has been chosen. The bootstrap capacitor must have a voltage rating that is able to withstand twice the maximum supply voltage. A minimum 50 V rating is recommended. The capacitance is determined using the following equation: CBST + QGATE DVBST (eq. 1) The overlap protection circuit prevents both the high−side MOSFET and the low−side MOSFET from being on at the same time, and minimizes the associated off times. This will reduce power losses in the switching elements. The overlap protection circuit accomplishes this by controlling the delay from turning off the high−side MOSFET to turning on the low−side MOSFET. To prevent cross conduction during the high−side MOSFET’s turn−off and the low−side MOSFET’s turn−on, the overlap circuit monitors the voltage at the SW pin. When the PWM input signal goes low, DRVH will go low after a propagation delay (tpdlDRVH), turning the high−side MOSFET off. However, before the low−side MOSFET can turn on, the overlap protection circuit waits for the voltage at the SW pin to fall below 4.0 V. Once SW falls below the 4.0 V where QGATE is the total gate charge of the high−side MOSFET, and DVBST is the voltage droop allowed on the high−side MOSFET drive. For example, a NTD60N03 has a total gate charge of about 30 nC. For an allowed droop of 300 mV, the required bootstrap capacitance is 100 nF. A good quality ceramic capacitor should be used. If an external Schottky diode will be used for bootstrap, it must be rated to withstand the maximum supply voltage plus any peak ringing voltages that may be present on SW. The average forward current can be estimated by: IF(AVG) + QGATE fMAX (eq. 2) where fMAX is the maximum switching frequency of the controller. The peak surge current rating should be checked in−circuit, since this is dependent on the source impedance of the 12 V supply and the ESR of CBST. http://onsemi.com 7 NCP3418, NCP3418A PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH −X− A 8 5 B 1 4 S 0.25 (0.010) M Y M −Y− G C −Z− H D 0.25 (0.010) M SEATING PLANE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 NCP3418, NCP3418A PACKAGE DIMENSIONS SOIC−8 EP CASE 751AC−01 ISSUE B 2X 0.10 C A−B D A 8 5 D EXPOSED PAD 5 DETAIL A F 8 E1 2X E G h 4 1 NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS (ANGLES IN DEGREES). 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 MM TOTAL IN EXCESS OF THE “b” DIMENSION AT MAXIMUM MATERIAL CONDITION. 4. DATUMS A AND B TO BE DETERMINED AT DATUM PLANE H. MILLIMETERS MIN MAX 1.35 1.75 0.00 0.10 1.35 1.65 0.31 0.51 0.28 0.48 0.17 0.25 0.17 0.23 4.90 BSC 6.00 BSC 3.90 BSC 1.27 BSC 0.40 1.27 1.04 REF 2.24 3.20 1.55 2.51 0.25 0.50 0_ 8_ 0.10 C D PIN ONE LOCATION 8X A2 GAUGE PLANE 0.10 C SEATING PLANE b1 L (L1) DETAIL A q C SIDE VIEW A1 0.25 c1 SECTION A−A SOLDERING FOOTPRINT* 2.72 0.107 1.52 0.060 7.0 0.275 2.03 0.08 4.0 0.155 0.6 1.270 SCALE 6:1 0.024 0.050 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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