NCP348GEVB

NCP348, NCP348AE Positive Overvoltage Protection Controller with Internal Low RON NMOS FET and Status FLAG The NCP348 is able to disconnect the systems from its output pin in case wrong input operating conditions are detected. The system is positive overvoltage protected up to +28 V. Due to this device using internal NMOS, no external device is necessary, reducing the system cost and the PCB area of the application board. The NCP348 is able to instantaneously disconnect the output from the input, due to integrated Low RON Power NMOS (65 mW), if the input voltage exceeds the overvoltage threshold (OVLO) or undervoltage threshold (UVLO). At powerup (EN pin = low level), the Vout turns on 50 ms after the Vin exceeds the undervoltage threshold. The NCP348 provides a negative going flag (FLAG) output, which alerts the system that a fault has occurred. In addition, the device has ESD−protected input (15 kV Air) when bypassed with a 1.0 mF or larger capacitor. Features • • • • • • • • • • • • Overvoltage Protection up to 28 V On−Chip Low RDS(on) NMOS Transistor: 65 mW Internal Charge Pump Overvoltage Lockout (OVLO) Undervoltage Lockout (UVLO) Internal 50 ms Startup Delay Alert FLAG Output Shutdown EN Input Compliance to IEC61000−4−2 (Level 4) 8.0 kV (Contact) 15 kV (Air) ESD Ratings: Machine Model = B Human Body Model = 3 10 Lead WDFN 2.5x2 mm Package This is a Pb−Free Device http://onsemi.com MARKING DIAGRAM BAxM G WDFN10 MT SUFFIX CASE 516AA BAI BAJ M G = NCP348 = NCP348AE = Date Code = Pb−Free Package PIN CONNECTIONS IN 1 GND 2 FLAG 3 IN 4 IN 5 10 EN PAD1 GND PAD2 IN 9 NC 8 NC 7 OUT 6 OUT (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. Applications • • • • • Cell Phones Camera Phones Digital Still Cameras Personal Digital Applications MP3 Players Q © Semiconductor Components Industries, LLC, 2010 May, 2010 − Rev. 6 1 Publication Order Number: NCP348/D NCP348, NCP348AE VBat VBat D3 7011X/SM NCP1835B GND 1 mF 6 7 8 9 ISEL 8 4 270 K 4.7 mF VBat 3 TIMER NCP348 1 IN OUT 4 IN OUT 5 IN NC 10 NC EN FLAG ENABLE / 2 Microprocessor Wall Adapter − AC/DC 3 EN CFLG 2 FAULT V2P8 VSNS 1 VCC BAT 1M 6 7 9 10 GND 5 ENABLE / Microprocessor V2P8 VBat 100 nF Lithium BATTERY 15 pF 0 0 Figure 1. Typical Application Circuit INPUT OUTPUT 60 mA ESD Protection Output Impedance = 200 k Core Negative Protection Gate Driver Charge Pump Delay Generator ESD Protection 200 kHz Oscillator LDO VREG Power ON 10 V EN EN Block VREG UVLO VREF VREF UVLO OVLO VREF OVLO DISABLE Figure 2. Functional Block Diagram http://onsemi.com 2 FLAG ESD Protection NCP348, NCP348AE PIN FUNCTION DESCRIPTION Pin No. Symbol Function Description 1 4 5 IN POWER Input Voltage Pin. This pin is connected to the power supply. The device system core is supplied by this input. A 1 mF low ESR ceramic capacitor, or larger, must be connected between this pin and GND. The three IN pins must be hardwired to common supply. 2 GND POWER Ground 3 FLAG OUTPUT Fault Indication Pin. This pin allows an external system to detect a fault on IN pin. The FLAG pin goes low when input voltage exceeds OVLO threshold or drop below UVLO threshold. Since the FLAG pin is open drain functionality, an external pull up resistor to VCC must be added. 6 7 OUT OUTPUT Output Voltage Pin. This pin follows IN pin when “no fault” is detected. The output is disconnected from the Vin power supply when the input voltage is under the UVLO threshold or above OVLO threshold. The two OUT pins must be hardwired to common supply. 8 NC OPEN No Connect 9 NC OPEN No Connect 10 EN INPUT Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to GND to a pull down or to a I/O pin. This pin does not have an impact on the fault detection. PAD1 PAD1, under the device. See PCB recommendations page 10. Can be shorted to GND. PAD2 The PAD2 is electrically connected to the internal NMOS drain and connected to Pins 4 and 5. See PCB recommendations page 10. MAXIMUM RATINGS Rating Symbol Value Unit Vminin −0.3 V Vmin −0.3 V Vmaxin 30 V Maximum Voltage (All others to GND) Vmax 7.0 V Maximum Current (UVLO OVLO to FLAG < = 0.4 V (See Figures 4 & 10) Vin increasing from 5.0 V to 8.0 V at 3.0 V/ms, Rload connected on Vout − 1.0 − ms tdis From EN > = 1.2 V to Vout < 0.3 V Rload = 5.0 W (See Figures 5 & 12) − 1.0 5.0 ms EN Leakage Current TIMINGS Startup Delay Alert Delay Disable Time NOTE: Electrical parameters are guaranteed by correlation across the full range of temperature. 4. Additional UVLO and OVLO thresholds ranging from UVLO and from OVLO can be manufactured. Contact your ON Semiconductor representative for availability. http://onsemi.com 4 NCP348, NCP348AE TIMING DIAGRAMS OVLO 0 < VIN < UVLO And/Or VOLTAGE DETECTION /EN = 1 Figure 16. Simplified Diagram CONDITIONS IN OUT /EN = 0 & UVLO < VIN < OVLO VOLTAGE DETECTION Figure 17. Simplified Diagram Operation overtaking undervoltage UVLO (Figure 3). The NCP348 provides a FLAG output, which alerts the system that a fault has occurred. A 50 ms additional delay, regarding available output (Figure 3) is added between output signal rising up and to FLAG signal rising up. FLAG pin is an open drain output. The NCP348 provides overvoltage protection for positive voltage, up to 28 V. A Low RDS(on) NMOS FET protects the systems (i.e.: charger) connected on the Vout pin, against positive overvoltage. At powerup, with EN pin = low, the output is rising up 50 ms after the input http://onsemi.com 8 NCP348, NCP348AE Vout = 0 FLAG = Low Reset Timer Vin < UVLO or Vin > OVLO Vout = 0 FLAG = Low Timer Count OVLO > Vin > UVLO T < 50 ms Timer Check T = 50 ms Reset Timer Vin < UVLO or Vin > OVLO Check Vin FLAG = Low Timer Count UVLO < Vin < OVLO EN = 1 EN = 0 Check EN Vout = Open Vin < UVLO or Vin > OVLO Vout = Vin T < 50 ms Timer Check T = 50 ms Check EN UVLO < Vin < OVLO EN = 1 Vout = Open FLAG = High Check Vin UVLO < Vin < OVLO EN = 0 Vout = Vin FLAG = High Check Vin Vin < UVLO or Vin > OVLO Figure 18. State Machine http://onsemi.com 9 NCP348, NCP348AE Undervoltage Lockout (UVLO) As example: Rload = 8.0 W, Vin = 5.0 V Typical RDS(on) = 65 mW, Iout = 618 mA To ensure proper operation under any conditions, the device has a built−in undervoltage lockout (UVLO) circuit. During Vin positive going slope, the output remains disconnected from input until Vin voltage is below 3.25 V (NCP348MTT version), plus hysteresis, nominal. The FLAG output is tied to low as long as Vin does not reach UVLO threshold. This circuit has a 50 mV hysteresis to provide noise immunity to transient condition. Additional UVLO thresholds ranging from UVLO can be manufactured. (See Selection Guide on page 12) Contact your ON Semiconductor representative for availability. Vout = 8 x 0.618 = 4.95 V NMOS losses = RDS(on) x Iout2 = 0.065 x 0.6182 = 25 mW ESD Tests The NCP348 input pin fully supports the IEC61000−4−2. 1.0 mF (minimum) must be connected between Vin and GND, close to the device. That means, in Air condition, Vin has a "15 kV ESD protected input. In Contact condition, Vin has "8.0 kV ESD protected input. Please refer to Figure 19 to see the IEC 61000−4−2 electrostatic discharge waveform. Overvoltage Lockout (OVLO) To protect connected systems on Vout pin from overvoltage, the device has a built−in overvoltage lockout (OVLO) circuit. During overvoltage condition, the output remains disabled as long as the input voltage exceeds 6.4 V typical (NCP348MTT version). Additional OVLO thresholds ranging from OVLO can be manufactured. (See Selection Guide on page 12) Contact your ON Semiconductor representative for availability. FLAG output is tied to low until Vin is higher than OVLO. This circuit has a 100 mV hysteresis to provide noise immunity to transient conditions. FLAG Output The NCP348 provides a FLAG output, which alerts external systems that a fault has occurred. This pin is tied to low as soon the OVLO threshold is exceeded or when the Vin level is below the UVLO threshold. When Vin level recovers normal condition, FLAG is held high, keeping in mind that an additional 50 ms delay has been added between available output and FLAG = high. The pin is an open drain output, thus a pull up resistor (typically 1 MW, minimum 10 kW) must be added to Vbat. Minimum Vbat supply must be 2.5 V. The FLAG level will always reflects Vin status, even if the device is turned off (EN = 1). Figure 19. Electrostatic Discharge Waveform PCB Recommendations The NCP348 integrates a 2 amperes rated NMOS FET, and the PCB rules must be respected to properly evacuate the heat out of the silicon. The PAD1 is internally isolated from the active silicon and should preferably be connected to ground. The PAD2 of the NCP348 package is connected to the internal NMOS drain and can be used to increase the heat transfer if necessary from an applications standpoint. Depending upon the power dissipated in the application, one can either use the PCB tracks connected to Pins 4 and 5 to evacuate heat, or make profit of the PAD2 area to add extra copper surface to reduce the junction temperature (See Figure 20). Of course, in any case, this pad shall be not connected to any other potential. Figure 20 shows copper area according to RqJA and allows the design of the heat transfer plane connected to PAD2. EN Input To enable normal operation, the EN pin shall be forced to low or connected to ground. A high level on the pin, disconnects OUT pin from IN pin. EN does not overdrive an OVLO or UVLO fault. Internal NMOS FET The NCP348 includes an internal Low RDS(on) NMOS FET to protect the systems, connected on OUT pin, from positive overvoltage. Regarding electrical characteristics, the RDS(on), during normal operation, will create low losses on Vout pin. http://onsemi.com 10 NCP348, NCP348AE 310 290 1 oz C.F. 270 1 oz Sim 2 oz C.F. qJA (°C/W) 250 2 oz Sim 230 1 210 190 2 175 150 0 25 50 75 100 125 150 175 200 225 250 275 300 325350 COPPER HEAT SPREADING AREA (mm2) Figure 21. Demo Board Layout Figure 20. INPUT 1 mF 25 V X5R 0603 Murata GRM188R61E105KA12D OUTPUT C1 1 IN 4 IN 5 IN 10 EN_Power EN EN 6 OUT 7 OUT NCP348 8 NC 9 NC GND 2 FLAG 3 C2 100 nF 50 V X7R 0805 not necessary FLAG Power FLAG R1 1M EN_State R2 100 k 3 2 1 R3 2 1 100 k J2 1 GND FLAG_State Figure 22. Demo Board Schematic http://onsemi.com 11 F1 F2 F3 F4 2 NCP348, NCP348AE ORDERING INFORMATION Package Shipping† NCP348MTTBG WDFN−10 (Pb−Free) 3000 / Tape & Reel NCP348MTTXG WDFN−10 (Pb−Free) 10000 / Tape & Reel NCP348AEMTTBG WDFN−10 (Pb−Free) 3000 / Tape & Reel NCP348AEMTTXG WDFN−10 (Pb−Free) 10000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. SELECTION GUIDE The NCP348 can be available in several undervoltage and overvoltage thresholds versions. Part number is designated as follows: NCP348xxMTTxG ab c Code Contents a UVLO Typical Threshold a: − = 3.25 V a: A = 3.25 V b OVLO Typical Threshold b: − = 6.4 V b: E = 6.02 V c Tape & Reel Type c: B = 3000 c: X = 10000 http://onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS LLGA10 2.5x2.5, 0.5P CASE 513AG-01 ISSUE A DATE 15 MAY 2007 1 SCALE 4:1 A D PIN ONE REFERENCE 2X 0.10 C 2X ÎÎÎ ÎÎÎ ÎÎÎ 0.10 C E DIM A A1 b D D2 E E2 e G K L L1 L3 TOP VIEW A 0.05 C 11X NOTE 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PADS AS WELL AS THE TERMINALS. B 0.05 C SIDE VIEW A1 C SEATING PLANE (0.10) G 2X L1 1 GENERIC MARKING DIAGRAM* D2 e (0.10) 10X 5 L 1 PIN ONE DETAIL XXXX ALYW G E2 10X K 10 L3 0.10 C A B 6 10X b 0.05 C NOTE 3 BOTTOM VIEW SOLDERING FOOTPRINT* 0.25 9X MILLIMETERS MIN MAX 0.50 0.60 0.00 0.05 0.20 0.30 2.50 BSC 0.90 1.00 2.50 BSC 1.45 1.55 0.50 BSC 0.20 0.30 0.20 --0.30 REF 0.05 BSC 0.20 0.30 0.95 XXXX AL Y W G = Specific Device Code = Assembly Location = Year = Work Week = Pb-Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, “G” or microdot “ G”, may or may not be present. 0.30 1.50 2.90 1 0.40 10X 0.52 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: 98AON24198D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped “CONTROLLED COPY” in red. NEW STANDARD: © Semiconductor Components Industries, LLC, 2002 Case Outline Number: http://onsemi.com 10 PIN LLGA, 2.5X2.5, 0.5P October, DESCRIPTION: 2002 - Rev. 0 PAGE 1 OFXXX 2 1 DOCUMENT NUMBER: 98AON24198D PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION. REQ. BY W. CLEMENS. 09 MAR 2007 A ADDED DEVICE MARKING INFORMATION. REQ. BY W. CLEMENS. 15 MAY 2007 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. © Semiconductor Components Industries, LLC, 2007 May, 2007 - Rev. 01A Case Outline Number: 513AG MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WDFN10 2.5x2, 0.5P CASE 516AA−01 ISSUE C DATE 06 FEB 2007 SCALE 4:1 D PIN ONE REFERENCE 0.10 C 2X 2X A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. B ÍÍÍ ÍÍÍ ÍÍÍ E DIM A A1 A3 b D D2 D3 e E E2 G G1 K L 0.10 C A3 0.10 C A 10X 0.08 C A1 C 0.10 C A D2 L 1 XXX M G E2 8X 0.10 C A 10 e B G 10X 0.10 C A 0.05 C 0.05 C 1.18 0.78 1.00 --0.40 = Specific Device Code = Date Code = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 6 b 0.30 XXXM G K 5 MAX 0.80 0.05 GENERIC MARKING DIAGRAM* B G1 D3 0.05 C 10X SEATING PLANE MILLIMETERS MIN NOM 0.70 0.75 0.00 --0.20 REF 0.20 0.25 2.50 BSC 0.97 1.08 0.57 0.68 0.50 BSC 2.00 BSC 0.80 0.90 0.375 BSC 0.35 BSC 0.20 --0.20 0.30 B NOTE 3 SOLDERING FOOTPRINT* 2.50 0.95 1.13 10X 0.58 10X 0.30 0.50 PITCH 0.05 0.73 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON21397D WDFN10 2.5X2, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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