NCP360GEVB

NCP360, NCV360 USB Positive Overvoltage Protection Controller with Internal PMOS FET and Status FLAG The NCP360 disconnects systems at its output when wrong VBUS operating conditions are detected at its input. The system is positive overvoltage protected up to +20 V. Thanks to an integrated PMOS FET, no external device is necessary, reducing the system cost and the PCB area of the application board. The NCP360 is able to instantaneously disconnect the output from the input if the input voltage exceeds the overvoltage threshold (OVLO). The NCP360 provides a negative going flag (FLAG) output, which alerts the system that a fault has occurred. In addition, the device has ESD−protected input (15 kV Air) when bypassed with a 1 mF or larger capacitor. Features • • • • • • • • • • • • • Very Fast Protection, Up to 20 V, with 25 mA Current Consumption On−chip PMOS Transistor Overvoltage Lockout (OVLO) Undervoltage Lockout (UVLO) Alert FLAG Output EN Enable Pin Thermal Shutdown Compliance to IEC61000−4−2 (Level 4) 8 kV (Contact) 15 kV (Air) ESD Ratings: Machine Model = B ESD Ratings: Human Body Model = 2 6 Lead UDFN 2x2 mm Package 5 Lead TSOP 3x3 mm Package NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These are Pb−Free Devices http://onsemi.com MARKING DIAGRAMS UDFN6 MU SUFFIX CASE 517AB 1 xx M G M = Date Code G = Pb−Free Package TSOP−5 SN SUFFIX CASE 483 5 1 A Y W G xxxAYWG G 1 = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 11 of this data sheet. Applications • • • • • USB Devices Mobile Phones Peripheral Personal Digital Applications MP3 Players Q © Semiconductor Components Industries, LLC, 2012 March, 2012 − Rev. 10 1 Publication Order Number: NCP360/D NCP360, NCV360 PIN CONNECTIONS EN 1 GND 2 IN 1 5 OUT GND 2 4 OUT EN 3 6 FLAG PAD1 IN 3 5 OUT 4 FLAG TSOP−5 UDFN6 (Top Views) PIN FUNCTION DESCRIPTION (UDFN6 Package) Pin No. Name Type Description 1 EN INPUT 2 GND POWER Ground 3 IN POWER Input Voltage Pin. This pin is connected to the VBUS. A 1 mF low ESR ceramic capacitor, or larger, must be connected between this pin and GND. 4, 5 OUT OUTPUT Output Voltage Pin. The output is disconnected from the VBUS power supply when the input voltage is above OVLO threshold or below UVLO threshold. A 1 mF capacitor must be connected to these pins. The two OUT pins must be hardwired to common supply. 6 FLAG OUTPUT Fault Indication Pin. This pin allows an external system to detect a fault on VBUS pin. The FLAG pin goes low when input voltage exceeds OVLO threshold. Since the FLAG pin is open drain functionality, an external pull up resistor to VCC must be added. − PAD1 POWER Exposed Pad. Can be connected to GND or isolated plane. Must be used to thermal dissipation. Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to GND or to a I/O pin. This pin does not have an impact on the fault detection. PIN FUNCTION DESCRIPTION (TSOP−5 Package) Pin No. Name Type Description 1 IN POWER Input Voltage Pin. This pin is connected to the VBUS. A 1 mF low ESR ceramic capacitor, or larger, must be connected between this pin and GND. 2 GND POWER Ground 3 EN INPUT 4 FLAG OUTPUT Fault Indication Pin. This pin allows an external system to detect a fault on VBUS pin. The FLAG pin goes low when input voltage exceeds OVLO threshold. Since the FLAG pin is open drain functionality, an external pull up resistor to VCC must be added. 5 OUT OUTPUT Output Voltage Pin. The output is disconnected from the VBUS power supply when the input voltage is above OVLO threshold or below UVLO threshold. A 1 mF capacitor must be connected to this pin. Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to GND or to a I/O pin. This pin does not have an impact on the fault detection. http://onsemi.com 2 NCP360, NCV360 INPUT OUTPUT 3 1 mF 25 V X5R 0603 C1 4 OUT 5 OUT IN C2 NCP360 1 EN FLAG GND FLAG Power 1 mF 25 V X5R 0603 6 FLAG 2 R1 1M J2 2 1 FLAG_State Figure 1. Typical Application Circuit (UDFN Pinout) OUTPUT INPUT (2 out pins in UDFN package) Thermal Shutdown Soft Start EN LDO UVLO OVLO VREF Figure 2. Functional Block Diagram http://onsemi.com 3 FLAGV NCP360, NCV360 MAXIMUM RATINGS Rating Symbol Value Unit Vminin −0.3 V Vmin −0.3 V Vmaxin 21 V Maximum Voltage (All others to GND) Vmax 7.0 V Maximum Current from Vin to Vout (PMOS) (Note 1) Imax 600 mA RqJA 305 260 °C/W Operating Ambient Temperature Range TA −40 to +85 °C Storage Temperature Range Tstg −65 to +150 °C Junction Operating Temperature TJ 150 °C ESD Withstand Voltage (IEC 61000−4−2) Human Body Model (HBM), Model = 2 (Note 3) Machine Model (MM) Model = B (Note 4) Vesd 15 Air, 8.0 Contact 2000 200 kV V V Moisture Sensitivity MSL Level 1 − Minimum Voltage (IN to GND) Minimum Voltage (All others to GND) Maximum Voltage (IN to GND) Thermal Resistance, Junction−to−Air (Note 2) TSOP−5 UDFN Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. With minimum PCB area. By decreasing RqJA, the current capability increases. See PCB recommendation page 9. 2. RqJA is highly dependent on the PCB heat sink area (connected to PAD1, UDFN). See PCB Recommendations. 3. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114. 4. Machine Model, 200 pF discharged through all pins following specification JESD22/A115. 5. Compliant with JEDEC Latch−up Test, up to maximum voltage range. http://onsemi.com 4 NCP360, NCV360 ELECTRICAL CHARACTERISTICS (Min/Max limits values (−40°C < TA < +85°C) and Vin = +5.0 V. Typical values are TA = +25°C, unless otherwise noted.) Characteristic Input Voltage Range Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis Symbol UVLO Overvoltage Lockout Hysteresis OVLOhyst OVLO Supply Current Vdrop Idd Iddovlo Output Off State Current Istd FLAG Output Low Voltage Volflag FLAG Leakage Current FLAGleak Typ 1.2 Vin falls below UVLO threshold Max Unit 20 V 2.85 3.0 3.15 V 50 30 70 50 90 70 mV 5.43 6.0 6.75 7.0 5.675 6.25 7.07 7.2 5.9 6.5 7.4 7.4 V 50 100 125 mV Vin = 5 V, I charge = 500 mA 105 200 mV No Load, Vin = 5.25 V 24 35 mA 50 50 85 85 mA 26 37 mA 400 mV UVLOhyst OVLO Supply Quiescent Current Min Vin Overvoltage Lockout Threshold Vin versus Vout Dopout Conditions MU/SN, SNAE SNAF, SNAI Vin rises above OVLO threshold Vin = 7 V Vin = 8 V MU/SN SNAE SNAF SNAI MU/SN, SNAE SNAF, SNAI Vin = 5.25 V, EN = 1.2 V Vin > OVLO, Sink 1 mA on FLAG pin FLAG level = 5 V EN Voltage High Vih Vin from 3.3 V to 5.25 V EN Voltage Low Vil Vin from 3.3 V to 5.25 V EN Leakage Current ENleak 5.0 nA 1.2 V 0.4 V EN = 5.5 V or GND 170 nA ton From Vin: (0 to (OVLO − 300 mV) < Vin < OVLO) to Vout = 0.8xVin, Rise time UVLO to FLAG = 1.2 V, See Fig 3 & 10 3.0 toff From Vin > OVLO to Vout ≤ 0.3 V, See Fig 4 & 11 Vin increasing from normal operation to >OVLO at 1V/ms. No output capacitor. 0.8 1.5 ms Alert Delay tstop From Vin > OVLO to FLAG ≤ 0.4 V, See Fig 4 & 12 Vin increasing from normal operation to >OVLO at 1V/ms 1.0 2.0 ms Disable Time tdis From EN 0.4 to 1.2V to Vout ≤ 0.3V, See Fig 5 & 13 Vin = 4.75 V. No output capacitor. 2.0 ms Thermal Shutdown Temperature Tsd 150 °C Tsdhyst 30 °C TIMINGS Start Up Delay FLAG going up Delay Output Turn Off Time Thermal Shutdown Hysteresis NOTE: Thermal Shutdown parameter has been fully characterized and guaranteed by design. http://onsemi.com 5 15 ms ms NCP360, NCV360 Vin > 1.2V OVLO or VIN < UVLO Voltage Detection Figure 7. CONDITIONS IN OUT Voltage Detection Figure 8. http://onsemi.com 6 UVLO < VIN < OVLO NCP360, NCV360 TYPICAL OPERATING CHARACTERISTICS Figure 10. FLAG Going Up Delay Vin = Ch1, FLAG = Ch3 Figure 9. Startup Vin = Ch1, Vout = Ch3 Figure 12. Alert Delay Vout = Ch1, FLAG = Ch3 Figure 11. Output Turn Off Time Vin = Ch1, Vout = Ch2 Figure 14. Thermal Shutdown Vin = Ch1, Vout = Ch2, FLAG = Ch3 Figure 13. Disable Time EN = Ch1, Vout = Ch2, FLAG = Ch3 http://onsemi.com 7 NCP360, NCV360 TYPICAL OPERATING CHARACTERISTICS 450 400 Vin = 3.6 V RDS(on) (mW) 350 300 250 Vin = 5 V 200 150 100 50 0 −50 0 50 100 TEMPERATURE (°C) IQ, SUPPLY QUIESCENT CURRENT (mA) Figure 15. Direct Output Short Circuit Figure 16. RDS(on) vs. Temperature (Load = 500 mA) 180 160 140 120 100 80 125°C 25°C 60 40 −40°C 20 0 1 3 5 7 9 11 13 15 17 19 Vin, INPUT VOLTAGE (V) Figure 17. Supply Quiescent Current vs. Vin http://onsemi.com 8 21 150 NCP360, NCV360 In Operation Internal PMOS FET NCP360 provides overvoltage protection for positive voltage, up to 20 V. A PMOS FET protects the systems (i.e.: VBUS) connected on the Vout pin, against positive over−voltage. The Output follows the VBUS level until OVLO threshold is overtaken. NCP360 includes an internal PMOS FET to protect the systems, connected on OUT pin, from positive overvoltage. Regarding electrical characteristics, the RDSon, during normal operation, will create low losses on Vout pin, characterized by Vin versus Vout dropout. (See Figure 16). Undervoltage Lockout (UVLO) To ensure proper operation under any conditions, the device has a built−in undervoltage lock out (UVLO) circuit. During Vin positive going slope, the output remains disconnected from input until Vin voltage is above 3.2 V nominal. The FLAGV output is pulled to low as long as Vin does not reach UVLO threshold. This circuit has a UVLO hysteresis to provide noise immunity to transient condition. ESD Tests NCP360 fully support the IEC61000−4−2, level 4 (Input pin, 1 mF mounted on board). That means, in Air condition, Vin has a ±15 kV ESD protected input. In Contact condition, Vin has ±8 kV ESD protected input. Please refer to Fig 19 to see the IEC 61000−4−2 electrostatic discharge waveform. Vin (V) 20 V OVLO UVLO 0 Vout OVLO UVLO 0 Figure 18. Output Characteristic vs. Vin Overvoltage Lockout (OVLO) To protect connected systems on Vout pin from overvoltage, the device has a built−in overvoltage lock out (OVLO) circuit. During overvoltage condition, the output remains disabled until the input voltage exceeds OVLO − Hysteresis. FLAG output is tied to low until Vin is higher than OVLO. This circuit has a OVLO hysteresis to provide noise immunity to transient conditions. Figure 19. PCB Recommendations The NCP360 integrates a 500 mA rated PMOS FET, and the PCB rules must be respected to properly evacuate the heat out of the silicon. The UDFN PAD1 must be connected to ground plane to increase the heat transfer if necessary from an application standpoint. Of course, in any case, this pad shall be not connected to any other potential. By increasing PCB area, the RqJA of the package can be decreased, allowing higher charge current to fill the battery. Taking into account that internal bondings (wires between package and silicon) can handle up to 1 A (higher than thermal capability), the following calculation shows two different example of current capability, depending on PCB area: • With 305°C/W (without PCB area), allowing DC current is 500 mA • With 260°C/W (200 mm2), the charge DC current allows with a 85°C ambient temperature is: I = √(TJ-TA)/(RqJA x RDSON) I = 625 mA FLAG Output NCP360 provides a FLAG output, which alerts external systems that a fault has occurred. This pin is tied to low as soon the OVLO threshold is exceeded When Vin level recovers normal condition, FLAG is held high. The pin is an open drain output, thus a pull up resistor (typically 1 MW− Minimum 10 kW) must be provided to Vbattery. FLAG pin is an open drain output. EN Input To enable normal operation, the EN pin shall be forced to low or connected to ground. A high level on the pin disconnects OUT pin from IN pin. EN does not overdrive an OVLO or UVLO fault. http://onsemi.com 9 NCP360, NCV360 In every case, we recommend to make thermal measurement on final application board to make sure of the final Thermal Resistance. 380 50% 45% TSOP−5 1.0 oz TSOP−5 2.0 oz DFN 2x2.2 1.0 oz DFN 2x2.2 2.0 oz % Delta DFN vs TSOP−5 Theta JA (C/W) 280 230 40% 35% 30% 25% 20% 180 15% % Delta DFN vs TSOP−5 330 10% 130 5% 80 0 100 200 300 400 500 600 0% 700 Copper heat spreader area (mm^2) Figure 20. Thermal Resistance of UDFN 2x2 and TSOP Packages as a Function of PCB Area and Thickness http://onsemi.com 10 NCP360, NCV360 ORDERING INFORMATION Marking Package Shipping† NCP360MUTBG ZD UDFN6 (Pb−Free) 3000 / Tape & Reel NCP360MUTXG ZD UDFN6 (Pb−Free) 10000 / Tape & Reel NCP360SNT1G SYA TSOP−5 (Pb−Free) 3000 / Tape & Reel NCP360SNAET1G AAP TSOP−5 (Pb−Free) 3000 / Tape & Reel NCP360SNAFT1G AA5 TSOP−5 (Pb−Free) 3000 / Tape & Reel NCP360SNAIT1G ACE TSOP−5 (Pb−Free) 3000 / Tape & Reel NCV360SNT1G* VUE TSOP−5 (Pb−Free) 3000 / Tape & Reel NCV360SNAET1G* VEY TSOP−5 (Pb−Free) 3000 / Tape & Reel NCV360SNAFT1G* VUM TSOP−5 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements SELECTION GUIDE The NCP360 can be available in several undervoltage and overvoltage thresholds versions. Part number is designated as follows: NCP360xxxxTxG a bc d Code Contents a Package MU = UDFN SN = TSOP5 b UVLO Typical Threshold b: − = 3.0 V b: A = 3.0 V c OVLO Typical Threshold c: − = 5.675 V c: E = 6.25 V c: F = 7.07 V c: I = 7.2 V d Tape & Reel Type (parts per reel) d: 1 = 3000 d: B = 3000 d: X = 10000 http://onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−5 CASE 483 ISSUE N 5 1 SCALE 2:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSION A. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. D 5X NOTE 5 2X DATE 12 AUG 2020 0.20 C A B 0.10 T M 2X 0.20 T 5 B 1 4 2 B S 3 K DETAIL Z G A A TOP VIEW DIM A B C D G H J K M S DETAIL Z J C 0.05 H C SIDE VIEW SEATING PLANE END VIEW GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 0.95 0.037 MILLIMETERS MIN MAX 2.85 3.15 1.35 1.65 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 0_ 10 _ 2.50 3.00 1.9 0.074 5 5 XXXAYWG G 1 1 Analog 2.4 0.094 XXX = Specific Device Code A = Assembly Location Y = Year W = Work Week G = Pb−Free Package 1.0 0.039 XXX MG G Discrete/Logic XXX = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) 0.7 0.028 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ARB18753C TSOP−5 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS UDFN6 2x2, 0.65P CASE 517AB ISSUE C DATE 10 APR 2013 SCALE 4:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. TIE BARS MAY BE VISIBLE IN THIS VIEW AND ARE CONNECTED TO THE THERMAL PAD. A B D NOTE 5 PIN ONE REFERENCE 0.10 C 0.10 C ÍÍ ÍÍ ÍÍ E END VIEW TOP VIEW ÉÉÉ ÉÉÉ ÇÇÇ A3 DETAIL B 0.10 C EXPOSED Cu A 6X 0.08 C A1 NOTE 4 C SIDE VIEW DETAIL A D2 1 SEATING PLANE L 3 4 6X L DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS b e BOTTOM VIEW 0.10 M C A B 0.05 M C A1 GENERIC MARKING DIAGRAM* ALTERNATE CONSTRUCTIONS L1 6 A3 DETAIL B L E2 ÉÉ ÉÉ ÇÇ MOLD CMPD MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.127 REF 0.25 0.35 2.00 BSC 1.50 1.70 2.00 BSC 0.80 1.00 0.65 BSC 0.25 0.35 --0.15 DIM A A1 A3 b D D2 E E2 e L L1 XXMG G XX = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. RECOMMENDED SOLDERING FOOTPRINT* PACKAGE OUTLINE 1.70 6X 0.47 2.30 0.95 1 0.65 PITCH 6X 0.40 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON22162D UDFN6 2X2, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com ◊ TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative