NCP367DPMUECTBG

NCP367 Battery Charge Front-End Protection, USB and AC/DC Supply Compliant NCP367 is a charge path protection device which allows disconnecting the systems from its output pin in case wrong charging conditions are detected. The system is positive overvoltage protected up to +30 V. Thanks to a very low current consumption, the USB charge is compatible with this integrated component. This device uses internal PMOS FET, making external devices unnecessary, which reduces the system cost and PCB area of the application board. First, NCP367 is able to instantaneously disconnect the output from the input if the input voltage exceeds the overvoltage threshold. Additional overcurrent protection function allows turning off internal PMOS FET when the charge current exceeds current limit, which is externally selectable. The current limit value can be modified with control logic pin to divide it by internal gain, allowing USB 100 mA/500 mA charging or USB/Wall adapter charging up to overcurrent threshold. At the same time, Li ion Battery voltage is continuously monitored, providing more safety during the charge. Thermal shutdown protection is also available. NCP367 provides a negative going flag (FLAG) output, which alerts the system that a fault has occurred as overvoltage (power supply or battery voltage), overcurrent or thermal event. In addition, the device has ESD−protected input (15 kV Air) when bypassed with a 1 mF or larger capacitor. • • • 8 1 DFN8 MU SUFFIX CASE 506BP MARKING DIAGRAM 1 XX MG G XX = Specific Device Code M = Date Code G = Pb−Free Device (Note: Microdot may be in either location) PIN ASSIGNMENT IN Features • • • • • • • • • • • • www.onsemi.com 1 8 GND 7 FLAG VBAT 2 Overvoltage Protection Up to + 30 V OUT Fast Turn Off Time NC 3 6 GS Very Low Current Consumption/USB Compliant 5 EN ILIM 4 Li ion Battery Voltage Monitoring (Top View) Overvoltage Lockout (OVLO) Undervoltage Lockout (UVLO) Overcurrent Protection Externally Adjustable (OCP) up to 2.8 A ORDERING INFORMATION See detailed ordering, marking and shipping information in the Thermal Shutdown package dimensions section on page 12 of this data sheet. Shutdown EN and Gain Input Pins Soft−Start to Eliminate Inrush Current Typical Application Alert FLAG Output • USB Devices Compliance to IEC61000−4−2 (Level 4) • Mobile Phones 8 kV (Contact), 15 kV (Air) • Peripheral ESD Ratings: Machine Model = B ESD Ratings: Human Body Model = 2 • Personal Digital Applications 8 Lead DFN 2.2x2 mm Package • MP3 Players These are Pb−Free Devices QFN−16 © Semiconductor Components Industries, LLC, 2015 February, 2015 − Rev. 11 1 Publication Order Number: NCP367/D NCP367 NCP367 1 5 6 Wall Adapter / USB 1 mF B+ 9 OUT 7 FLAG 2 GS VBAT 4 GND ILIM 8 IN EN Battery Charger 1 mF 10 k 100 k Li+ BATTERY DCDC MCU Figure 1. Typical Application Circuit VIN/VUSB OUT ILIM Soft−Start I limit + GAIN 1/2.75 GS VBAT 4.35 V LDO Driver VREF OVLO UVLO Logic + Timer Thermal Shutdown FLAG GND EN Pin Figure 2. Functional Block Diagram www.onsemi.com 2 NCP367 PIN FUNCTION DESCRIPTION Pin Name Type Description 1 IN POWER Input Voltage Pin. This pin is connected to the power supply: Wall Adapter or USB. A 1 mF low ESR ceramic capacitor, or larger, must be connected between this pin and GND. 2 VBAT INPUT Li ion Battery voltage sense pin. A serial resistor must be placed between this pin and positive pin of the battery pack. 3 NC OUTPUT Not Connected 4 ILIM OUTPUT Current Limit Pin. This pin provides the reference, based on the internal band−gap voltage reference, to limit the overcurrent, across internal PMOSFET, from IN to OUT. A 1% tolerance, or better, resistor shall be used to get the highest accuracy of the Overcurrent Limit. 5 EN INPUT Enable Mode Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the output is disconnected from the input. The state of this pin does not have an impact on the fault detection of the FLAG pin. 6 GS INPUT Gain Select Pin. When the GS pin is tied to 0 level, the Overcurrent threshold is defined by Ilimit setting. See logic table. When GS pin is tied to high, the Overcurrent threshold is set to Ilimit/GS 7 FLAG OUTPUT Fault Indication Pin. This pin allows an external system to detect fault condition. The FLAG pin goes low when input voltage is below UVLO threshold, exceeds OVLO threshold, charge current from wall adapter to battery exceeds programmed current limit, Li ion Battery voltage (4.3 V) is exceeded or internal temperature exceeds thermal shutdown limit. Since the FLAG pin is open drain functionality, an external pull−up resistor to VBattery must be added (10 kW minimum value). 8 GND POWER Ground. 9 OUT OUTPUT Output Voltage Pin. This pin follows IN pin when “no input fault” is detected. The output is disconnected from the Vin power supply when voltage, current or thermal fault events are detected. A 1 mF low ESR ceramic capacitor, or larger, must be connected between this pin and GND. ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ NOTE: Pin out provided for concept purpose only and might change in the final product MAXIMUM RATINGS Rating Symbol Value Unit Vminin −0.3 V Vmin −0.3 V Vmaxin 30 V Maximum Voltage (All others to GND) Vmax 7.0 V Maximum DC Current from Vin to Vout (PMOS) Imax 3.4 A Thermal Resistance, Junction−to−Air (without PCB area) RqJA 190 °C/W Operating Ambient Temperature Range TA −40 to +85 °C Storage Temperature Range Tstg −65 to +150 °C Junction Operating Temperature TJ 150 °C Vesd 15 Air, 8.0 Contact 2000 200 kV V V LU Class 1 − MSL Level 1 − Minimum Voltage (IN to GND) Minimum Voltage (All others to GND) Maximum Voltage (IN to GND) ESD Withstand Voltage (IEC 61000−4−2) Human Body Model (HBM), Model = 2 (Note 1) Machine Model (MM) Model = B (Note 2) Latchup Moisture Sensitivity Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114. 2. Machine Model, 200 pF discharged through all pins following specification JESD22/A115. www.onsemi.com 3 NCP367 ELECTRICAL CHARACTERISTICS − NCP367OPMUEA (Min/Max limits values (−40°C < TA < +85°C) and Vin = +3.5 V. Typical values are TA = +25°C, unless otherwise noted.) Characteristic Input Voltage Range Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis Symbol Conditions Vin UVLO Min 1.2 Vin falls down UVLO threshold 1.75 UVLOhyst Overvoltage Lockout Threshold NCP367OPMUEA OVLO Overvoltage Lockout Hysteresis OVLOhyst Typ Max Unit 28 V 1.85 1.9 V 60 100 mV 3.8 3.95 45 150 mV Vin rises up OVLO threshold V 3.65 Vin versus Vout Resistance RDS(on) Enable Mode, Load Connected to Vout 50 100 mW Supply Quiescent Current Idd No Load 42 130 mA Disable Mode Idddis EN = 1.2 V 35 110 mA Overcurrent Threshold NCP367OPMUEA IOCP EN = low, Load Connected to Vout,, Rilim = 0 W, 1 A/ms, GS = 0.4 V 2.85 3.40 Overcurrent Response A 2.30 Ireg 1 A/ms, GS = low, Ilim = 1.51 A Current Limit Gain NCP367OPMUEA GSvalue GS = 1.2 V Battery Overvoltage Threshold OVBAT 0°C to 85°C 4.3 4.35 4.4 V OVHYS 0°C to 85°C 100 150 200 mV 20 nA 4.0 ms 400 mV Battery Overvoltage Hysteresis VBATLEAK VBAT Deglitch Time VBATDEG VBAT > OVBAT Volflag Vin > OVLO Sink 1 mA on FLAG pin FLAGleak FLAG level = 5 V FLAG Leakage Current EN Voltage High Vih EN Voltage Low Vil EN Leakage Current ENleak GS Voltage High GS Voltage Low GS Leakage Current % 2.55 VBAT Pin Leakage FLAG Output Low Voltage 5.0 0.2 2.0 10 nA 1.2 V 0.4 200 Vih 1.2 V Vil 0.4 GSleak V nA 200 V nA TIMINGS Start Up Delay ton From Vin > UVLO to Vout = 0.8xVin 15 30 45 ms tstart From Vout > 0.2xVin to FLAG = 1.2 V 15 30 45 ms tREARM OCP Active 15 30 45 ms tREG OCP Active 1.2 1.8 3.0 ms toff From Vin > OVLO to Vout ≤ 0.3 V, Vin increasing from 3.5 V to 6.5 V at 3 V/ms. 1.5 5.0 ms Alert Delay tstop From Vin > OVLO to FLAG ≤ 0.4 V, (see Figure 16) Vin increasing from 3.5 V to 6.5 V at 3 V/ms 1.5 ms Disable Time tdis From EN 0.4 to 1.2 V to Vout ≤ 0.3 V 3.0 ms Tsd 150 °C Tsdhyst 30 °C FLAG going up Delay Rearming Delay Overcurrent Regulation Time Output Turn Off Time Thermal Shutdown Temperature Thermal Shutdown Hysteresis NOTE: Electrical parameters are guaranteed by correlation across the full range of temperature. www.onsemi.com 4 NCP367 ELECTRICAL CHARACTERISTICS − NCP367DPMUEB (Min/Max limits values (−40°C < TA < +85°C) and Vin = +4.0 V. Typical values are TA = +25°C, unless otherwise noted.) Characteristic Input Voltage Range Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis Symbol Conditions Vin UVLO Min 1.2 Vin falls down UVLO threshold 1.75 UVLOhyst Overvoltage Lockout Threshold NCP367DPMUEB OVLO Overvoltage Lockout Hysteresis OVLOhyst Typ Max Unit 28 V 1.85 1.9 V 60 100 mV 4.54 4.7 45 100 mV Vin rises up OVLO threshold V 4.38 Vin versus Vout Resistance RDS(on) Vin = 5 V, Enable Mode, Load Connected to Vout 50 100 mW Supply Quiescent Current Idd No Load 42 130 mA Disable Mode Idddis EN = 1.2 V 35 110 mA Overcurrent Threshold NCP367DPMUEB IOCP Vin = 4.3 V, EN = low, Load Connected to Vout,, Rilim = 0 W, 1 A/ms, GS = 0.4 V 1.45 1.80 Overcurrent Response A 1.25 Ireg 1 A/ms, GS = low, Ilim = 1.51 A Current Limit Gain NCP367DPMUEB GSvalue GS = 1.2 V Battery Overvoltage Threshold OVBAT Vin = 4.2 V, 0°C to 85°C 4.3 4.35 4.4 V 100 160 200 mV 20 nA 4.0 ms 400 mV Battery Overvoltage Hysteresis OVHYS Vin = 4.2 V, 0°C to 85°C VBATLEAK Vin = 4.0 V, VBAT Deglitch Time VBATDEG VBAT > OVBAT Volflag Vin > OVLO Sink 1 mA on FLAG pin FLAGleak FLAG level = 5 V FLAG Leakage Current EN Voltage High Vih EN Voltage Low Vil EN Leakage Current ENleak GS Voltage High GS Voltage Low GS Leakage Current % 2.77 VBAT Pin Leakage FLAG Output Low Voltage 5.0 0.2 2.0 10 nA 1.2 V 0.4 200 Vih 1.2 V Vil 0.4 GSleak V nA 200 V nA TIMINGS Start Up Delay ton From Vin > UVLO to Vout = 0.8xVin 15 30 45 ms tstart From Vout > 0.2xVin to FLAG = 1.2 V 15 30 45 ms tREARM OCP Active 15 30 45 ms tREG OCP Active 1.2 1.8 3.0 ms toff From Vin > OVLO to Vout ≤ 0.3 V, Vin increasing from 4 V to 7 V at 3 V/ms. 1.5 5.0 ms Alert Delay tstop From Vin > OVLO to FLAG ≤ 0.4 V, (see Figure 16) Vin increasing from 4 V to 7 V at 3 V/ms 1.5 ms Disable Time tdis From EN 0.4 to 1.2 V to Vout ≤ 0.3 V 3.0 ms Tsd 150 °C Tsdhyst 30 °C FLAG going up Delay Rearming Delay Overcurrent Regulation Time Output Turn Off Time Thermal Shutdown Temperature Thermal Shutdown Hysteresis NOTE: Electrical parameters are guaranteed by correlation across the full range of temperature. www.onsemi.com 5 NCP367 ELECTRICAL CHARACTERISTICS − Other OVLO version (Min/Max limits values (−40°C < TA < +85°C) and Vin = +5.0 V. Typical values are TA = +25°C, unless otherwise noted.) Characteristic Symbol Input Voltage Range Vin Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis UVLO Min OVLO Overvoltage Lockout Hysteresis OVLOhyst Vin versus Vout Resistance Vin falls down UVLO threshold 1.75 Supply Quiescent Current Disable Mode Overcurrent Threshold V 100 mV 5.85 6.07 6.84 7.20 6.05 6.28 7.08 7.50 100 150 mV 50 100 mW 42 130 mA 40 110 mA IOCP Vin = 5 V, EN = low, Load Connected to Vout,, Rilim = 0 W, 1 A/ms, GS = 0.4 V 1.51 2.85 1.80 3.40 A 1.25 2.30 1 A/ms, GS = low, Ilim = 1.51 A 5.0 GS = 1.2 V 2.70 2.55 % OVBAT 0°C to 85°C 4.3 4.35 4.4 V OVHYS 0°C to 85°C 100 150 200 mV 20 nA 4.0 ms 400 mV VBAT Deglitch Time VBATDEG VBAT > OVBAT Volflag Vin > OVLO Sink 1 mA on FLAG pin FLAGleak FLAG level = 5 V EN Voltage High Vih Vin from 3.3 V to 5.25 V EN Voltage Low Vil Vin from 3.3 V to 5.25 V EN Leakage Current ENleak EN = 5.5 V or GND GS Voltage High Vih Vin from 3.3 V to 5.25 V GS Voltage Low Vil Vin from 3.3 V to 5.25 V GSleak EN = 5.5 V or GND GS Leakage Current 1.9 80 No Load VBATLEAK FLAG Leakage Current 1.85 EN = 1.2 V VBAT Pin Leakage FLAG Output Low Voltage V V Vin = 5 V, Enable Mode, Load Connected to Vout NCP367Dx GSvalue NCP367Ox Battery Overvoltage Hysteresis 28 Idd Ireg Battery Overvoltage Threshold Unit Idddis NCP367Dx NCP367Ox Overcurrent Response Max Vin rises up OVLO threshold 5.64 5.85 6.60 6.90 RDS(on) Typ 1.2 UVLOhyst Overvoltage Lockout Threshold NCP367xPMUEC NCP367DPMUEE NCP367DPMUEL NCP367OPMUEO Current Limit Gain Conditions 0.2 2.0 10 nA 1.2 V 0.4 200 V nA 1.2 V 0.4 200 V nA TIMINGS Start Up Delay ton From Vin > UVLO to Vout = 0.8xVin 15 30 45 ms tstart From Vout > 0.2xVin to FLAG = 1.2 V 15 30 45 ms tREARM OCP Active 15 30 45 ms tREG OCP Active 1.2 1.8 3.0 ms toff From Vin > OVLO to Vout ≤ 0.3 V, Vin increasing from 5 V to 8 V at 3 V/ms. 1.5 5.0 ms Alert Delay tstop From Vin > OVLO to FLAG ≤ 0.4 V, (see Figure 16) Vin increasing from 5 V to 8 V at 3 V/ms 1.5 ms Disable Time tdis From EN 0.4 to 1.2 V to Vout ≤ 0.3 V 3.0 ms Tsd 150 °C Tsdhyst 30 °C FLAG going up Delay Rearming Delay Overcurrent Regulation Time Output Turn Off Time Thermal Shutdown Temperature Thermal Shutdown Hysteresis NOTE: Electrical parameters are guaranteed by correlation across the full range of temperature. www.onsemi.com 6 NCP367 TYPICAL OPERATING CHARACTERISTICS Vin Vin Vin toff Vin ton /FLAG /FLAG Vout Vout tstop tstart /FLAG /FLAG Figure 3. Hot Plug−in from 0 to 5 V, ton and tstart Figure 4. Overvoltage from 5 to 8 V, toff and tstop Vin ton Vout V Vin in Vin tstart Vout VVout out /Flag Figure 5. Retrieve Normal Operation, ton and tstart /Flag /Flag Figure 6. Overvoltage from 0 to 10 V VBatDEG Vin Vbat Vout /Flag Figure 7. Battery Overvoltage, Deglitch Time www.onsemi.com 7 NCP367 TYPICAL OPERATING CHARACTERISTICS 2.00 5.66 1.98 5.62 UVLO + hysteresis 1.92 OVLO (V) UVLO (V) 1.94 1.90 1.88 UVLO 1.86 5.60 5.58 OVLO − Hysteresis 5.56 5.54 1.84 5.52 1.82 1.80 −50 OVLO 5.64 1.96 −25 0 25 50 75 100 5.50 −50 125 −25 0 TEMPERATURE (°C) 25 50 75 100 125 TEMPERATURE (°C) Figure 8. UVLO and Hysteresis Figure 9. OVLO and Hysteresis vs. Temperature (5.6 V version) 20 4.40 4.35 15 VBATLEAK (nA) OVBAT (V) 4.30 4.25 4.20 10 5 4.15 4.10 −50 −25 0 25 50 75 100 0 −50 125 TEMPERATURE (°C) −25 0 25 50 75 100 TEMPERATURE (°C) Figure 11. VBAT Pin Leakage vs. Temperature Figure 10. VBAT Threshold and Hysteresis vs. Temperature www.onsemi.com 8 125 NCP367 APPLICATION INFORMATION Operation FLAG output is tied to low as long as Vin is higher than OVLO. This circuit has a 100 mV hysteresis to provide noise immunity to transient conditions. The NCP367 is an integrated IC which offers a complete protection of the portable devices during the Li ion battery charge. First, the input pin is protected up to +30 V, protecting the down stream system (charger, transceiver, system...) against the power supply transients such as inrush current or defective functionality. Additional protection level is offered with the overcurrent block which eliminates current peak or opens the charge path if an overcurrent default appears. More of that, the battery voltage is monitored all along the input power supply is connected, allowing to open charge path if Li ion battery voltage exceeds 4.3 V, caused by CCCV charger or battery pack fault. The integrated pass element (PMOS FET) is sized to support very high charge DC current up to 2.3 A. The overcurrent threshold can be externally adjusted with a pull−down resistor and gain select pin is available to divide current limit threshold with internal fixed gain. Allowing to adjust with logic pin the overcurrent threshold if USB/500 mA or WA/1.5 A is detected, without changing RILIM resistor, in example. Undervoltage, Overvoltage, Overcurrent and thermal faults are signalized thanks to the open drain FLAG pin, by pulling its down. FLAG Output NCP367 provides a FLAG output, which alerts external systems that a fault has occurred. This pin is tied to low as soon as the OVLO, OVBAT, IOCP or internal temperature thresholds are exceeded and remains low until between minimum driving voltage and UVLO threshold. When Vin level recovers normal condition, FLAG is held high. The pin is an open drain output, thus a pull up resistor (typically 1 MW − Minimum 10 kW) must be provided to VCC. FLAG pin is an open drain output, which is able to support 1 mA maximum. EN Input To enable normal operation, the EN pin shall be forced to low or connected to ground. A high level on the pin, disconnects OUT pin from IN pin. EN does not overdrive a UVLO or OVLO fault. Overcurrent Protection (OCP) This device integrates the overcurrent protection function, from wall adapter to battery. That means the current across the internal PMOS is regulated and cut when the value, set by external RSEL resistor, exceeds ILIM longer than tREG. An internal resistor is placed in series with the pin allowing to have a maximum OCP value when ILIM pin is directly connected to GND. By adding external resistors in series with ILIM and GND, the OCP value is decreased. An additional logic pin, GS (gain select), is very useful in case of different charge rate is necessary (Wall adapter and USB, for example). By setting GS to 0.4 V, overcurrent thresholds are depending on R select resistor, which is connect between pin 4 and GND. When the GS pin is tied to 1.2 V (high logic level) the preselected current limit is divided by 2.75. Due Undervoltage Lockout (UVLO) To ensure proper operation under any conditions, the device has a built−in undervoltage lock out (UVLO) circuit. During Vin positive going slope, the output remains disconnected from input until Vin voltage is above 1.85 V plus hysteresis nominal. This circuit has a 80 mV hysteresis to provide noise immunity to transient condition. Overvoltage Lockout (OVLO) To protect connected systems on Vout pin from overvoltage, the device has a built−in overvoltage lock out (OVLO) circuit. During overvoltage condition, the output remains disabled as long as the input voltage exceeds this threshold. www.onsemi.com 9 NCP367 to this option, both fast charge or USB charge are authorized with the same device. RLIM (kW) = 249 / IOCP − 165 NCP367OxMUxxTBG RLIM (kW) = 532 / IOCP − 180 During overcurrent event, charge area is opened and FLAG output is tied to low, allowing the mController to take into account the fault event and then open the charge path. At power up (accessory is plugged on input pins), the current is limited up to ILIM during 1.8 ms (typical), to allow capacitor charge and limit inrush current. If the ILIM threshold is exceeded over 1.8 ms, the device enter in OCP burst mode until the overcurrent event disappears. IOCP (mA) 1500 1000 GS = Low VBAT Sense 500 The connection of the VBAT pin to the positive connection of the Li ion battery pack allows preventing overvoltage transient, greater than 4.35 V. In case of wrong charger conditions, the PMOS is then opened, eliminating Battery pack over voltage which could create safety issues and temperature increasing. The 4.35 V comparator has a 150 mV built−in hysteresis. More of that, deglitch function of 2 ms is integrated to prevent voltage transients on the Battery voltage. If the battery over voltage condition exceeds deglitch time, the charge path is opened and FLAG pin is tied to low level until the VBAT is greater than 4.35 V – hysteresis. At wall adapter insertion, and if the battery is fully charged, Vbat comparator stays locked until battery needs to be recharged (4.2 V typ − 4.1 V min). A serial resistor has to be placed in series with Vbat pin and battery connection, with a 200 kW recommended value. GS = High 0 0 100 200 300 400 500 Rilim(kW) 600 700 800 Figure 12. IOCP versus RLIM, GS = low and high, 1.5 A version IOCP (mA) 3 2 GS = Low 1 GS = High PCB Recommendations 0 0 100 200 300 400 500 600 700 The NCP367 integrates low RDS(on) PMOS FET, nevertheless PCB layout rules must be respected to properly evacuate the heat out of the silicon. The DFN PAD1 corresponds to the PMOS drain so must be connected to OUT plane to increase the heat transfer. Of course, in any case, this pad shall be not connected to any other potential. Following figure shows package thermal resistance of a DFN 2.2x2 mm. 800 Rilim (kW) Figure 13. Over Current Threshold versus RLIMIT 2.85 A Version Typical RLIM calculation is following: NCP367DxMUxxTBG www.onsemi.com 10 NCP367 240 1.2 Theta JA curve with PCB cu thk 1.0 oz Theta JA curve with PCB cu thk 2.0 oz Power curve with PCB cu thk 2.0 oz Power curve with PCB cu thk 1.0 oz 220 1.1 200 180 0.9 160 0.8 140 T_ambient 25°C 120 Max Power (W) Theta JA (°C/W) 1 0.7 0.6 100 80 0 100 200 300 400 500 600 0.5 700 COPPER HEAT SPREADER AREA (mm2) Figure 14. Internal PMOS FET ESD Tests NCP367 includes an internal PMOS FET to protect the systems, connected on OUT pin, from positive over−voltage. Regarding electrical characteristics, the RDS(on), during normal operation, will create low losses on Vout pin versus Vin, due to very low RDS(on). NCP367 fully support the IEC61000−4−2, level 4 (Input pin, 1 mF mounted on board). That means, in Air condition, Vin has a ±15 kV ESD protected input. In Contact condition, Vin has ±8 kV ESD protected input. Please refer to Figure 16 to see the IEC 61000−4−2 electrostatic discharge waveform. 100 90 RDS(on) (mW) 80 70 60 50 40 30 20 −50 −25 0 25 50 75 TEMPERATURE (°C) 100 125 Figure 16. IEC 61000−4−2 Electrostatic Discharge Figure 15. Typical RDS(on) versus Temperature www.onsemi.com 11 NCP367 ORDERING INFORMATION Marking Package Shipping† NCP367DPMUECTBG DC DFN8 (Pb−Free) 3000 / Tape & Reel NCP367DPMUEETBG DE DFN8 (Pb−Free) 3000 / Tape & Reel NCP367DPMUELTBG DL DFN8 (Pb−Free) 3000 / Tape & Reel NCP367OPMUEOTBG P3 DFN8 (Pb−Free) 3000 / Tape & Reel NCP367OPMUEATBG EA DFN8 (Pb−Free) 3000 / Tape & Reel NCP367DPMEBTBG PE DFN8 (Pb−Free) 3000 / Tape & Reel NCP367OPMUECTBG EC DFN8 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. SELECTION GUIDE The NCP367 can be available in several undervoltage and overvoltage thresholds versions. Part number is designated as follows: NCP367xxMUxxTBG ab cd Code Contents a Overcurrent threshold a = D: 1.51 A a = O: 2.85 A b VBAT Voltage b: P = 4.36 V (additional thresholds available for a wide Lithium ion material range) c UVLO Typical Threshold c: E = 1.85 V d OVLO Typical Threshold (Additional thresholds available) d: C = 5.85 V d: E = 6.07 V d: L = 6.85 V d: O = 7.20 V d: A = 3.80 V d: B = 4.54 V www.onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN8, 2.0x2.2, 0.5P CASE 506BP−01 ISSUE A 8 DATE 13 JAN 2010 1 SCALE 4:1 A B D PIN ONE REFERENCE 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L L1 ÉÉÉ ÉÉÉ ÉÉÉ DETAIL A E ALTERNATE TERMINAL CONSTRUCTIONS 0.10 C 2X 0.10 C ÇÇÇ ÇÇÇ ÉÉÉ EXPOSED Cu TOP VIEW (A3) DETAIL B 0.05 C DIM A A1 A3 b D D2 E E2 e K L L1 A MOLD CMPD DETAIL B 9X ALTERNATE CONSTRUCTIONS 0.05 C NOTE 4 SIDE VIEW A1 C SEATING PLANE D2 DETAIL A L 1 8 K 5 e 1.43 1.05 0.20 0.25 --- 1 4 E2 8X 0.20 0.10 C A B 8X b 0.10 C A B e/2 BOTTOM VIEW 0.05 C MILLIMETERS TYP MAX --1.00 --0.05 0.20 REF --0.30 2.00 BSC --1.53 2.20 BSC --1.25 0.50 BSC 0.22 0.30 --0.35 --0.15 GENERIC MARKING DIAGRAM* 0.10 C A B 8X MIN 0.80 0.00 NOTE 3 XXMG G XX = Specific Device Code M = Date Code G = Pb−Free Device *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. SOLDERING FOOTPRINT* 1.63 ÇÇ Ç ÇÇ ÇÇ ÇÇÇÇÇÇÇ 1.15 ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ 1 0.50 PITCH 8X 0.45 2.50 8X 0.28 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON38697E DFN8, 2.0X2.2, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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