NCP372
Positive and Negative
Overvoltage Protection
Controller with Internal
Low Ron NMOS FETs and
Status FLAG
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The NCP372 is able to disconnect systems from its output pin
when wrong operating conditions are detected at it’s input. The
system is both positive and negative overvoltage protected up to
±28 V.
This device uses internal NMOS, and therefore, no external device
is necessary, reducing the system cost and the PCB area of the
application board.
The NCP372 is able to instantaneously disconnect the output from
the input, due to integrated Low Ron Power NMOS, if the input
voltage exceeds the overvoltage threshold (OVLO) or undervoltage
threshold (UVLO).
At powerup (EN pin = low level), the Vout turns on 30 ms after the
Vin exceeds the undervoltage threshold.
The NCP372 provides a negative going flag (FLAG) output, which
alerts the system that a fault has occurred.
In addition, the device has ESD−protected input (15 kV Air) when
bypassed with a 1.0 mF or larger capacitor.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Overvoltage Protection up to 28 V
Negative Voltage Protection down to −28 V
Reverse Current Blocking
On−Chip Low RDS(on) NMOS Transistor: Typical 130 mW
Overvoltage Lockout (OVLO)
Undervoltage Lockout (UVLO)
Soft−Start
Alert FLAG Output
Shutdown EN Input
Compliance to IEC61000−4−2 (Level 4)
8.0 kV (Contact)
15 kV (Air)
ESD Ratings: Machine Model = B
Human Body Model = 2
12 Lead LLGA 3x3 mm Package
This is a Pb−Free and Halogen−Free Device
MARKING
DIAGRAM
NCAI
372
ALYWG
G
1
12 PIN LLGA
MU SUFFIX
CASE 513AK
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
IN
1
12 OUT
IN
2
11
OUT
GND
3
10
FLAG
RES
4
RES
RES
NCP372
9
EN
5
8
NC
6
7
GND
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
Applications
•
•
•
•
•
•
Cell Phones
Camera Phones
Digital Still Cameras
Personal Digital Assistant
MP3 Players
GPS
© Semiconductor Components Industries, LLC, 2010
October, 2010 − Rev. 1
1
Publication Order Number:
NCP372/D
NCP372
TYPICAL APPLICATION CIRCUIT AND FUNCTIONAL BLOCK DIAGRAM
10k
Charger
Wall Adapter
1mF
U1
1
2
3
4
5
6
12
IN
OUT 11
IN
OUT 10
GND FLAG 9
RES
EN 8
NC 7
RES
RES
GND
NCP372
FLAG
EN
System
FLAG
4.7mF
0
LI+BATTERY
EN
GND
Figure 1. Typical Application Circuit
OUTPUT
INPUT
Gate Driver
VREF
Charge
Pump
EN
Block
UVLO
OVLO
Control
Logic
and
Timer
FLAG
Thermal
Shutdown
EN
Figure 2. Functional Block Diagram
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2
GND
NCP372
PIN FUNCTION DESCRIPTION
Pin
Name
Type
Description
1, 2
IN
POWER
Input voltage pins. These pins are connected to the power supply. A 1 mF low ESR ceramic capacitor, or
larger, must be connected between these pins and GND. The two IN pins must be hardwired to common
supply.
3
GND
POWER
Main Ground
4
RES
INPUT
Reserved pin. This pin must be connected to GND.
5
RES
INPUT
Reserved pin. This pin must be connected to GND.
6
RES
INPUT
Reserved pin. This pin must be connected to GND.
7
GND
POWER
8
NC
NC
9
EN
INPUT
10
FLAG
OUTPUT
Fault Indication Pin. This pin allows an external system to detect fault condition. The pin goes low when
input voltage exceeds OVLO threshold, drops below UVLO threshold, or internal temperature exceeds
thermal shutdown limit. Since the pin is open drain functionality, an external pull up resistor to VBat must
be added (10 kW minimum value).
11,12
OUT
OUTPUT
Output Voltage Pin. This pin follows IN pins when “no input fault” is detected. The output is disconnected
from the VIN power supply when the input voltage is under the UVLO threshold or above OVLO threshold
or thermal shutdown limit is exceeded.
13
PAD1
POWER
The PAD1 is used to dissipate the internal MOSFET thermal energy and must be soldered to an isolated
PCB area. The area must not be connected to any potential other than a completely isolated one. See
PCB Recommendations on page 10.
This pin must be directly hardwired to GND or through a pull down resistor with a 1 MW maximum value.
Not Connected
Enable Pin. The device enters into shutdown mode when this pin is tied to a high level. In this case the
output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to GND
to a pull−down or to an I/O pin. This pin does not have an impact on the fault detection.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Vminin
−30
V
Vmin
−0.3
V
Maximum Voltage (IN to GND)
Vmaxin
30
V
Maximum Voltage (OUT to GND)
Minimum Voltage (IN to GND)
Minimum Voltage (All others to GND)
Vmaxout
10
V
Maximum Voltage (All others to GND)
Vmax
7
V
Maximum DC Current
Imax
2.5
A
RqJA
200
°C/W
TA
−40 to +85
°C
TSTG
−65 to +150
°C
TJ
150
°C
ESD Withstand Voltage (IEC 61000−4−2)
Human Body Model (HBM), Model = 2, (Note 2)
Machine Model (MM) Model = B, (Note 3)
Vesd
15kV air, 8kV contact
2000V
200V
kV
V
V
Moisture Sensitivity
MSL
Level 1
Thermal Resistance, Junction−to−Air, (Note 1)
Operating Ambient Temperature Range
Storage Temperature Range
Junction Operating Temperature
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The RqJA is highly dependent on the PCB heat sink area (connected to PAD1). See PCB recommendation paragraph.
2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114.
3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
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3
NCP372
ELECTRICAL CHARACTERISTICS (Vin = 5 V, Minimum/Maximum limits at −40°C < TA < +85°C unless otherwise noted. Typical
values are at TA = +25°C)
Characteristics
Input Voltage Range
Input Voltage
Undervoltage Lockout Threshold
Symbols
Conditions
Min
Vin
EN = low or high, Vout = 0 V
−28
Vinmin
EN = low or high, Vout = 4.25V
−24
Typ
Max
Unit
28
V
V
UVLO
Vin falls below UVLO Threshold
2.6
2.7
2.8
V
UVLOhyst
Vin rises above UVLO Threshold + UVLOhyst
45
60
75
mV
Over voltage Lockout Threshold
NCP372MUAITXG
OVLO
Vin rises above OVLO threshold
6.0
6.3
6.6
V
Overvoltage Lockout Hysteresis
OVLOhyst
Vin falls below to OVLO − OVLOhyst
60
80
100
mV
RDS(on)
Vin = 5 V, EN = low, Load Connected to Vout
Vin = 5 V, EN = low,
Load Connected to Vout @ 25°C
130
220
mW
130
200
IddSTD
No Load. EN = high, Vin connected
90
170
mA
Input Supply Quiescent Current
IddIN
25°C
Overtemperature Range
200
260
310
mA
FLAG Output Low Voltage
Volflag
1.2 V < Vin < UVLO
Sink 50 mA on FLAG Pin
30
400
mV
Undervoltage Lockout
Hysteresis
Vin to Vout Resistance
Input Standby Current
Vin > OVLO, Sink 1 mA on FLAG Pin
FLAG Leakage Current
FLAGleak
EN Voltage High
VihEN
EN Voltage Low
VilEN
EN Leakage Current
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
400
FLAG Level = 5.5 V
1.0
nA
1.2
V
0.55
ENleak
Vin connected
Vin disconnected
V
200
1.0
nA
TSD
150
°C
TSDHYST
30
°C
TIMINGS
Start Up Delay
ton
From Vin > UVLO to Vout w 0.3 V
20
30
40
ms
tstart
From Vout > 0.3 V to FLAG = 1.2 V
20
30
40
ms
toff
From Vin > OVLO to Vout v 0.3 V
Vin Increasing from 5 V to 8 V at 3 V/ms
1.5
5.0
ms
Alert Delay
tstop
From Vin > OVLO to FLAG v 0.4 V See Figure 3
and 9 Vin Increasing from 5 V to 8 V at 3 V/ms
1.5
ms
Disable Time
tdis
EN = 0.4 V to 1.2 V to Vout v 0.3 V
2.5
ms
FLAG Going Up Delay
Turn Off Delay
NOTE:
Electrical parameters are guaranteed by correlation across the full range of temperature.
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4
NCP372
TIMING DIAGRAMS
OVLO
Vout = 0
FLAG = Low
Timer Count
OVLO > Vin > UVLO
Timer Check
T < ton
T = ton
Reset Timer
Vin < UVLO or
Vin > OVLO
Check Vin
FLAG = Low
Timer Count
UVLO < Vin < OVLO
EN = 1
EN = 0
Check EN
Vout = Open
Vin < UVLO or
Vin > OVLO
Vout = Vin
T < tstart
Timer Check
T = tstart
Check EN
UVLO < Vin < OVLO
EN = 1
Vout = Open
FLAG = High
Check Vin
UVLO < Vin < OVLO
EN = 0
Vout = Vin
FLAG = High
Check Vin
Vin < UVLO or
Vin > OVLO
Figure 17. State Machine
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9
NCP372
Thermal Shutdown protection
PCB Recommendations
In case of internal overheating, the integrated thermal
shutdown protection turns off the internal MOSFETs in
order to instantaneously decrease the device temperature.
The thermal threshold has been set at 150°C FLAG then
goes low to inform the MCU.
As the thermal hysteresis is 30°C, the MOSFETs will
turn on as soon the device temperature falls below 120°C.
If the fault event is still present, the temperature increase
engages the thermal shutdown again until the fault event
disappears.
Since the NCP372 integrates 2.5 A N−MOSFETs, PCB
rules must be respected to properly evacuate the heat out of
the silicon.
From an applications standpoint, PAD1 of the NCP372
package should be connected to an isolated PCB area to
increase the heat transfer if necessary.
In any case, PAD1 should be not connected to any other
potential or GND other than the isolated extra copper
surface.
To assist in the design of the transfer plane connected to
PAD1, Figure 18 shows the copper area required with
respect to RqJA.
MAXIMUM qTA (°C/W)
250
2.5
Power Curve with
PCB cu thk 2 oz
200
150
2
Power Curve with
PCB cu thk 1 oz
100
1
qJA Curve with
PCB cu thk 2 oz
50
0
1.5
0
100
200
qJA Curve with
PCB cu thk 1 oz
300
400
500
0.5
600
0
700
COPPER HEAT SPREAD AREA (mm2)
Figure 18. Copper heat Spread Area
ESD Tests
The NCP372 conforms to the IEC61000−4−2, level 4 on
the Input pin. A 1 mF (I.E Murata GRM188R61E105KA12D)
must be placed close to the IN pins. If the IEC61000−4−2 is
not a requirement, a 100 nF/25 V must be placed between IN
and GND.
The above configuration supports 15 kV (Air) and 8 kV
(Contact) at the input per IEC61000−4−2 (level 4).
Please refer to Figure 19 for the IEC61000−4−2
electrostatic discharge waveform.
Figure 19. Ipeak = f(t)/IEC61000−4−2
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10
NCP372
RDS(on) and Dropout
As example: Rload = 8 W, Vin= 5 V. RDS(on) = 155 mW. Iout
= 800 mA.
The NCP372 includes two internal low RDS(on)
N−MOSFETs to protect the system, connected on OUT pin,
from overvoltage, negative voltage and reverse current
protection. During normal operation, the RDS(on)
characteristics of the N−MOSFETs give rise to low losses
on Vout pin.
Vout = 4.905 V
NMOS Losses = RDS(on) x Iout2 = 0.155 x 0.82 = 0.0992 W
ORDERING INFORMATION
Device
NCP372MUAITXG
Marking
Package
Shipping†
NCAI
372
LLGA12
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
SELECTION GUIDE
The NCP372 can be available in several undervoltage and overvoltage options. Part number is designated as follows:
NCP372MUxxTxG
ab c d
Code
Contents
a
UVLO Typical Threshold
a: A = 2.7 V
b
OVLO Typical Threshold
b: I = 6.3 V
c
Tape & Reel Type
c: X = 3000
d
d: G = Pb−Free
The products described herein (NCP372), may be covered by one or more U.S. patents. There may be other patents pending.
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11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
LLGA12 3x3, 0.5P
CASE 513AK−01
ISSUE O
DATE 28 JUN 2007
1
SCALE 4:1
PIN ONE
REFERENCE
2X
0.15 C
2X
ÇÇÇ
ÇÇÇ
ÇÇÇ
0.15 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A B
D
E
DIM
A
A1
b
D
D2
E
E2
e
K
L
TOP VIEW
0.10 C
A
12X
0.08 C
A1
GENERIC
MARKING DIAGRAM*
SIDE VIEW
C
SEATING
PLANE
XXXXX
XXXXX
ALYWG
G
D2
1
12X
12X
6
K
L
e
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
E2
12
7
12X
b
BOTTOM VIEW
MILLIMETERS
MIN
MAX
0.50
0.60
0.00
0.05
0.20
0.30
3.00 BSC
2.60
2.80
3.00 BSC
1.90
2.10
0.50 BSC
0.20
−−−
0.25
0.35
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.10 C A B
0.05 C
NOTE 3
SOLDERING FOOTPRINT*
3.30
12X
0.50
1
0.50
PITCH
0.43
2.75
11X
0.30
2.05
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON24833D
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
12 PIN LLGA, 3 X 3 X 0.55T, 0.5P
PAGE 1 OF 1
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