NCP392B
Adjustable Front End
Overvoltage Protection
Controller with Protected
Vbus Output
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The NCP392B is an overvoltage front end protection and be able to
disconnect the systems from its output pin in case wrong input
operating conditions are detected, up to +28 V. Due to this device
using internal NMOS, no external device is necessary, reducing the
system cost and the PCB area of the application board.
Internal OVLO threshold is available, or can be adjusted if external
resistor bridge is used (A version).
At power up (EN pin = low level), the Vout turns on tstart time after
internal timer elapsed.
Additional timer option is available in the B version for OTG
supporting.
A LDO, internally connected on IN pin, provided a protected output
voltage even if an over voltage is present on IN pin.
MARKING
DIAGRAM
A
Y
WW
G
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Over−voltage Protection Up to + 28 V
On−chip Low RDS(on) NMOS Transistors: Typical 34 mW
Over−voltage Lockout (OVLO)
Externally Adjustable OVLO (A Version)
Protected VBUS Indicator Output VBUS_DET
Internal 15 ms Startup Delay
100 ms Start Up Delay Option (B Version)
Shutdown EN Input
+ 100 V Surge Capability, in Compliance with IEC61000−4−5
Standard
Compliance to IEC61000−4−2 (Level 4)
8 kV (Contact)
15 kV (Air)
ESD Ratings:
Machine Model = B (200 V)
Human Body Model = 2 (2 kV)
CSP−12 package 1.3 x 2.0 mm, 0.4 mm Pitch
This is a Pb−Free Device
392BR
AYWW
G
WLCSP 12
FCC SUFFIX
CASE 567JM
= Assembly Location
= Year
= Work Week
= Pb−Free Package
PIN CONNECTION
1
2
3
4
/EN
OUT
OUT
PGND
B
VBUS
_D
OUT
IN
PGND
C
OVLO
IN
IN
PGND
A
(Top View)
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 9 of this data sheet.
Typical Applications
•
•
•
•
•
Cell Phones
Tablets
Camera Phones
Digital Still Cameras
Personal Digital Applications
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 1
1
Publication Order Number:
NCP392B/D
NCP392B
B3 IN
0.1 mF
NCP392B
OUT A2
C2 IN
OUT A3
C3 IN
OUT B2
OUTPUT
CHARGER
Lithium Battery
PMIC
C1 OVLO
GND
A4
GND GND
C4
B4
EN
A1
VBUS_D B1
VBUS_DET
/EN
Figure 1. Typical Application Circuit: NCP392B with Adjustable OVLO
FUNCTIONAL BLOCK DIAGRAM
INPUT
OUTPUT
Gate driver
OVLO
GND
selected
Charge
Pump
OVLO
TSD
R1
C1
External OVLO
VREF
Internal OVLO
selected
R2
C2
OVLO
Control
logic and
Timer
SEL
VIN
/EN
LDO
VBUS_DET
Figure 2. Functional Block Diagram
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2
/EN
NCP392B
PIN FUNCTION DESCRIPTION
1
2
3
4
/EN
OUT
OUT
PGND
B
VBUS
_D
OUT
IN
PGND
C
OVLO
IN
IN
PGND
A
(Top View)
Figure 3. Pinout
Table 1. NCP392 PIN DESCRIPTION
Pin
Pin
Name
Type
A1
EN
I/O
A2,
A3,
B2
OUT
OUTPUT
Output voltage pins.
These pins follow IN pins, with debounce time, when “no fault” are detected.
The outputs are disconnected from the Vin power supply when the input voltage is below UVLO,
above OVLO threshold or internal thermal protection is exceeded.
The three OUT pins must be hardwired together and used for power dissipation.
A4,
B4,
C4
PGND
POWER
Ground. The three GND pins must be hardwired together and connect to the system GND.
B1
VBUS_D
ET
OUTPUT
Vbus detect pin. This pin reflects Vin pin, and be in pass through mode up to regulation level. Upper
this trip, this output regulates IN voltage whatever OVLO event or /EN setting.
B3,
C2,
C3
IN
POWER
Input voltage pins.
These pins are connected to the power supply.
The three IN pins must be hardwired together.
C1
OVLO
INPUT
Description
Enable pin bar.
The device enters in shutdown mode when this pin is tied to a high level. In this case the output is
disconnected from the input.
To allow normal functionality, the EN pin is tied low with internal pull down.
This pin does not have an impact on the VBUS_DET.
External OVLO Adjustment. Connect external resistor bridge to OVLO pin to select a different OVLO
threshold. Connect OVLO pin to GND if not used. In this case internal OVLO will be selected.
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3
NCP392B
Table 2. MAXIMUM RATINGS
Symbol
Value
Unit
Minimum Voltage (IN, OVLO to GND)
Rating
VminIN
−0.3
V
Minimum Voltage (All others to GND)
Vmin
−0.3
V
VmaxIN
29
V
Maximum Voltage (OVLO to GND)
VmaxOVLO
14
V
Maximum Voltage (OUT to GND)
VmaxOUT
22
V
Maximum Voltage (VBUS_DET to GND)
VmaxVBUS
10
V
Maximum Voltage (IN to GND)
Maximum Voltage (All others to GND)
Vmax
7
V
Maximum DC current
Imax
4.5
A
Peak input current
Ipeak
8
A
Thermal Resistance, Junction−to−Air
RqJA
70
°C/W
Operating Ambient Temperature Range
TA
−40 to +85
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Junction Operating temperature
TJ
+ 125
°C
ESD Withstand Voltage (IEC 61000−4−2)
Human Body Model (HBM), model = 2 (Note 1)
Machine Model (MM) model = B (Note 2)
Vesd
15 kV air, 8 kV contact
2000 V
200 V
kV
V
V
Moisture Sensitivity
MSL
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114.
2. Machine Model, 200 pF discharged through all pins following specification JESD22/A115
Table 3. ELECTRICAL CHARACTERISTICS
Min / Max limits values (−40°C < TA < +85°C and TJ = 125°C) and Vin = +5 V (Unless otherwise noted). Typical values are TA = +25°C.
Characteristics
Input Voltage Range
Under voltage Lockout
Under voltage Lockout hysteresis
Symbols
Conditions
Vin, VOVLO
Min
2.8
UVLO
Vin rising
UVLOhyst
Vin falling
Internal Over voltage Lockout
threshold NCP392BR
OVLO
Vin rising (Note 3)
OVLO pin tied to GND
25°C
5.9
Internal Over voltage Lockout
hysteresis
OVLOhyst
Vin falling
1.5
External OVLO Reference
OVLO_EXT
External OVLO select
40
60
5.95
1.221
4
OVLOEXThyst
Vin falling
Unit
28
V
2.8
V
80
mV
6
2.5
%
1.26
V
20
V
2
0.3
V
Vin = 5 V, /EN = GND, –40°C < TJ < 125°C
34
50
mW
Supply Quiescent Current
Idd
No load. /EN = 0.4 V
90
200
mA
Standby Current
Istb
No load. /EN = 1.2 V,
No load on VBUS_DET
150
mA
100
nA
OVLO select leakage
0.2
%
RDSon
Vin versus Vout Resistance
OVLOSEL
Max
V
1.18
External Adjustable OVLO
Over−Voltage Lockout Hysteresis
Typ
IOVLO
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Please contact your ON Semiconductor representative for additional OVLO threshold.
Electrical parameters are guaranteed by correlation across the full range of temperature.
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4
NCP392B
Table 3. ELECTRICAL CHARACTERISTICS
Min / Max limits values (−40°C < TA < +85°C and TJ = 125°C) and Vin = +5 V (Unless otherwise noted). Typical values are TA = +25°C.
Characteristics
Symbols
Conditions
Min
Typ
Max
Unit
VBUS_DET (A Version)
VBUS_DET Regulation
VBUSTHRES
VBUS_DET Pass Through
VBUS_DET ron
Vin > VBUSTHRES
6.5
9
V
Vin < VBUSTHRES, I load 1 mA
Vin – 0.2
Vin
V
LDORON
VBUS_DET Current
60
W
1.5
mA
LOGIC
EN Voltage High
EN Voltage Low
EN Pull−down
Vih
1.2
V
Vil
0.4
ENpd
V
100
kW
TIMINGS
tSTART
From Vin > 2.8 V to 10% Vout, /EN low
15
ms
tEN
Vin present, From /EN high to low, 10% Vout
15
ms
Soft start
tRISE
From 10% to 90% of Vout, C load 100 mF,
Rload, 100 W, /EN low
1
ms
VBUS_DET rise time
tVBUS
/EN low, From Vin applied to 90%
VBUS_DET, 4.7 mF load
3.5
Turn off time
tOFF
Surge off time
100
ns
Disable time
tDIS
From EN >1.2 V to 90% Vout. No load
20
ms
tOVLO
Vin rising 2 V/ms
1.5
ms
TSD
140
°C
TSD rearm
115
°C
Start up Time
Enable time
OVLO turn off time
5.5
ms
TSD
Thermal shutdown
Thermal shutdown rearming
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Please contact your ON Semiconductor representative for additional OVLO threshold.
Electrical parameters are guaranteed by correlation across the full range of temperature.
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5
NCP392B
Over−voltage Lockout (OVLO)
Operation
To protect connected systems on Vout pin from
over−voltage, the device has a built−in over−voltage lock
out (OVLO) circuit. During over−voltage condition, the
output remains disabled until the input voltage is above
OVLO – hysteresis.
The NCP392B provides over−voltage protection for positive
voltage surge, up to +28 V. An additional clamp, between IN
and GND, protects the part against surge test, following IEC
61000−4−5 standard. A protected VBUS_DET output pin
provides a secondary supply for the platform biasing.
Under−voltage Lockout (UVLO)
To ensure proper operation under any conditions, the
device has a built−in under−voltage lock out (UVLO)
circuit. This circuit has a built−in hysteresis to provide noise
immunity to transient conditions.
VIN
OVLO
UVLO
VBUS DET
VBUSTHRES
VOUT
/EN
tVBUS
tOFF
tSTART
tRISE
tSTART
tRISE
tSOFT
tSOFT
Figure 4. UVLO, OVLO and /EN Functionality
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6
tVBUS
tOFF
NCP392B
To select the internal OVLO threshold, the OVLO pin
must be externally tied to GND.
INPUT
INPUT
Internal OVLO
selected
OVLO
GND
OVLO
Internal OVLO
selected
C2
C1
GND
R2
VREF
R1
External OVLO
selected
VREF
SEL
VIN
LDO
VBUS_DET
SEL
VIN
Figure 6. External Connection to Resistor Bridge of
OVLO
LDO
Example:
NEW_OVLOTH target 12 V.
VBUS_DET
R1 + R2
Figure 5. External Connection to GND of OVLO
ǒR 1 ) R 2Ǔ
OVLO EXT
R2
(eq. 2)
R2
Taking into account external input bridge doesn’t have
excessive current consumption, and 1% is recommended:
If OVLO pin is not grounded, and by adding external
bridge resistor on OVLO pin, between IN and GND,
overvoltage protection can be adjusted as following:
NEW_OVLO TH +
ǒOVLO
* 1Ǔ + R2 ǒ 12 * 1Ǔ + 8.828
1.221
1.221
R2 arbitrarily fixed at 1.05 MW.
R1 = 9.269 MW (9.31 MW standard value)
Obtained typical OVLO = 12.04 V
C1 and C2 should be selected in such a way that the time
constant R1C1 = R2C2.
(eq. 1)
With: OVLOEXT = 1.221 V Typical (OVLO External
Reference)
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7
NCP392B
VIN
OVLO
UVLO
TSD
VBUS DET
VBUSTHRES
VOUT
OVLO
/EN
tOFF
tVBUS
tSTART
tVBUS
tRISE
tOFF
tSTART
tRISE
Figure 7. OVLOEXT, TSD Modes
EN Inputs and Production Mode
Thermal Shutdown Protection
To enable normal operation, the EN pin has to be at low
level. Internal pull down is embedded in the part.
A high level on the EN pin, disconnects OUT pin from IN
pin.
In case of internal overheating, the integrated thermal
shutdown (TSD) protection allows to open the internal
MOSFET in order to instantaneously decrease the device
temperature.
Embedded hysteresis allows to reengage the MOSFET
when the junction temperature decreases.
If the fault event is still present, the temperature increases
again and engages the thermal shutdown one more time until
fault event disappeared.
Table 4. CONTROL LOGIC MODES
OVP State
NCP392Bx
/EN
OVLO EXT
Low
High
Low
ON Tstart
15 ms
OFF
High
OFF
OFF
PCB Recommendations
To limit internal power dissipation, PCB routing must be
carefully done to improve current capability.
The NCP392B is declined in a CSP package. So power
dissipation can be decreased on each pin connection but
main thermal area must be as large as possible around IN and
OUT pins. Taking into account and respectively, four IN and
OUT pins must be hardwired together on the PCB.
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8
NCP392B
Maximum power dissipation can be calculated with
following formula:
T J * T A + R qJA
Pd
(eq. 3)
TJ: junction temperature
TA: ambient temperature
RqJA: thermal resistance of the junction to air through the
case and board.
Pd: power dissipation = RDS(on) x I2
ESD Tests
The NCP392B fully supports the IEC61000−4−2, level 4
(Input pin, 1 mF mounted on board).
That means, in Air condition, Vin has a ±15 kV ESD
protected input. In Contact condition, Vin has ±8 kV ESD
protected input.
Please refer to the Figure 8 to see the IEC 61000−4−2
electrostatic discharge waveform.
Figure 8. Ipeak = f(t) / IEC61000−4−2
ORDERING INFORMATION
Device
Marking
Option
Package
Shipping†
NCP392BRFCCT1G
392BR
OVLO 5.95 V
WLCSP
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP12, 1.3x2.0
CASE 567JM
ISSUE A
DATE 02 JUL 2014
SCALE 4:1
PIN A1
REFERENCE
2X
0.10 C
2X
ÈÈ
ÈÈ
ÈÈ
0.10 C
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
A B
DIE COAT
(OPTIONAL)
A3
D
DIM
A
A1
A2
A3
b
D
E
e
DETAIL A
TOP VIEW
A2
DETAIL A
GENERIC
MARKING DIAGRAM*
A
0.10 C
0.08 C
SIDE VIEW
NOTE 3
A1
C
XXXXXX
AYWW
G
SEATING
PLANE
A
Y
WW
G
e/2
12X
0.05 C A B
0.03 C
e
b
e
C
B
A
1
2
3
4
BOTTOM VIEW
MILLIMETERS
MIN
MAX
0.60
−−−
0.17
0.23
0.36 REF
0.04 REF
0.24
0.30
1.26
1.31
2.01
2.04
0.40 BSC
= Assembly Location
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
RECOMMENDED
SOLDERING FOOTPRINT*
A1
0.40
PITCH
PACKAGE
OUTLINE
12X
0.25
0.40
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON80460F
WLCSP12, 1.3X2.0
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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