NCP4300A
Dual Operational Amplifier
and Voltage Reference
The NCP4300A is a monolithic integrated circuit specifically
designed to control the output current and voltage levels of switch
mode battery chargers and power supplies. This device contains a
precision 2.6 V shunt reference and two operational amplifiers.
Op−Amp 1 is designed to perform voltage control and has its
non−inverting input internally connected to the reference. Op−Amp 2
is designed for current control and has both inputs uncommitted. The
NCP4300A offers the power converter designer a control solution that
features increased precision with a corresponding reduction in system
complexity and cost. This device is available in an 8−lead surface
mount package.
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MARKING
DIAGRAM
8
SOIC−8
D SUFFIX
CASE 751
8
1
1
A
L
Y
W
A
G
Features
• This is a Pb−Free Device
Operational Amplifier
•
•
•
•
•
•
Low Input Offset Voltage: 0.5 mV
Input Common Mode Voltage Range Includes Ground
Low Supply Current: 210 mA/Op−Amp (@VCC = 5.0 V)
Medium Unity Gain Bandwidth: 0.7 MHz
Large Output Voltage Swing: 0 V to VCC − 1.5 V
Wide Power Supply Voltage Range: 3.0 V to 35 V
• Fixed Output Voltage Reference: 2.60 V
• High Precision Over Temperature: 1.0%
• Wide Sink Current Range: 80 mA to 80 mA
Out 1 1
8
VCC
In 1− 2
7
Out 2
In 1+ 3
6
In 2−
GND 4
5
In 2+
(Top View)
ORDERING INFORMATION
Typical Applications
• Battery Charger
• Switch Mode Power Supply
8
-
1
+
3
Device
Package
Shipping†
NCP4300ADG
SOIC−8
(Pb−Free)
98 Units / Rail
NCP4300ADR2G
SOIC−8
(Pb−Free)
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Output 2
-
7
Inputs 1
VCC
+
2
6
2.6 V
GND
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Option Code
= Pb−Free Package
PIN CONNECTIONS
Voltage Reference
Output 1
N4300
ALYWA
G
4
Inputs 2
5
Figure 1. Functional Block Diagram
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 4
1
Publication Order Number:
NCP4300A/D
NCP4300A
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Supply Voltage (VCC to GND)
Rating
VCC
36
V
ESD Protection Voltage at any Pin (Human Body Model)
VESD
2.0 K (min)
V
Op−Amp 1 and 2 Input Voltage Range (Pins 2, 5, 6)
VIR
−0.6 to VCC +0.6
V
Op−Amp 2 Input Differential Voltage Range (Pins 5, 6)
VIDR
VCC to GND
V
Voltage Reference Cathode Current (Pin 3)
IK
100
mA
Maximum Junction Temperature
TJ
150
°C
Operating Ambient Temperature Range
TA
0 to 105
°C
Storage Temperature Range
Tstg
−55 to 150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Resistance, Junction−to−Ambient
RqJA
155
°C/W
Thermal Resistance, Junction−to−Case
RqJC
45
°C/W
TYPICAL ELECTRICAL CHARACTERISTICS
Characteristic
Total Supply Current, excluding Current in the Voltage Reference
VCC = 5.0 V, no load; 0°C v TA v 105°C
Symbol
Min
Typ
Max
Unit
ICC
−
0.42
0.8
mA
−
−
0.5
−
2.0
3.0
−
7.0
−
−
−
−50
−
−150
−150
50
25
100
−
−
−
Op−Amp 1 (Op−amp with non−inverting input connected to the internal Vref)
(VCC = 5.0 V, Vout = 1.4 V, TA = 25°C, unless otherwise noted)
Input Offset Voltage
TA = 25°C
TA = 0°C to 105°C
VIO
Input Offset Voltage Temperature Coefficient
TA = 0°C to 105°C
DVIO/DT
Input Bias Current (Inverting input only)
TA = 25°C
TA = 0°C to 105°C
IIB
mV
mV/°C
nA
Large Signal Voltage Gain (VCC = 15 V, RL = 2.0 kW, Vout = 1.4 V to 11.4 V)
TA = 25°C
TA = 0°C to 105°C
AVOL
Power Supply Rejection (VCC = 5.0 V to 30 V)
PSRR
40
90
−
dB
IO+
10
16
−
mA
Output Sink Current (VCC = 15 V, Vout = 2.0 V, VID = −1.0 V)
IO−
10
25
−
mA
Output Voltage Swing, High (VCC = 30 V, RL = 10 kW, VID = +1.0 V)
TA = 25°C
TA = 0°C to 105°C
VOH
27
27
28
−
−
−
Output Voltage Swing, Low (RL = 10 kW, VID = −1.0 V)
TA = 25°C
TA = 0°C to 105°C
VOL
−
−
17
−
100
100
Slew Rate (Vin = 0.5 to 2.0 V, VCC = 15 V, RL = 2.0 kW, Av = 1.0, CL = 100 pF)
SR
0.3
0.5
−
V/ms
Unity Gain Bandwidth (VCC = 30 V, RL = 2.0 kW, CL = 100 pF, Vin = 0.5 Vpp @
f = 70 kHz)
BW
0.3
0.7
−
MHz
Total Harmonic Distortion (f = 1.0 kHz, AV = 10, RL = 2.0 kW, VCC = 30 V,
Vout = 2.0 VPP)
THD
−
0.02
−
%
Output Source Current (VCC = 15 V, Vout = 2.0 V, VID = +1.0 V)
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2
V/mV
V
mV
NCP4300A
TYPICAL ELECTRICAL CHARACTERISTICS (continued)
Characteristic
Symbol
Min
Typ
Max
−
−
0.5
−
2.0
3.0
−
7.0
−
−
−
2.0
−
30
30
−
−
−50
−
−150
−150
−
0 to
VCC −1.5
−
50
25
100
−
−
−
40
90
−
40
30
60
−
−
−
Unit
Op−Amp 2 (Independent op−amp) (VCC = 5.0 V, Vout = 1.4 V, TA = 25°C, unless otherwise noted)
VIO
Input Offset Voltage
TA = 25°C
TA = 0°C to 105°C
Input Offset Voltage Temperature Coefficient
TA = 0°C to 105°C
DVIO/DT
Input Offset Current
TA = 25°C
TA = 0°C to 105°C
IIO
Input Bias Current
TA = 25°C
TA = 0°C to 105°C
IIB
Input Common Mode Voltage Range (VCC = 0 V to 35 V)
VICR
Large Signal Voltage Gain (VCC = 15 V, RL = 2.0 kW, Vout = 1.4 V to 11.4 V)
TA = 25°C
TA = 0°C to 105°C
AVOL
Power Supply Rejection (VCC = 5.0 V to 30 V)
PSRR
Common Mode Rejection (VCM = 0 V to 3.5 V)
TA = 25°C
TA = 0°C to 105°C
CMRR
mV
mV/°C
nA
nA
V
V/mV
dB
dB
Output Source Current (VCC = 15 V, Vout = 2.0 V, VID = +1.0 V)
IO+
10
16
−
mA
Output Sink Current (VCC = 15 V, Vout = 2.0 V, VID = −1.0 V)
IO−
10
25
−
mA
Output Voltage Swing, High (VCC = 30 V, RL = 10 kW, VID = +1.0 V)
TA = 25°C
TA = 0°C to 105°C
VOH
27
27
28
−
−
−
Output Voltage Swing, Low (RL = 10 kW, VID = −1.0 V)
TA = 25°C
TA = 0°C to 105°C
VOL
−
−
17
−
100
100
V
mV
Slew Rate (Vin = 0.5 to 3.0 V, VCC = 15 V, RL = 2.0 kW, Av = 1.0, CL = 100 pF)
SR
0.3
0.5
−
V/ms
Unity Gain Bandwidth (VCC = 30 V, RL = 2.0 kW, CL = 100 pF, Vin = 0.5 Vpp @
f = 70 kHz)
BW
0.3
0.7
−
MHz
Total Harmonic Distortion (f = 1.0 KHz, AV = 10, RL = 2.0 kW, VCC = 30 V,
Vout = 2.0 VPP)
THD
−
0.02
−
%
−
2.574
2.60
2.60
−
2.626
Voltage Reference
Reference Voltage (IK = 10 mA)
TA = 25°C
TA = 0°C to 105°C
Vref
V
Reference Input Voltage Deviation Over Full Temperature Range
(IK = 10 mA, TA = 0°C to 105°C)
DVref
−
5.0
22
mV
Minimum Cathode Current for Regulation
IK(min)
−
55
80
mA
Dynamic Impedance
TA = 25°C, IK = 1.0 to 80 mA, f t 1.0 KHz
TA = 0°C to 125°C, IK = 1.0 mA to 60 mA, f t 1.0 KHz
|ZKA|
−
−
0.3
−
0.5
0.6
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3
W
TA = 25°C
60
Vref, REFERENCE VOLTAGE (V)
IK, CATHODE CURRENT (mA)
NCP4300A
40
20
0
−20
−1.0
0
1.0
2.0
2.620
2.610
2.600
2.590
2.580
3.0
100
Figure 3. Reference Voltage
vs. Ambient Temperature
10
0.35
0.3
0.25
0
50
TA = 25°C
8.0
Stable
6.0
Unstable
4.0
2.0
Stable
0
100 pF
100
1000 pF
1.0 mF
10 mF
100 mF
CL, LOAD CAPACITANCE
TA, AMBIENT TEMPERATURE (°C)
Figure 5. Reference Stability
vs. Load Capacitance
Figure 4. Reference Dynamic Impedance
vs. Ambient Temperature
0
1.0
VCC = 5.0 V
IIB, INPUT BIAS CURRENT (nA)
VO, INPUT OFFSET VOLTAGE (mV)
80
Figure 2. Reference Cathode Current
vs. Cathode Voltage
IK = 1.0 mA to 60 mA
Op−Amp 2
0.5
0
Op−Amp 1
−0.5
−1.0
60
40
TA, AMBIENT TEMPERATURE (°C)
IK, CATHODE CURRENT (mA)
|ZKA|, DYNAMIC IMPEDANCE (W)
20
0
VKA, CATHODE VOLTAGE (V)
0.4
0.2
IK = 10 mA
0
20
40
60
80
VCC = 5.0 V
−5.0
−10
−15
Op−Amp 1
−20
−25
100
Op−Amp 2
0
20
40
60
80
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 6. Input Offset Voltage
vs. Ambient Temperature
Figure 7. Input Bias Current
vs. Ambient Temperature
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4
100
CMRR, COMMON MODE REJECTION RATIO (dB)
NCP4300A
65
VCC = 3.0 V to 35 V
60
105°C
55
25°C
50
0
0°C
10
20
30
40
VCC, SUPPLY VOLTAGE (V)
Figure 8. Common Mode Rejection Ratio
vs. Supply Voltage
DETAILED OPERATING DESCRIPTION
INTRODUCTION
Power supplies and battery chargers require precise
control of output voltage and current in order to prevent
catastrophic damage to the system connected. Many present
day power sources contain a wide assortment of building
blocks and glue devices to perform the required sensing for
proper regulation. Typical feedback loop circuits may
consist of a voltage and current amplifier, summing circuitry
and a reference. The NCP4300A contains all of these basic
functions in a manner that is easily adaptable to many of the
various power source−load configurations.
reference is initially trimmed to a ±0.5% tolerance at
TA = 25_C and is guaranteed to be within ±1.0% over an
ambient temperature range of 0_C to 105_C.
Voltage Sensing Operational Amplifier (Op−Amp 1)
The internal Op−Amp 1 is designed to perform the voltage
control function. The non−inverting input of the op−amp is
connected to the precision voltage reference internally. The
inverting input of the op−amp monitors the voltage
information derived from the system output. As the control
threshold is internally connected to the voltage reference,
the voltage regulation threshold is fixed at 2.6 V. For any
output voltage from 2.6 V up to the maximum limit can be
configurated with an external resistor divider. The output
terminal of Op−Amp 1 (pin 1) provides the error signal for
output voltage control. The output pin also provides a means
for external compensation.
OPERATING DESCRIPTION
The NCP4300A is an analog regulation control circuit that
is designed to simultaneously close the voltage and current
feedback loops in power supply and battery charger
applications. This device can control the feedback loop in
either constant−voltage (CV) or constant−current (CC)
mode with smooth crossover. A concise description of the
integrated circuit blocks is given in below. The functional
block diagram of the IC is shown in Figure 1.
Independent Operational Amplifier (Op−Amp 2)
The internal Op−Amp 2 is configurated as a general
purpose op−amp with all terminals available for the user.
With the low offset voltage provided, 0.5 mV, this op−amp
can be used for current sensing in a constant current
regulator.
Internal Reference
An internal precision band gap reference is used to set the
2.6 V voltage threshold and current threshold setting. The
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5
NCP4300A
Opto
Isolator
8
6
-
AC
Line
7
SMPS
Iout
+
+
2.6 V
+
2
Battery
Pack
R1
Vout
1
5
−
3
4
R3
R2
R4
R5
Current
Sense
The above circuit demonstrates the use of the NCP4300A in a constant−current constant−voltage switch mode battery charger application. The charging current level is set by resistors R3, R4, and R5. The reference voltage is divided down by resistors R3 and R4 to create an offset voltage at pin 6. This results in a high state at the op amp output, pin 7. As the battery pack
charge current increases, a proportional increasing voltage is developed across R5 that will eventually cancel out the pin 6
offset voltage. This will cause the op amp output to sink current from the opto isolator diode, and control the SMPS block
in a constant−current mode. Resistors R1 and R2 divide the battery pack voltage down to the 2.6 V reference level. As the
battery pack voltage exceeds the desired programmed level, the voltage at pin 2 will become slightly greater than pin 3. This
will cause the op amp output to sink current from the opto isolator diode, and control the SMPS block in a constant−voltage
mode. The formulas for programming the output current and voltage are given below.
Iout +
ǒ
Vref
R3 ) 1 R5
R4
ǒ
Ǔ
Vout + R1 ) 1 Vref
R2
Ǔ
With : R3 + 30 k
R4 + 1.2 k
R5 + 0.1
Iout + 1.0 A
With : R1 + 4.7 k
R2 + 3.6 k
Vout + 6.0 V
Figure 9. Constant−Current Constant−Voltage Switch Mode Battery Charger
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
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special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
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SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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