NCP4305
Secondary Side
Synchronous Rectification
Driver for High Efficiency
SMPS Topologies
The NCP4305 is high performance driver tailored to control a
synchronous rectification MOSFET in switch mode power supplies.
Thanks to its high performance drivers and versatility, it can be used in
various topologies such as DCM or CCM flyback, quasi resonant
flyback, forward and half bridge resonant LLC.
The combination of externally adjustable minimum off-time and
on-time blanking periods helps to fight the ringing induced by the PCB
layout and other parasitic elements. A reliable and noise less operation
of the SR system is insured due to the Self Synchronization feature. The
NCP4305 also utilizes Kelvin connection of the driver to the MOSFET
to achieve high efficiency operation at full load and utilizes a light load
detection architecture to achieve high efficiency at light load.
The precise turn−off threshold, extremely low turn−off delay time
and high sink current capability of the driver allow the maximum
synchronous rectification MOSFET conduction time and enables
maximum SMPS efficiency. The high accuracy driver and 5 V gate
clamp enables the use of GaN FETs.
www.onsemi.com
MARKING
DIAGRAMS
8
1
SOIC−8
D SUFFIX
CASE 751
1
4305x
ALYWG
G
1
• Self−Contained Control of Synchronous Rectifier in CCM, DCM and
•
•
•
•
•
•
•
•
•
•
NCP4305x
ALYW G
G
1
DFN8
MN SUFFIX
CASE 488AF
Features
•
•
•
•
•
•
•
8
WDFN8
MT SUFFIX
CASE 511AT
5xMG
G
QR for Flyback, Forward or LLC Applications
Precise True Secondary Zero Current Detection
4305x = Specific Device Code
Typically 12 ns Turn off Delay from Current Sense Input to Driver
x = A, B, C, D or Q
Rugged Current Sense Pin (up to 200 V)
A
= Assembly Location
Ultrafast Turn−off Trigger Interface/Disable Input (7.5 ns)
L
= Wafer Lot
Y
= Year
Adjustable Minimum ON−Time
W
= Work Week
Adjustable Minimum OFF-Time with Ringing Detection
M
= Date Code
G
= Pb−Free Package
Adjustable Maximum ON−Time for CCM Controlling of Primary
QR Controller
(Note: Microdot may be in either location)
Improved Robust Self Synchronization Capability
ORDERING INFORMATION
8 A / 4 A Peak Current Sink / Source Drive Capability
See
detailed
ordering and shipping information on page 49 of
Operating Voltage Range up to VCC = 35 V
this data sheet.
Automatic Light−load & Disable Mode
Typical Applications
Adaptive Gate Drive Clamp
• Notebook Adapters
GaN Transistor Driving Capability (options A and C)
• High Power Density AC/DC Power Supplies (Cell
Low Startup and Disable Current Consumption
Phone Chargers)
Maximum Operation Frequency up to 1 MHz
• LCD TVs
SOIC-8 and DFN−8 (4x4) and WDFN8 (2x2) Packages
• All SMPS with High Efficiency Requirements
These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2016
June, 2016 − Rev. 3
1
Publication Order Number:
NCP4305/D
NCP4305
Figure 1. Typical Application Example − LLC Converter with Optional LLD and Trigger Utilization
Figure 2. Typical Application Example − DCM, CCM or QR Flyback Converter with optional LLD and Disabled
TRIG
www.onsemi.com
2
NCP4305
Figure 3. Typical Application Example − Primary Side Flyback Converter with optional LLD and Disabled TRIG
Figure 4. Typical Application Example − QR Converter − Capability to Force Primary into CCM Under Heavy
Loads utilizing MAX−TON
www.onsemi.com
3
NCP4305
PIN FUNCTION DESCRIPTION
ver. A, B, C, D
ver. Q
Pin Name
1
1
VCC
2
2
MIN_TOFF
Adjust the minimum off time period by connecting resistor to ground.
3
3
MIN_TON
Adjust the minimum on time period by connecting resistor to ground.
4
4
LLD
This input modulates the driver clamp level and/or turns the driver off during light load
conditions.
5
−
TRIG/DIS
Ultrafast turn−off input that can be used to turn off the SR MOSFET in CCM applications in order to improve efficiency. Activates disable mode if pulled−up for more than
100 ms.
6
6
CS
Current sense pin detects if the current flows through the SR MOSFET and/or its body
diode. Basic turn−off detection threshold is 0 mV. A resistor in series with this pin can
decrease the turn off threshold if needed.
7
7
GND
Ground connection for the SR MOSFET driver and VCC decoupling capacitor. Ground
connection for minimum on and off time adjust resistors, LLD and trigger inputs.
GND pin should be wired directly to the SR MOSFET source terminal/soldering point
using Kelvin connection. DFN8 exposed flag should be connected to GND
8
8
DRV
Driver output for the SR MOSFET
−
5
MAX_TON
MIN_TON
Description
Supply voltage pin
Adjust the maximum on time period by connecting resistor to ground.
ELAPSED
ADJ
DISABLE
Minimum ON time
generator
EN
Disable detection
&
V DRV clamp
modulation
LLD
V_DRV
control
VDD
100mA
CS
CS_ON
CS
detection
DRIVER
CS_OFF
DRV Out
DRV
Control logic
CS_RESET
V DD
RESET
MIN_TOFF
ADJ
Minimum OFF
time generator
ELAPSED
DISABLE
EN
TRIG
TRIG/ DISABLE
Vtrig
Figure 5. Internal Circuit Architecture − NCP4305A, B, C, D
www.onsemi.com
4
VCC
DISABLE
Disable detection
10 A
VCC managment
UVLO
GND
NCP4305
ELAPSED
MIN_TON
ADJ
DISABLE
Minimum ON time
generator
EN
Disable detection
&
V DRV clamp
modulation
LLD
V_DRV
control
VDD
100mA
CS_ON
CS
CS
detection
DRV Out
DRIVER
DRV
CS_OFF
Control logic
CS_RESET
VDD
RESET
MIN_TOFF
ADJ
ELAPSED
Minimum OFF
time generator
EN
DISABLE
VCC managment
UVLO
VCC
ELAPSED
MAX_TON
ADJ
Maximum ON time
generator
GND
EN
Figure 6. Internal Circuit Architecture − NCP4305Q (CCM QR) with MAX_TON
ABSOLUTE MAXIMUM RATINGS
Rating
Supply Voltage
Symbol
Value
Unit
VCC
−0.3 to 37.0
V
VTRIG/DIS,
VMIN_TON,
VMIN_TOFF,
VMAX_TON, VLLD
−0.3 to VCC
V
Driver Output Voltage
VDRV
−0.3 to 17.0
V
Current Sense Input Voltage
VCS
−4 to 200
V
VCS_DYN
−10 to 200
V
IMIN_TON, IMIN_TOFF,
IMAX_TON, ILLD, ITRIG
−10 to 10
mA
RqJ−A_SOIC8
160
°C/W
TRIG/DIS, MIN_TON, MIN_TOFF, MAX_TON, LLD Input Voltage
Current Sense Dynamic Input Voltage (tPW = 200 ns)
MIN_TON, MIN_TOFF, MAX_TON, LLD, TRIG Input Current
Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, SOIC8
RqJ−A_DFN8
80
°C/W
RqJ−A_WDFN8
160
°C/W
Maximum Junction Temperature
TJMAX
150
°C
Storage Temperature
TSTG
−60 to 150
°C
ESD Capability, Human Body Model, Except Pin 6, per JESD22−A114E
ESDHBM
2000
V
ESD Capability, Human Body Model, Pin 6, per JESD22−A114E
ESDHBM
1000
V
ESD Capability, Machine Model, per JESD22−A115−A
ESDMM
200
V
ESD Capability, Charged Device Model, Except Pin 6, per JESD22−C101F
ESDCDM
750
V
ESD Capability, Charged Device Model, Pin 6, per JESD22−C101F
ESDCDM
250
V
Junction to Air Thermal Resistance, 1 oz 1
in2
Copper Area, DFN8
Junction to Air Thermal Resistance, 1 oz 1 in2 Copper Area, WDFN8
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device meets latch−up tests defined by JEDEC Standard JESD78D Class I.
www.onsemi.com
5
NCP4305
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Maximum Operating Input Voltage
Min
Max
Unit
35
V
125
°C
VCC
Operating Junction Temperature
TJ
−40
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
ELECTRICAL CHARACTERISTICS
−40°C ≤ TJ ≤ 125°C; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 kW; VTRIG/DIS = 0 V; VLLD = 0 V; VCS = −1 to +4 V; fCS =
100 kHz, DCCS = 50%, unless otherwise noted. Typical values are at TJ = +25°C
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
VCC rising
VCCON
8.3
8.8
9.4
V
VCC falling
VCCOFF
7.3
7.8
8.3
SUPPLY SECTION
VCC UVLO (ver. B & C)
VCC UVLO Hysteresis (ver. B & C)
VCC UVLO (ver. A, D & Q)
VCCHYS
1.0
V
VCC rising
VCCON
4.20
4.45
4.80
VCC falling
VCCOFF
3.70
3.95
4.20
VCC UVLO Hysteresis
(ver. A, D & Q)
VCCHYS
Start−up Delay
VCC rising from 0 to VCCON + 1 V @ tr = 10 ms
Current Consumption,
RMIN_TON = RMIN_TOFF = 0 kW
CLOAD = 0 nF, fSW = 500 kHz
0.5
V
V
75
125
ms
3.3
4.0
5.6
mA
B, D, Q
3.8
4.5
6.0
CLOAD = 0 nF, fSW = 500 kHz,
WDFN
A, C
3.0
4.0
5.6
B, D, Q
3.5
4.5
6.0
CLOAD = 1 nF, fSW = 500 kHz
A, C
4.5
6.0
7.5
B, D, Q
7.7
9.0
10.7
A, C
20
25
30
A, C
CLOAD = 10 nF, fSW = 500 kHz
tSTART_DEL
ICC
B, D, Q
Current Consumption
No switching, VCS = 0 V,
RMIN_TON = RMIN_TOFF = 0 k
ICC
Current Consumption below UVLO
No switching, VCC = VCCOFF – 0.1 V, VCS = 0 V
Current Consumption in Disable
Mode
VLLD = VCC − 0.1 V, VCS = 0 V
40
50
60
1.5
2.0
2.5
mA
75
125
mA
40
55
70
mA
45
65
80
40
55
ns
35
ns
ICC_UVLO
ICC_DIS
VTRIG = 5 V, VLLD = VCC – 3 V, VCS = 0 V
DRIVER OUTPUT
Output Voltage Rise−Time
CLOAD = 10 nF, 10% to 90% VDRVMAX
Output Voltage Fall−Time
CLOAD = 10 nF, 90% to 10% VDRVMAX
Driver Source Resistance
Driver Sink Resistance
Output Peak Source Current
Output Peak Sink Current
Maximum Driver Output Voltage
tr
tf
20
RDRV_SOURCE
1.2
W
RDRV_SINK
0.5
W
IDRV_SOURCE
4
A
IDRV_SINK
VCC = 35 V, CLOAD > 1 nF, VLLD = 0 V,
(ver. B, D and Q)
VDRVMAX
VCC = 35 V, CLOAD > 1 nF, VLLD = 0 V, (ver. A, C)
Minimum Driver Output Voltage
Minimum Driver Output Voltage
VCC = VCCOFF + 200 mV, VLLD = 0 V, (ver. B)
VDRVMIN
8
A
9.0
9.5
10.5
4.3
4.7
5.5
7.2
7.8
8.5
VCC = VCCOFF + 200 mV, VLLD = 0 V, (ver. C)
4.2
4.7
5.3
VCC = VCCOFF + 200 mV, VLLD = 0 V,
(ver. A, D, Q)
3.6
4.0
4.4
0.0
0.4
1.2
VLLD = VCC − VLLDREC V
VDRVLLDMIN
www.onsemi.com
6
V
V
V
NCP4305
ELECTRICAL CHARACTERISTICS
−40°C ≤ TJ ≤ 125°C; VCC = 12 V; CDRV = 0 nF; RMIN_TON = RMIN_TOFF = 10 kW; VTRIG/DIS = 0 V; VLLD = 0 V; VCS = −1 to +4 V; fCS =
100 kHz, DCCS = 50%, unless otherwise noted. Typical values are at TJ = +25°C
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
CS INPUT
Total Propagation Delay From CS
to DRV Output On
VCS goes down from 4 to −1 V, tf_CS = 5 ns
tPD_ON
35
60
ns
Total Propagation Delay From CS
to DRV Output Off
VCS goes up from −1 to 4 V, tr_CS = 5 ns
tPD_OFF
12
23
ns
CS Bias Current
VCS = −20 mV
Turn On CS Threshold Voltage
Turn Off CS Threshold Voltage
Guaranteed by Design
Turn Off Timer Reset Threshold
Voltage
CS Leakage Current
ICS
−105
−100
−95
mA
VTH_CS_ON
−120
−75
−40
mV
VTH_CS_OFF
−1
0
mV
VTH_CS_RESET
0.42
0.54
V
0.48
VCS = 200 V
ICS_LEAKAGE
0.4
mA
VTRIG = 5 V; Shorter pulses may not be
proceeded
tTRIG_PW_MIN
10
ns
2.02
2.18
V
7.5
12.5
ns
TRIGGER DISABLE INPUT
Minimum Trigger Pulse Duration
Trigger Threshold Voltage
VTRIG_TH
Trigger to DRV Propagation Delay
VTRIG goes from 0 to 5 V, tr_TRIG = 5 ns
Trigger Blank Time After DRV
Turn−on Event
VCS drops below VTH_CS_ON
Delay to Disable Mode
Disable Recovery Timer
tPD_TRIG
tTRIG_BLANK
35
50
65
ns
VTRIG = 5 V
tDIS_TIM
75
100
125
ms
VTRIG goes down from 5 to 0 V
tDIS_REC
5
8
13
ms
200
ns
16
mA
Minimum Pulse Duration to Disable VTRIG = 0 V; Shorter pulses may not be
Mode End
proceeded
Pull Down Current
1.87
VTRIG = 5 V
tDIS_END_MIN
ITRIG
9
13
MINIMUM tON and tOFF ADJUST
Minimum tON time
RMIN_TON = 0 W
tON_MIN
35
55
75
ns
Minimum tOFF time
RMIN_TOFF = 0 W
tOFF_MIN
190
245
290
ns
Minimum tON time
RMIN_TON = 10 kW
tON_MIN
0.92
1.00
1.08
ms
Minimum tOFF time
RMIN_TOFF = 10 kW
tOFF_MIN
0.92
1.00
1.08
ms
Minimum tON time
RMIN_TON = 50 kW
tON_MIN
4.62
5.00
5.38
ms
Minimum tOFF time
RMIN_TOFF = 50 kW
tOFF_MIN
4.62
5.00
5.38
ms
MAXIMUM tON ADJUST
Maximum tON Time
VMAX_TON = 3 V
tON_MAX
4.3
4.8
5.3
ms
Maximum tON Time
VMAX_TON = 0.3 V
tON_MAX
41
48
55
ms
Maximum tON Output Current
VMAX_TON = 0.3 V
IMAX_TON
−105
−100
−95
mA
LLD INPUT
Disable Threshold
VLLD_DIS = VCC − VLLD
VLLD_DIS
0.8
0.9
1.0
V
Recovery Threshold
VLLD_REC = VCC − VLLD
VLLD_REC
0.9
1.0
1.1
V
Disable Hysteresis
Disable Time Hysteresis
VLLD_DISH
Disable to Normal, Normal to Disable
Disable Recovery Time
Low Pass Filter Frequency
Driver Voltage Clamp Threshold
VDRV = VDRVMAX, VLLDMAX = VCC − VLLD
0.1
tLLD_DISH
V
ms
45
tLLD_DIS_REC
7.0
12.5
16.0
ms
fLPLLD
6
10
13
kHz
VLLDMAX
2.0
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
7
NCP4305
TYPICAL CHARACTERISTICS
4.7
9.3
4.6
9.1
VCCON
4.4
8.7
4.3
8.5
4.2
4.1
VCCOFF
4.0
VCCON
8.9
VCC (V)
VCC (V)
4.5
8.3
8.1
VCCOFF
7.9
3.9
7.7
3.8
7.5
7.3
−40 −20
3.7
−40 −20
0
20
40
60
TJ (°C)
80
100
120
Figure 7. VCCON and VCCOFF Levels,
ver. A, D, Q
0
20
40
60
TJ (°C)
80
100
Figure 8. VCCON and VCCOFF Levels,
ver. B, C
www.onsemi.com
8
120
NCP4305
TYPICAL CHARACTERISTICS
6
TJ = 55°C
TJ = 25°C
120
TJ = 85°C
TJ = 125°C
5
100
ICC_UVLO (mA)
ICC (mA)
4
TJ = 0°C
3
TJ = −20°C
TJ = −40°C
2
1
80
60
40
20
0
0
5
10
15
20
25
30
0
−40
35
−20
0
20
80
100
TJ (°C)
Figure 9. Current Consumption, CDRV = 0 nF,
fCS = 500 kHz, ver. D
Figure 10. Current Consumption, VCC =
VCCOFF − 0.1 V, VCS = 0 V, ver. D
120
60
CDRV = 10 nF
CDRV = 10 nF
25
50
20
40
ICC (mA)
ICC (mA)
60
VCC (V)
30
15
10
30
20
CDRV = 1 nF
5
CDRV = 1 nF
10
CDRV = 0 nF
CDRV = 0 nF
0
−40
−20
0
20
40
60
80
100
0
−40 −20
120
0
20
40
60
80
100
120
TJ (°C)
TJ (°C)
Figure 11. Current Consumption, VCC = 12 V,
VCS = −1 to 4 V, fCS = 500 kHz, ver. A
Figure 12. Current Consumption, VCC = 12 V,
VCS = −1 to 4 V, fCS = 500 kHz, ver. D
70
80
65
75
70
60
ICC_DIS (mA)
ICC_DIS (mA)
40
55
50
60
55
45
40
−40
65
50
−20
0
20
40
60
80
100
45
−40
120
−20
0
20
40
60
80
100
120
TJ (°C)
TJ (°C)
Figure 13. Current Consumption in Disable,
VCC = 12 V, VCS = 0 V, VLLD = VCC − 0.1 V
Figure 14. Current Consumption in Disable,
VCC = 12 V, VCS = 0 V, VLLD = VCC − 3 V, VTRIG =
5V
www.onsemi.com
9
NCP4305
TYPICAL CHARACTERISTICS
0
−90
−92
−0.2
−94
−0.4
−98
ICS (mA)
ICS (mA)
−96
−100
−102
−104
TJ = 125°C
TJ = 85°C
TJ = 55°C
TJ = 25°C
TJ = 0°C
TJ = −20°C
TJ = −40°C
−0.6
−0.8
−1.0
−106
−108
−110
−40
−1.2
−20
0
20
40
60
80
100
−1.4
−1.0 −0.8 −0.6 −0.4 −0.2
120
0.4
0.6
VCS (V)
Figure 15. CS Current, VCS = −20 mV
Figure 16. CS Current, VCC = 12 V
2.5
−50
VTH_CS_ON (mV)
−30
2.0
ICC (mA)
0.2
TJ (°C)
3.0
TJ = 125°C
TJ = 85°C
TJ = 55°C
TJ = 25°C
TJ = 0°C
TJ = −20°C
TJ = −40°C
1.5
1.0
0.5
0
−4
0
−3
−2
0.8 1.0
−70
−90
−110
−130
−1
0
1
2
3
−150
−40 −20
4
0
20
40
60
80
100
VCS (V)
TJ (°C)
Figure 17. Supply Current vs. CS Voltage,
VCC = 12 V
Figure 18. CS Turn−on Threshold
1.0
120
0.60
VTH_CS_RESET (V)
VTH_CS_OFF (mV)
0.5
0
−0.5
−1.0
0.55
0.50
0.45
−1.5
−2.0
−40
−20
0
20
40
60
80
100
0.40
−40
120
−20
0
20
40
60
80
TJ (°C)
TJ (°C)
Figure 19. CS Turn−off Threshold
Figure 20. CS Reset Threshold
www.onsemi.com
10
100
120
NCP4305
0.80
200
0.75
180
0.70
160
0.65
140
ICS_LEAKAGE (nA)
VTH_CS_RESET (V)
TYPICAL CHARACTERISTICS
0.60
0.55
0.50
0.45
100
80
60
0.40
40
0.35
0.30
20
0
−40
0
5
10
15
20
25
30
35
−20
0
20
40
60
80
100
VCC (V)
TJ (°C)
Figure 21. CS Reset Threshold
Figure 22. CS Leakage, VCS = 200 V
60
24
55
22
120
20
50
18
tPD_OFF (ns)
tPD_ON (ns)
120
45
40
35
16
14
12
10
30
8
25
6
20
−40
−20
0
20
40
60
80
100
4
−40
120
0
20
40
60
80
100
120
TJ (°C)
TJ (°C)
Figure 23. Propagation Delay from CS to DRV
Output On
Figure 24. Propagation Delay from CS to DRV
Output Off
2.5
2.15
2.13
2.4
2.11
2.3
2.09
2.2
VTRIG_TH (V)
VTRIG_TH (V)
−20
2.07
2.05
2.03
2.1
2.0
1.9
2.01
1.8
1.99
1.7
1.97
1.6
1.5
1.95
−40 −20
0
20
40
60
80
100
120
TJ = 125°C
TJ = 85°C
TJ = 55°C
TJ = 25°C
0
5
10
15
20
TJ = 0°C
TJ = −20°C
TJ = −40°C
25
TJ (°C)
VCC (V)
Figure 25. Trigger Threshold, VCC = 12 V
Figure 26. Trigger Threshold
www.onsemi.com
11
30
35
NCP4305
16
14
15
12
14
10
ITRIG (mA)
ITRIG (mA)
TYPICAL CHARACTERISTICS
13
12
4
10
2
TJ = 125°C
TJ = 85°C
TJ = 55°C
TJ = 25°C
TJ = 0°C
TJ = −20°C
TJ = −40°C
0
−20
0
20
40
60
80
100
0
120
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5 5.0
TJ (°C)
VTRIG (V)
Figure 27. Trigger Pull Down Current
Figure 28. Trigger Pull Down Current,
VCC = 12 V
14
115
12
110
10
105
tDIS_TIM (ms)
tPD_TRIG (ns)
6
11
9
−40
8
6
100
95
90
4
2
−40
−20
0
20
40
60
80
100
85
−40 −20
120
0
20
40
60
80
100
120
TJ (°C)
TJ (°C)
Figure 29. Propagation Delay from Trigger to
Driver Output Off
Figure 30. Delay to Disable Mode, VTRIG = 5 V
75
1.08
70
1.06
65
1.04
tMIN_TON (ms)
tMIN_TON (ns)
8
60
55
50
1.02
1.00
0.98
45
0.96
40
0.94
35
−40
−20
0
20
40
60
80
100
0.92
−40
120
−20
0
20
40
60
80
100
120
TJ (°C)
TJ (°C)
Figure 31. Minimum On−time RMIN_TON = 0 W
Figure 32. Minimum On−time RMIN_TON = 10 kW
www.onsemi.com
12
NCP4305
TYPICAL CHARACTERISTICS
5.4
290
5.3
280
270
tMIN_TOFF (ns)
tMIN_TON (ms)
5.2
5.1
5.0
4.9
240
230
210
4.7
4.6
−40
−20
0
20
40
60
80
100
200
190
−40
120
−20
0
20
40
60
80
100
120
TJ (°C)
TJ (°C)
Figure 33. Minimum On−time RMIN_TON = 50 kW
Figure 34. Minimum Off−time RMIN_TOFF = 0 W
1.08
5.4
1.06
5.3
1.04
5.2
tMIN_TOFF (ms)
tMIN_TOFF (ms)
250
220
4.8
1.02
1.00
0.98
5.1
5.0
4.9
0.96
4.8
0.94
4.7
0.92
−40
−20
0
20
40
60
80
100
4.6
−40
120
−20
0
20
40
60
80
100
TJ (°C)
TJ (°C)
Figure 35. Minimum Off−time RMIN_TOFF =
10 kW
Figure 36. Minimum Off−time RMIN_TOFF =
50 kW
1.04
1.08
1.03
1.06
1.02
1.04
tMIN_TOFF (ms)
tMIN_TON (ms)
260
1.01
1.00
0.98
120
1.02
1.00
0.98
0.96
0.96
0.94
0.94
092
0.92
0
5
10
15
20
25
30
0
35
5
10
15
20
25
30
VCC (V)
VCC (V)
Figure 37. Minimum On−time RMIN_TON = 10 kW
Figure 38. Minimum Off−time RMIN_TOFF =
10 kW
www.onsemi.com
13
35
NCP4305
TYPICAL CHARACTERISTICS
5.5
10.4
VCC = 12 V, CDRV = 0 nF
VCC = 12 V, CDRV = 1 nF
VCC = 12 V, CDRV = 10 nF
VCC = 35 V, CDRV = 0 nF
VCC = 35 V, CDRV = 1 nF
VCC = 35 V, CDRV = 10 nF
VDRV (V)
10.0
9.8
5.1
VDRV (V)
10.2
VCC = 12 V, CDRV = 0 nF
VCC = 12 V, CDRV = 1 nF
VCC = 12 V, CDRV = 10 nF
VCC = 35 V, CDRV = 0 nF
VCC = 35 V, CDRV = 1 nF
VCC = 35 V, CDRV = 10 nF
5.3
9.6
4.9
4.7
9.4
4.5
9.2
9.0
−40 −20
0
20
40
60
80
4.3
−40 −20
120
100
20
40
60
80
100
120
TJ (°C)
TJ (°C)
Figure 39. Driver and Output Voltage, ver. B, D
and Q
Figure 40. Driver Output Voltage, ver. A and C
50
5.3
TJ = 125°C
TJ = 85°C
TJ = 55°C
TJ = 25°C
45
40
TJ = 0°C
TJ = −20°C
TJ = −40°C
5.2
5.1
tMAX_TON (ms)
35
30
25
20
5.0
4.9
4.8
4.7
15
4.6
10
4.5
5
0
4.4
0
0.5
1.0
1.5
2.0
2.5
4.3
−40
3.0
−20
0
20
40
60
80
100
120
VMAX_TON (V)
TJ (°C)
Figure 41. Maximum On−time, ver. Q
Figure 42. Maximum On−time, VMAX_TON = 3 V,
ver. Q
55
53
51
tMAX_TON (ms)
tMAX_TON (ms)
0
49
47
45
43
41
−40
−20
0
20
40
60
80
100
TJ (°C)
Figure 43. Maximum On−time, VMAX_TON =
0.3 V, ver. Q
www.onsemi.com
14
120
NCP4305
APPLICATION INFORMATION
General description
forward). The time delay from trigger input to driver turn off
event is tPD_TRIG. Additionally, the trigger input can be used
to disable the IC and activate a low consumption standby
mode. This feature can be used to decrease standby
consumption of an SMPS. If the trigger input is not wanted
than the trigger pin can be tied to GND or an option can be
chosen to replace this pin with a MAX_TON input.
An output driver features capability to keep SR transistor
closed even when there is no supply voltage for NCP4305.
SR transistor drain voltage goes up and down during SMPS
operation and this is transferred through drain gate
capacitance to gate and may turn on transistor. NCP4305
uses this pulsing voltage at SR transistor gate (DRV pin) and
uses it internally to provide enough supply to activate
internal driver sink transistor. DRV voltage is pulled low
(not to zero) thanks to this feature and eliminate the risk of
turned on SR transistor before enough VCC is applied to
NCP4305.
Some IC versions include a MAX_TON circuit that helps
a quasi resonant (QR) controller to work in CCM mode
when a heavy load is present like in the example of a
printer’s motor starting up.
Finally, the NCP4305 features a special pin (LLD) that
can be used to reduce gate driver voltage clamp according
to application load conditions. This feature helps to reduce
issues with transition from disabled driver to full driver
output voltage and back. Disable state can be also activated
through this pin to decrease power consumption in no load
conditions. If the LLD feature is not wanted then the LLD
pin can be tied to GND.
The NCP4305 is designed to operate either as a standalone
IC or as a companion IC to a primary side controller to help
achieve efficient synchronous rectification in switch mode
power supplies. This controller features a high current gate
driver along with high−speed logic circuitry to provide
appropriately timed drive signals to a synchronous
rectification MOSFET. With its novel architecture, the
NCP4305 has enough versatility to keep the synchronous
rectification system efficient under any operating mode.
The NCP4305 works from an available voltage with range
from 4 V (A, D & Q options) or 8 V (B & C options) to 35 V
(typical). The wide VCC range allows direct connection to
the SMPS output voltage of most adapters such as
notebooks, cell phone chargers and LCD TV adapters.
Precise turn-off threshold of the current sense comparator
together with an accurate offset current source allows the
user to adjust for any required turn-off current threshold of
the SR MOSFET switch using a single resistor. Compared
to other SR controllers that provide turn-off thresholds in the
range of −10 mV to −5 mV, the NCP4305 offers a turn-off
threshold of 0 mV. When using a low RDS(on) SR (1 mW)
MOSFET our competition, with a −10 mV turn off, will turn
off with 10 A still flowing through the SR FET, while our
0 mV turn off turns off the FET at 0 A; significantly
reducing the turn-off current threshold and improving
efficiency. Many of the competitor parts maintain a drain
source voltage across the MOSFET causing the SR
MOSFET to operate in the linear region to reduce turn−off
time. Thanks to the 8 A sink current of the NCP4305
significantly reduces turn off time allowing for a minimal
drain source voltage to be utilized and efficiency
maximized.
To overcome false triggering issues after turn-on and
turn−off events, the NCP4305 provides adjustable minimum
on-time and off-time blanking periods. Blanking times can
be adjusted independently of IC VCC using external
resistors connected to GND. If needed, blanking periods can
be modulated using additional components.
An extremely fast turn−off comparator, implemented on
the current sense pin, allows for NCP4305 implementation
in CCM applications without any additional components or
external triggering.
An ultrafast trigger input offers the possibility to further
increase efficiency of synchronous rectification systems
operated in CCM mode (for example, CCM flyback or
Current Sense Input
Figure 44 shows the internal connection of the CS
circuitry on the current sense input. When the voltage on the
secondary winding of the SMPS reverses, the body diode of
M1 starts to conduct current and the voltage of M1’s drain
drops approximately to −1 V. The CS pin sources current of
100 mA that creates a voltage drop on the RSHIFT_CS resistor
(resistor is optional, we recommend shorting this resistor).
Once the voltage on the CS pin is lower than VTH_CS_ON
threshold, M1 is turned−on. Because of parasitic
impedances, significant ringing can occur in the application.
To overcome false sudden turn−off due to mentioned
ringing, the minimum conduction time of the SR MOSFET
is activated. Minimum conduction time can be adjusted
using the RMIN_TON resistor.
www.onsemi.com
15
NCP4305
Figure 44. Current Sensing Circuitry Functionality
Figure 45). Therefore the turn−off current depends on
MOSFET RDSON. The −0.5 mV threshold provides an
optimum switching period usage while keeping enough time
margin for the gate turn-off. The RSHIFT_CS resistor
provides the designer with the possibility to modify
(increase) the actual turn−on and turn−off secondary current
thresholds. To ensure proper switching, the min_tOFF timer
is reset, when the VDS of the MOSFET rings and falls down
past the VTH_CS_RESET. The minimum off−time needs to
expire before another drive pulse can be initiated. Minimum
off−time timer is started again when VDS rises above
VTH_CS_RESET.
The SR MOSFET is turned-off as soon as the voltage on
the CS pin is higher than VTH_CS_OFF (typically −0.5 mV
minus any voltage dropped on the optional RSHIFT_CS). For
the same ringing reason, a minimum off-time timer is
asserted once the VCS goes above VTH_CS_RESET. The
minimum off-time can be externally adjusted using
RMIN_TOFF resistor. The minimum off−time generator can
be re−triggered by MIN_TOFF reset comparator if some
spurious ringing occurs on the CS input after SR MOSFET
turn−off event. This feature significantly simplifies SR
system implementation in flyback converters.
In an LLC converter the SR MOSFET M1 channel
conducts while secondary side current is decreasing (refer to
www.onsemi.com
16
NCP4305
VDS = VCS
ISEC
V TH_CS _RESET – (RSHIFT _CS*ICS )
VTH_CS_OFF – (RSHIFT _CS*ICS )
VTH_CS _ON – (RSHIFT _CS*ICS )
VDRV
Turn−on delay
Turn −off delay
Min ON−time
tMIN_TON
Min t OFF timer was
stopped here because
of VCS 10 mH. Proper safety insulation
between primary and secondary sides can be easily assured
by using triple insulated wire for one or, better, both
windings.
This
primary
triggering
technique
provides
approximately 0.5% efficiency improvement when the
application is operated in deep CCM and transformer with
leakage of 1% of primary inductance is used.
It is also possible to use capacitive coupling (use
additional capacitor with safety insulation) between the
Minimum tON and tOFF Adjustment
The NCP4305 offers an adjustable minimum on−time and
off−time blanking periods that ease the implementation of a
synchronous rectification system in any SMPS topology.
These timers avoid false triggering on the CS input after the
MOSFET is turned on or off.
The adjustment of minimum tON and tOFF periods are
done based on an internal timing capacitance and external
resistors connected to the GND pin − refer to Figure 68 for
a better understanding.
Figure 68. Internal Connection of the MIN_TON Generator (the MIN_TOFF Works in the Same Way)
Current through the MIN_TON adjust resistor can be
calculated as:
I R_MIN_TON +
V ref
R Ton_min
The internal capacitor size would be too large if
IR_MIN_TON was used. The internal current mirror uses a
proportional current, given by the internal current mirror
ratio. One can then calculate the MIN_TON and
MIN_TOFF blanking periods using below equations:
(eq. 5)
If the internal current mirror creates the same current
through RMIN_TON as used the internal timing capacitor (Ct)
charging, then the minimum on−time duration can be
calculated using this equation.
t MIN_TON + C t
V ref
I R_MIN_TON
+ Ct
V ref
Vref
t MIN_TON + 1.00 * 10 −4 * R MIN_TON [ms]
(eq. 7)
t MIN_TOFF + 1.00 * 10 −4 * R MIN_TOFF [ms]
(eq. 8)
Note that the internal timing comparator delay affects the
accuracy of Equations 7 and 8 when MIN_TON/
MIN_TOFF times are selected near to their minimum
possible values. Please refer to Figures 69 and 70 for
measured minimum on and off time charts.
(eq. 6)
+ C t @ R MIN_TON
RMIN_TON
www.onsemi.com
37
NCP4305
10
The absolute minimum tON duration is internally clamped
to 55 ns and minimum tOFF duration to 245 ns in order to
prevent any potential issues with the MIN_TON and/or
MIN_TOFF pins being shorted to GND.
The NCP4305 features dedicated anti−ringing protection
system that is implemented with a MIN_TOFF blank
generator. The minimum off−time one−shot generator is
restarted in the case when the CS pin voltage crosses
VTH_CS_RESET threshold and MIN_TOFF period is active.
The total off-time blanking period is prolonged due to the
ringing in the application (refer to Figure 45).
Some applications may require adaptive minimum on and
off time blanking periods. With NCP4305 it is possible to
modulate blanking periods by using an external NPN
transistor − refer to Figure 71. The modulation signal can be
derived based on the load current, feedback regulator
voltage or other application parameter.
9
8
tMIN_TON (ms)
7
6
5
4
3
2
1
0
0
10
20
30
40
50
60
70
80
90 100
RMIN_TON (kW)
Figure 69. MIN_TON Adjust Characteristics
10
9
tMIN_TOFF (ms)
8
7
6
5
4
3
2
1
0
0
10
20
30
40
50
60
70
80
90 100
RMIN_TOFF (kW)
Figure 70. MIN_TOFF Adjust Characteristics
Figure 71. Possible Connection for MIN_TON and MIN_TOFF Modulation
www.onsemi.com
38
NCP4305
Maximum tON adjustment
The Internal connection of the MAX_TON feature is
shown in Figure 72. Figure 72 shows a method that allows
for a modification of the maximum on−time according to
output voltage. At a lower VOUT, caused by hard overload
or at startup, the maximum on−time should be longer than at
nominal voltage. Resistor RA can be used to modulate
maximum on−time according to VOUT or any other
parameter.
The operational waveforms at heavy load in QR type
SMPS are shown in Figure 73. After tMAX_TON time is
exceeded, the synchronous switch is turned off and the
secondary current is conducted by the diode. Information
about turned off SR MOSFET is transferred by the DRV pin
through a small pulse transformer to the primary side where
it acts on the ZCD detection circuit to allow the primary
switch to be turned on. Secondary side current disappears
before the primary switch is turned on without a possibility
of cross current condition.
The NCP4305Q offers an adjustable maximum on−time
(like the min_tON and min_tOFF settings shown above) that
can be very useful for QR controllers at high loads. Under
high load conditions the QR controller can operate in CCM
thanks to this feature. The NCP4305Q version has the ability
to turn−off the DRV signal to the SR MOSFET before the
secondary side current reaches zero. The DRV signal from
the NCP4305Q can be fed to the primary side through a
pulse transformer (see Figure 4 for detail) to a transistor on
the primary side to emulate a ZCD event before an actual
ZCD event occurs. This feature helps to keep the minimum
switching frequency up so that there is better energy transfer
through the transformer (a smaller transformer core can be
used). Also another advantage is that the IC controls the SR
MOSFET and turns off from secondary side before the
primary side is turned on in CCM to ensure no cross
conduction. By controlling the SR MOSFET’s turn off
before the primary side turn off, producing a zero cross
conduction operation, this will improve efficiency.
Figure 72. Internal Connection of the MAX_TON Generator, NCP4305Q
www.onsemi.com
39
NCP4305
VDS = VCS
ISEC
V TH_CS _RESET – (RSHIFT _CS*ICS )
VTH_CS_OFF – (RSHIFT _CS*ICS )
VTH_CS _ON – (RSHIFT _CS*ICS )
Primary virtual ZCD
detection delay
V DRV
Turn−on delay
Turn −off delay
Min ON−time
t MIN _TON
Min OFF−time
tMIN _TOFF
Max ON−time
tMAX _TON
t
The tMIN _TON and tMIN _TOFF are adjustable by R MIN _TON and R MIN _TOFF resistors, t MAX_TON is adjustable by R MAX_TON
Figure 73. Function of MAX_TON Generator in Heavy Load Condition
Adaptive Gate Driver Clamp and automatic Light Load
Turn−off
and drop at MOSFET’s RDS(on) only improves stability
during load transients.
2nd − In extremely low load conditions or no load
conditions the NCP4305 fully disables driver output and
reduces the internal power consumption when output load
drops below the level where skip−mode takes place.
Both features are controlled by voltage at LLD pin. The
LLD pin voltage characteristic is shown in Figure 74. Driver
voltage clamp is a linear function of the voltage difference
between the VCC and LLD pins from VLLD_REC point up to
VLLD_MAX. A disable mode is available, where the IC
current consumption is dramatically reduced, when the
difference of VCC − VLLD voltage drops below VLLD_DIS.
When the voltage difference between the VCC − VLLD pins
increase above VLLC_REC the disable mode ends and the IC
regains normal operation. It should be noted that there are
also some time delays to enter and exit from the disable
mode. Time waveforms are shown at Figure 75. There is a
time, tLLD_DISH, that the logic ignores changes from disable
mode to normal or reversely. There is also some time
tLLD_DIS_R that is needed after an exit from the disable mode
to assure proper internal block biasing before SR controller
starts work normally.
As synchronous rectification system significantly
improves efficiency in most of SMPS applications during
medium or full load conditions. However, as the load
reduces into light or no−load conditions the SR MOSFET
driving losses and SR controller consumption become more
critical. The NCP4305 offers two key features that help to
optimize application efficiency under light load and no load
conditions:
1st − The driver clamp voltage is modulated and follows
the output load condition. When the output load decreases
the driver clamp voltage decreases as well. Under heavy
load conditions the SR MOSFET’s gate needs to be driven
very hard to optimize the performance and reduce
conduction losses. During light load conditions it is not as
critical to drive the SR MOSFET’s channel into such a low
RDSON state. This adaptive gate clamp technique helps to
optimize efficiency during light load conditions especially
in LLC applications where the SR MOSFETs with high
input capacitance are used.
Driver voltage modulation improves the system behavior
when SR controller state is changed in and out of normal or
disable modes. Soft transient between drop at body diode
www.onsemi.com
40
NCP4305
VDRVCLAMP
ICC
VDRVMAX
VLLD_DIS VLLD_REC
VCC −VLLD
VLLD_MAX
Figure 74. LLD Voltage to Driver Clamp and Current Consumption Characteristic (DRV Unloaded)
VCC−VLLD
tLLD_DISH
tLLD_DISH
tLLD_DISH
tLLD_DISH
VLLD_REC
DISABLE MODE
NORMAL
DISABLE MODE
tLLD_DIS_R
tLLD_DIS_R
NORMAL
ICC
NORMAL
VLLD_DIS
t
Figure 75. LLD Pin Disable Behavior in Time Domain
through R3 and capacitors C2 and C3, the load level can be
sensed. Output voltage of this detector on the LLD pin is
referenced to controller VCC with an internal differential
amplifier in NCP4305. The output of the differential
amplifier is then used in two places. First the output is used
in the driver block for gate drive clamp voltage adjustment.
Next, the output signal is evaluated by a no−load detection
comparator that activates IC disable mode in case the load
is disconnected from the application output.
The two main SMPS applications that are using
synchronous rectification systems today are flyback and
LLC topologies. Different light load detection techniques
are used in NCP4305 controller to reflect differences in
operation of both mentioned applications.
Detail of the light load detection implementation
technique used in NCP4305 in flyback topologies is
displayed at Figure 76. Using a simple and cost effective
peak detector implemented with a diode D1, resistors R1
www.onsemi.com
41
NCP4305
Figure 76. NCP4305 Light Load and No Load Detection Principle in Flyback Topologies
directly reduces DRV clamp voltage down from its
maximum level. The DRV is then fully disabled when IC
enters disable mode. The IC exits from disable mode when
difference between LLD voltage and VCC increases over
VLLD_REC. Resistors R2 and R3 are also used for voltage
level adjustment and with capacitor C3 form low pass filter
that filters relatively high speed ripple at C2. This low pass
filter also reduces speed of state change of the SR controller
from normal to disable mode or reversely. Time constant
should be higher than feedback loop time constant to keep
whole system stable.
Operational waveforms related to the flyback LLD
circuitry are provided in Figure 77. The SR MOSFET drain
voltage drops to ~ 0 V when ISEC current is flowing. When
the SR MOSFET is conducting the capacitor C2 charges−up,
causing the difference between the LLD pin and VCC pin to
increase, and drop the LLD pin voltage. As the load
decreases the secondary side currents flows for a shorter a
shorter time. C2 has less time to accumulate charge and the
voltage on the C2 decreases, because it is discharged by R2
and R3. This smaller voltage on C2 will cause the LLD pin
voltage to increase towards VCC and the difference between
LLD and VCC will go to zero. The output voltage then
ISEC
VC2
VC3
VLLD_REC
VLLDMAX
VLLD_DIS
VDRV
VDRVMAX
IC enters
disable mode
t
Figure 77. NCP4305 Driver Clamp Modulation Waveforms in Flyback Application Entering into Light/No Load
Condition
www.onsemi.com
42
NCP4305
IOUT
VCC−VLLD
VLLD_REC
VLLDMAX
VLLD_DIS
VDRVMAX
IC enters
disable mode
VDRV
t
Figure 78. NCP4305 Driver Clamp Modulation Circuitry Transfer Characteristic in Flyback Application
The technique used for LLD detection in LLC is similar
to the LLD detection method used in a flyback with the
exception the D1 and D2 OR−ing diodes are used to measure
the total duty cycle to see if it is operating in skip mode.
Figure 79. NCP4305 Light Load Detection in LLC Topology
The driver clamp modulation waveforms of NCP4305 in
LLC are provided in Figure 80. The driver clamp voltage
clips to its maximum level when LLC operates in normal
mode. When the LLC starts to operate in skip mode the
driver clamp voltage begins to decrease. The specific output
current level is determined by skip duty cycle and detection
circuit consists of R1, R2, R3, C2, C3 and diodes D1, D2.
The NCP4305 enters disable mode in low load condition,
when VCC−VLLD drops below VLLD_DIS (0.9 V). Disable
mode ends when this voltage increase above VLLD_REC
(1.0 V) Figure 81 shows how LLD voltage modulates the
driver output voltage clamp.
www.onsemi.com
43
NCP4305
Normal operation
Skip operation
VCS 1
VCS 2
VC2
V LLDMAX
V CC −V LLD
(V C3)
V LLD_REC
V LLD_DIS
V DRVMAX
DRV clamp
IC enters
disable mode
t
Figure 80. NCP4305 Driver Clamp Modulation Waveforms in LLC Application
www.onsemi.com
44
NCP4305
VCC−VLLD
IC enters
disable mode
VLLDMAX
VLLD_REC
VLLD_DIS
VDRVMAX
DRV clamp
IOUT
t
Figure 81. NCP4305 Driver Clamp Modulation Circuitry Characteristic in LLC Application
behavior is shown in Figure 46. Operation waveforms for
this option are provided in Figure 83. Capacitor C2 is
charged to maximum voltage when LLC is switching. When
there is no switching in skip, capacitor C2 is discharged by
R2 and when LLD voltage referenced to VCC falls below
VLLD_DIS IC enters disable mode. Disable mode is ended
when LLC starts switching.
There exist some LLC applications where behavior
described above is not the best choice. These applications
transfer significant portion of energy in a few first pulses in
skip burst. It is good to keep SR fully working during skip
mode to improve efficiency. There can be still saved some
energy using LLD function by activation disable mode
between skip bursts. Simplified schematic for this LLD
Figure 82. NCP4305 Light Load Detection in LLC Application − Other Option
www.onsemi.com
45
NCP4305
Normal operation
Skip operation
VCS1
VCS2
VC2
VLLDMAX
VCC−VLLD
VLLD_DIS
DRV clamp
VLLD_REC
IC enters
disable mode
VDRVMAX
t
Figure 83. NCP4305 Light Load Detection Behavior in LLC Application – Other Option
Power Dissipation Calculation
significantly. Therefore, the MOSFET switch always
operates under Zero Voltage Switching (ZVS) conditions
when in a synchronous rectification system.
The following steps show how to approximately calculate
the power dissipation and DIE temperature of the NCP4305
controller. Note that real results can vary due to the effects
of the PCB layout on the thermal resistance.
It is important to consider the power dissipation in the
MOSFET driver of a SR system. If no external gate resistor
is used and the internal gate resistance of the MOSFET is
very low, nearly all energy losses related to gate charge are
dissipated in the driver. Thus it is necessary to check the SR
driver power losses in the target application to avoid over
temperature and to optimize efficiency.
In SR systems the body diode of the SR MOSFET starts
conducting before SR MOSFET is turned−on, because there
is some delay from VTH_CS_ON detect to turn−on the driver.
On the other hand, the SR MOSFET turn off process always
starts before the drain to source voltage rises up
Step 1 − MOSFET Gate−to Source Capacitance:
During ZVS operation the gate to drain capacitance does
not have a Miller effect like in hard switching systems
because the drain to source voltage does not change (or its
change is negligible).
www.onsemi.com
46
NCP4305
it will need to be measured. Please note that the input
capacitance is not linear (as shown Figure 84) and it needs
to be characterized for a given gate voltage clamp level.
Step 2 − Gate Drive Losses Calculation:
Gate drive losses are affected by the gate driver clamp
voltage. Gate driver clamp voltage selection depends on the
type of MOSFET used (threshold voltage versus channel
resistance). The total power losses (driving loses and
conduction losses) should be considered when selecting the
gate driver clamp voltage. Most of today’s MOSFETs for SR
systems feature low RDS(on) for 5 V VGS voltage. The
NCP4305 offers both a 5 V gate clamp and a 10 V gate
clamp for those MOSFET that require higher gate to source
voltage.
The total driving loss can be calculated using the selected
gate driver clamp voltage and the input capacitance of the
MOSFET:
P DRV_total + V CC @ V CLAMP @ C g_ZVS @ f SW (eq. 9)
Where:
VCC
VCLAMP
Cg_ZVS
C iss + C gs ) C gd
is the NCP4305 supply voltage
is the driver clamp voltage
is the gate to source capacitance of the
MOSFET in ZVS mode
fsw
is the switching frequency of the target
application
The total driving power loss won’t only be dissipated in
the IC, but also in external resistances like the external gate
resistor (if used) and the MOSFET internal gate resistance
(Figure 50). Because NCP4305 features a clamped driver,
it’s high side portion can be modeled as a regular driver
switch with equivalent resistance and a series voltage
source. The low side driver switch resistance does not drop
immediately at turn−off, thus it is necessary to use an
equivalent value (RDRV_SIN_EQ) for calculations. This
method simplifies power losses calculations and still
provides acceptable accuracy. Internal driver power
dissipation can then be calculated using Equation 10:
C rss + C gd
C oss + C ds ) C gd
Figure 84. Typical MOSFET Capacitances
Dependency on VDS and VGS Voltages
Therefore, the input capacitance of a MOSFET operating
in ZVS mode is given by the parallel combination of the gate
to source and gate to drain capacitances (i.e. Ciss capacitance
for given gate to source voltage). The total gate charge,
Qg_total, of most MOSFETs on the market is defined for hard
switching conditions. In order to accurately calculate the
driving losses in a SR system, it is necessary to determine the
gate charge of the MOSFET for operation specifically in a
ZVS system. Some manufacturers define this parameter as
Qg_ZVS. Unfortunately, most datasheets do not provide this
data. If the Ciss (or Qg_ZVS) parameter is not available then
www.onsemi.com
47
NCP4305
Figure 85. Equivalent Schematic of Gate Drive Circuitry
P DRV_IC +
1
@ C g_ZVS @ V CLAMP 2 @ f SW @
2
ǒ
R DRV_SINK_EQ
Ǔ
R DRV_SINK_EQ ) R G_EXT ) R g_int
1
) @ C g_ZVS @ V CLAMP 2 @ f SW @
2
ǒ
R DRV_SOURCE_EQ
) C g_ZVS @ V CLAMP @ f SW @ ǒV CC * V CLAMPǓ
Ǔ
(eq. 10)
R DRV_SOURCE_EQ ) R G_EXT ) R g_int
Step 4 − IC Die Temperature Arise Calculation:
Where:
RDRV_SINK_EQ
The die temperature can be calculated now that the total
internal power losses have been determined (driver losses
plus internal IC consumption losses). The package thermal
resistance is specified in the maximum ratings table for a
35 mm thin copper layer with no extra copper plates on any
pin (i.e. just 0.5 mm trace to each pin with standard soldering
points are used).
The DIE temperature is calculated as:
is the NCP4305x driver low side switch
equivalent resistance (0.5 W)
RDRV_SOURCE_EQ is the NCP4305x driver high side switch
equivalent resistance (1.2 W)
is the external gate resistor (if used)
RG_EXT
Rg_int
is the internal gate resistance of the
MOSFET
Step 3 − IC Consumption Calculation:
T DIE + ǒP DRV_IC ) P CCǓ @ R qJ−A ) T A
In this step, power dissipation related to the internal IC
consumption is calculated. This power loss is given by the
ICC current and the IC supply voltage. The ICC current
depends on switching frequency and also on the selected min
tON and tOFF periods because there is current flowing out
from the min tON and tOFF pins. The most accurate method
for calculating these losses is to measure the ICC current
when CDRV = 0 nF and the IC is switching at the target
frequency with given MIN_TON and MIN_TOFF adjust
resistors. IC consumption losses can be calculated as:
P CC + V CC @ I CC
Where:
PDRV_IC
PCC
RqJA
TA
(eq. 11)
www.onsemi.com
48
(eq. 12)
is the IC driver internal power dissipation
is the IC control internal power
dissipation
is the thermal resistance from junction to
ambient
is the ambient temperature
NCP4305
PRODUCT OPTIONS
OPN
Package
UVLO [V]
DRV clamp [V]
Pin 5 function
NCP4305ADR2G
SOIC8
4.5
4.7
TRIG
NCP4305AMTTWG
WDFN8
4.5
4.7
TRIG
NCP4305DDR2G
SOIC8
4.5
9.5
TRIG
NCP4305DMNTWG
DFN8
4.5
9.5
TRIG
NCP4305DMTTWG
WDFN8
4.5
9.5
TRIG
NCP4305QDR2G
SOIC8
4.5
9.5
MAX_TON
Usage
LLC, CCM flyback, DCM flyback, forward,
QR, QR with primary side CCM control
QR with forced CCM from secondary side
ORDERING INFORMATION
Device
NCP4305ADR2G
Package
Package marking
Packing
Shipping†
SOIC8
NCP4305A
SOIC−8
(Pb−Free)
2500 /Tape & Reel
WDFN−8
(Pb−Free)
3000 /Tape & Reel
DFN−8
(Pb−Free)
4000 /Tape & Reel
NCP4305DDR2G
NCP4305D
NCP4305QDR2G
NCP4305AMTTWG
NCP4305Q
WDFN8
NCP4305DMTTWG
NCP4305DMNTWG
5A
5D
DFN8
4305D
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
49
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN8, 4x4
CASE 488AF−01
ISSUE C
1
SCALE 2:1
A
B
D
PIN ONE
REFERENCE
2X
0.15 C
2X
0.15 C
0.10 C
8X
ÉÉ
ÉÉ
ÉÉ
0.08 C
DETAIL A
E
OPTIONAL
CONSTRUCTIONS
EXPOSED Cu
DETAIL B
ÇÇÇÇ
(A3)
A
A1
C
D2
ÇÇÇÇ
e
8X
SEATING
PLANE
ÉÉÉ
ÉÉÉ
ÇÇÇ
A3
A1
ALTERNATE
CONSTRUCTIONS
8X
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.25
0.35
4.00 BSC
1.91
2.21
4.00 BSC
2.09
2.39
0.80 BSC
0.20
−−−
0.30
0.50
−−−
0.15
XXXXXX
XXXXXX
ALYWG
G
E2
5
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
GENERIC
MARKING DIAGRAM*
L
4
ÇÇÇÇ
8
MOLD CMPD
DETAIL B
SIDE VIEW
K
ÇÇÇ
ÇÇÇ
ÉÉÉ
TOP VIEW
1
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. DETAILS A AND B SHOW OPTIONAL CONSTRUCTIONS FOR TERMINALS.
L
L
L1
NOTE 4
DETAIL A
DATE 15 JAN 2009
b
XXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.10 C A B
0.05 C
NOTE 3
BOTTOM VIEW
SOLDERING FOOTPRINT*
2.21
8X
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
0.63
4.30 2.39
PACKAGE
OUTLINE
8X
0.35
0.80
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON15232D
DFN8, 4X4, 0.8P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511AT−01
ISSUE O
DATE 26 FEB 2010
SCALE 4:1
D
PIN ONE
REFERENCE
2X
0.10 C
2X
ALTERNATE TERMINAL
CONSTRUCTIONS
EXPOSED Cu
e/2
MOLD CMPD
DETAIL B
A
A1
A3
SIDE VIEW
DIM
A
A1
A3
b
D
E
e
L
L1
L2
ÉÉÉ
ÉÉÉ
TOP VIEW
DETAIL B
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
DETAIL A
E
0.05 C
8X
L
L1
ÍÍ
ÍÍ
ÍÍ
0.10 C
L
A
B
ALTERNATE
CONSTRUCTIONS
C
GENERIC
MARKING DIAGRAM*
SEATING
PLANE
1
DETAIL A
e
1
7X
4
L
5
8X
BOTTOM VIEW
b
0.10 C A
0.05 C
XXMG
G
XX = Specific Device Code
M = Date Code
G
= Pb−Free Device
(Note: Microdot may be in either location)
L2
8
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
2.00 BSC
0.50 BSC
0.40
0.60
--0.15
0.50
0.70
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
B
RECOMMENDED
SOLDERING FOOTPRINT*
NOTE 3
7X
PACKAGE
OUTLINE
0.78
2.30
0.88
1
8X
0.30
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON48654E
WDFN8, 2X2, 0.5 P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
onsemi Website: www.onsemi.com
◊
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative
工商网监
湘ICP备2023018690号
