NCP45491XMNTWG

NCP45491 26V, 4-Channel Voltage Bus and 4-Channel High-Side Current Shunt Monitor The NCP45491 is a high−performance monolithic IC which can be used to monitor bus voltage and current on four high−voltage power supplies simultaneously. The HV bus voltages and currents are translated to a low−voltage power domain and multiplexed onto a single differential output for measurement externally by common ADCs. The device is configurable to operate either standalone or as a pair, permitting up to eight separate HV power supplies to be monitored and measured. www.onsemi.com 1 QFN32 4x4 CASE 485CD MARKING DIAGRAM Features • • • • • • • • • Translates and Scales Shunt and Bus Voltages up to 26 V Single Device Monitors Four Supplies May Be Paired for Monitoring Up To Eight Supplies Very Low Powerdown Current All Channels Individually Gain Programmable by External Resistor Selection Fast Settling Time Real−Time Indication of All Bus Voltages Valid Adjustable Output Common−Mode Voltage Adapts to Most External ADCs Lead−Free Device 45491 ALYWG CCCCC 45491 = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package CCCCC = Country of Assembly PIN CONFIGURATION Applications Computers/Notebooks Graphical Cards Power Management/Power Control Loops Battery Chargers RSHUNT VBUS to load ` R3 SH_IN_N1 SH_IN_P1 BS_IN1 SH_IN_N2 SH_IN_P2 BS_IN2 SH_O2 NC R1 SH_IN_P1 BS_IN1 SH_IN_N1 Channel 1 (of4) MUX_SEL Sequence Logic R4 1 2 3 4 5 6 7 8 MODE_SEL SH_O1 from Channel 2 R2 from Channel 3 GND_FET Multiplexer Single-ended to Diff Amp 33: GND 24 23 22 21 20 19 18 17 BS_REF BG_REF_OUT CM_REF_IN NC DIFF_OUT_P DIFF_OUT_N NC SH_O4 GND_FET SH_O3 BS_IN3 SH_IN_P3 SH_IN_N3 BS_IN4 SH_IN_P4 SH_IN_N4 • • • • DIFF_OUT_P (Top View) DIFF_OUT_N from Channel 4 ORDERING INFORMATION ENABLE BS_OK SKIP VREF Generator BS_REF BG_REF_OUT R5 R6 R7 Figure 1. Block Diagram © Semiconductor Components Industries, LLC, 2018 December, 2018 − Rev. 5 CM_REF_IN Package Shipping† NCP45491XMNTWG QFN32 (Pb−Free) 4000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ` R8 Device ` 1 Publication Order Number: NCP45491/D NCP45491 Table 1. PIN DESCRIPTION Pin Name I/O Function 2, 5, 12, 15 SH_IN_Px AI Shunt Resistor Sense +, High Voltage 1, 4, 13, 16 SH_IN_Nx AI Shunt Resistor Sense −, High Voltage 32, 7, 10, 17 SH_Ox AO Shunt Voltage Gain Set / Filter, Current Output 3, 6, 11, 14 BS_INx AI Bus Voltage Sense, High Impedance Input 20 DIFF_OUT_P AO Differential Output, Positive 19 DIFF_OUT_N AO Differential Output, Negative 22 CM_REF_IN AI Common−Mode Reference for Differential Output 29 MUX_SEL DI Multiplexer Select Input 24 BS_REF AI Bus OK Reference Input 30 BS_OK DO Bus OK output (open−drain; high impedance = BUS OK) 28 ENABLE DI Device Enable. When low, places device in low−power state 23 BG_REF_OUT AO Buffered Bandgap Voltage Output 9 GND_FET AO Low−side GND ref for resistor dividers (open drain type) 25 SKIP DI Skip Function control (see description) 26 MODE_SEL AI Multi−level Input for single−device, device A, or device B modes 8, 18, 21,31 NC 27 VCC PWR Device Power PAD GND GND Device Ground Pins must be floated Table 2. MAXIMUM RATINGS Rating Supply Voltage Range Shunt Input Voltage Range Bus Input Voltage Range Grounding FET Range Shunt Output Voltage Range Pins Condition Symbol Value Unit VCC GND = 0 V VCC −0.3 to 5.5 V SH_IN_Px, SH_IN_Nx GND = 0 V VSH_IN_X −0.3 to 30 V BS_INx GND = 0 V VBS_IN −0.3 to 30 V GND_FET GND = 0 V VGND_FET −0.3 to 30 V SH_Ox GND = 0 V VSH_Ox −0.3 to 5.5 V Digital Input Voltage Range MUX_SEL, ENABLE, SKIP, MODE_SEL GND = 0 V VEN −0.3 to 5.5 V Low Voltage I/O Range BS_REF, CM_REF_IN, MODE_SEL, DIFF_OUT_P, DIFF_OUT_N, BS_OK, BG_REF_OUT GND = 0 V VLV −0.3 to 5.5 V Thermal Resistance, Junction−to−Air RqJA 40 °C/W Thermal Resistance, Junction−to−Case (VIN Paddle) RqJC 5 °C/W Operating Temperature Range TA1 −40 to 105 °C Functional Temperature Range TA2 −40 to 125 °C Maximum Junction Temperature TJ 125 °C Storage Temperature Range TSTG −40 to 150 °C Lead Temperature, Soldering (10 sec.) TSLD 260 °C Moisture Sensitivity Level MSL 1 − Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2 NCP45491 Table 3. ESD RATINGS Rating Symbol Value Unit ESD Capability, Human Body Model (Note 1) ESDHBM >2.0 kV ESD Capability, Charged Device Model (Note 1) ESDCDM >0.5 kV ILU 100 mA Latch−up Immunity (Note 1) 1. Tested by the following methods @ TA = 25°C: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114). ESD Charged Device Model per JESD22−C101. Latch−up testing per JEDEC78E. Table 4. RECOMMENDED OPERATING RANGES Rating Supply Voltage Range Shunt Input Voltage Range Symbol Min Max Unit VCC 2.8 3.8 V VSH_IN_X 5 26 V Shunt Output Voltage Range (operating) VSH_Ox 0 0.5 V Shunt Output Voltage Range (floating) VSH_Ox 2.8 3.8 V Bus Input Pin Voltage Range (Standby Mode) VBS_INX 0 26 V Bus Input Pin Voltage Range (Full Function or Limited Function Mode) VBS_INX 0 0.5 V Grounding FET Range VGND_FET 0 26 V Low Voltage I/O Range VLV 0 3.8 V Ambient Temperature TA −40 85 °C Junction Temperature TJ −40 125 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Table 5. AC CHARACTERISTICS (VSH_IN_X = 15 V, VEN = 0 V, VCC = 3.3 V, unless indicated otherwise. Min and Max values are valid for temperature range −40°C ≤ TJ ≤ +105°C unless noted otherwise and are guaranteed by test, design, characterization, or statistical correlation. Typical values are referenced to TJ = 25°C) Parameter Symbol Min Typ Max Unit Multiplexer Settling Time (to 9.375 mV) TSTAB1 100 ns Multiplexer Settling Time (to 3.125 mV) TSTAB2 300 ns 11 ms MUX_SEL Period (normal operation) MUX_SEL Reset Period Power−up Time (STANDBY or Limited Function to Full Function) Differential Amplifier Capacitive Load Capability (Note 2) TMSP 0.185 TRP 35 ms TPWR_UP 40 ms CDIFF 82 pF 2. Differential Output CLOAD (i.e.: DIFF_OUT_x to GND) appears as a series RC with lumped equivalent R (0.86−8.6 W) and C (8.2−82 pF). www.onsemi.com 3 NCP45491 Table 6. DC CHARACTERISTICS (VSH_IN_X = 15 V, VEN = 0 V, VCC = 3.3 V, unless indicated otherwise. Min and Max values are valid for temperature range −40°C ≤ TJ ≤ +105°C unless noted otherwise and are guaranteed by test, design, characterization, or statistical correlation. Typical values are referenced to TJ = 25°C) Symbol Min MUX_SEL, SKIP, MODE_SEL, ENABLE Logic High VIH 1.4 MUX_SEL, SKIP, MODE_SEL, ENABLE Logic Low VIL Parameter Input Impedance (MODE_SEL, ENABLE pins) RFLOAT SH_O Pin Current Source Capability Typ Max Unit V 0.4 100k V W ISH_O_MAX 5 mA Fixed Current for Detection of SH_Ox Open ISH_LEAK 1 mA GND_FET ON Resistance (measured @ 1 mA) RGND_FET BG_REF_OUT Voltage 10 W 1.326 V IVBG_OUT 100 mA RBS_OK 300 W VBG BG_REF_OUT Load BS_OK Logic Low Impedance VCC range for BS_OK low impedance 1.274 1.3 VLI 1 3.8 V VCC Threshold Reference for BS_OK Input (POR) (Note 3) VBS_TH 2.6 2.8 V Shunt Monitor Offset Voltage (Note 4) VSM_OV ±150 mV Shunt Monitor Offset Voltage Drift (Note 4) SM_VD 2 mV/°C Shunt Monitor CMRR (VSH_IN_Px in valid range, see above) (Note 5) Valid SH_O resistance SM_CMRR 80 dB RSH_O 2000 W Differential Amp Input Offset Voltage, room temperature (Note 6) VD_OVRT ±2 mV Differential Amp Input Offset Voltage Drift, −40°C to +105°C (Note 6) VD_OVT ±6 mV 885 mV Differential Amp PSRR (VCC = 2.8 V to 3.8 V) DA_PSRR 60 Differential Amp Common−Mode Voltage VCM 565 dB Differential Amp Closed Loop Gain GDA Differential Full Scale Output VFSO 800 mVpp I_VCC (Fully Functional, VEN = 0, VCC must be 2.8 V − 3.8 V) IVCC_F 1.5 mA I_VCC (Limited Function, VEN = Tri−state, VCC must be 2.8 V − 3.8 V) IVCC_L 400 mA I_VCC (STANDBY) (Note 7) IVCC_S 180 mA I_SHO (STANDBY, non−floated SH_Ox pin) (Note 7) ISHO_S 100 mA I_SH_IN_N (VBUS current in Full Function) (Note 8) IVBUS 300 mA 2 V/V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Vcc detection for BS_OK must trip in this range. Device can be either operational or not operational in this range. 4. Shunt Monitor Offset Voltage and Offset Voltage Drift are referred to the SH_IN_Px and SH_IN_Nx pins. 5. Input Offset voltage at TJ = 25°C. 6. Differential Amplifier Offset Voltage and Offset Voltage Drift are referred to the multiplexer input pins (e.g. BS_INx or SH_Ox). 7. VEN = VCC; Total VCC standby current is IVCC_S plus an additional ISHO_S for every SH_Ox channel that is not floating. 8. Specifications for VBUS current draw are only applicable when VCC = 2.8 V to 3.8 V. www.onsemi.com 4 NCP45491 APPLICATIONS INFORMATION Differential Output Amplifier R4 R3 ) R4 A differential output amplifier provides a scaled representation of multiple bus voltages and currents to an external device on the DIFF_OUT_P and DIFF_OUT_N pins. These voltages and currents are presented sequentially (under control of the Sequence Logic block) via the Multiplexer. The common−mode voltage of the differential output amplifier is established by the voltage on the CM_REF_IN pin. The multiplier selection is controlled by a single digital input (MUX_SEL pin). The device will monitor this pin and cycle through the different measured parameters in a fixed sequence. The sequence will repeat cycle as shown in the tables until either a timeout condition is detected or the device is disabled. The MUX_SEL pin needs to be pulsed at least once before normal MUX_SEL cycles begin. The delay between the falling edge of the last initial MUX_SEL pulse and the first rising edge of the normal MUX_SEL cycle needs to be 14.75 ms > Td > 24.25 ms. The differential voltage across an external shunt resistor (RSHUNT) is converted to a current by a transconductor stage implemented by an op−amp and external resistor R1. This current is supplied to the SH_Ox pin where it is converted back to a ground−referenced voltage by external resistor R2. The conversion gain from differential voltage across the shunt resistor to that ground−referred voltage on SH_Ox may then be set directly as the ratio of RSHUNT to R1. A capacitor may be connected across R2 in order to provide noise filtering if required in the application. Note that bias current for the op−amp is taken from the “load” side of the shunt resistor so that it is included in the load current measurement. Operating Modes There are two operating modes – stand−alone (one to four channels) and paired operation (up to eight channels). In paired operation, MODE_SEL is used to designate a “Device A” and “Device B” of a pair. When paired, the differential output amplifiers of the two devices are expected to be “wire−or’ed” together, and the table logic insures that only one device will actively drive DIFF_OUT_P and DIFF_OUT_N at any given time. See description in the Auxiliary Functions section for details. Additionally, devices can be configured to operate with a reduced channel count. See description in the Auxiliary Functions section for details. Current Shunt Resistors The external resistors labeled RSHUNT, R1, and R2 in Figure 1 are used to define the full dynamic range of the shunt current monitoring and are user application dependent. Resistors RSHUNT and R1 are chosen based on the maximum load current (ILOAD) to define the SH_Ox current (ISH_Ox) using the equation; R SHUNT I R 1 LOAD Power−up Sequence VBUS voltages must be applied before VCC. VCC must be applied (2.8 V − 3.8 V) for expected operation and current consumption. The enable signal must be held low while the VCC supply comes up. After both VBUS and VCC supplies are present, EN can then be pulled high or floated if standby mode or limited function mode is desired. Refer to auxiliary functions section for more information. (eq. 1) ISH_Ox is also user defined and is not to exceed ISH_O_MAX. Ideally, the SH_Ox current is around 2 mA. The resistance of R2 is found with the relationship; R2 + V SH_Ox I SH_Ox (eq. 3) Multiplexer Select Current Shunt Monitor (one of four identical instances) I SH_Ox + V BUS + V BS_INx (eq. 2) Regardless of the values of ILOAD or ISH_Ox, the maximum voltage of the SH_Ox pin shall not exceed VSH_Ox, indicated in the operating range table. Bus Voltage Monitor (one of four identical instances) An external voltage divider is used to scale the voltage on the BS_INx pin to an appropriate full−scale range for the differential output amplifier. Resistors R3 and R4 form a resistor divider to define the full dynamic range of the bus voltage monitor with; www.onsemi.com 5 NCP45491 Four−Channel Stand−Alone Operation MUX_SEL Cycle Differential Amp Output Standby Hi−Z 1 Channel 1 Bus Voltage 2 Channel 1 Shunt Current 3 Channel 2 Bus Voltage 4 Channel 2 Shunt Current 5 Channel 3 Bus Voltage 6 Channel 3 Shunt Current 7 Channel 4 Bus Voltage 8 Channel 4 Shunt Current 9³1 Channel 1 Bus Voltage 10³2 Channel 1 Shunt Current Repeat cycle until reset or timeout …. MUX_SEL Cycle Standby 1 2 3 4 5 6 7 8 9 10 11 12 13³1 14³2 …. www.onsemi.com 6 Six−Channel Paired Operation Differential Amp Differential Amp Output (Device A) Output (Device B) Hi−Z Hi−Z Ch 1 Bus Voltage Hi−Z Ch 1 Shunt Current Hi−Z Ch 2 Bus Voltage Hi−Z Ch 2 Shunt Current Hi−Z Ch 3 Bus Voltage Hi−Z Ch 3 Shunt Current Hi−Z Hi−Z Ch 1 Bus Voltage Hi−Z Ch 1 Shunt Current Hi−Z Ch 2 Bus Voltage Hi−Z Ch 2 Shunt Current Hi−Z Ch 3 Bus Voltage Hi−Z Ch 3 Shunt Current Ch 1 Bus Voltage Hi−Z Ch 1 Shunt Current Hi−Z Repeat cycle until reRepeat cycle until reset or timeout set or timeout NCP45491 APPLICATIONS DIAGRAMS +3.3V 100kΩ VBUS EN MODE_SEL MUX_SEL SH_IN_Nx VCC To Load Pull to 3.3V or 0V to set SKIP logic SKIP SH_IN_Px BS_OK BS_INx DIFF_OUT_P Differential to ADC NCP45491 DIFF_OUT_N CM_REF_IN GND BS_REF SH_Ox BG_REF_OUT GND_FET Figure 2. Stand Alone Device Operation Power-Up Time 14.75us < Td < 24.29us MUX_SEL Ch 1 BV Diff. Out Ch 1 SC Ch 2 BV Ch 2 SC Ch 3 BV EN MODE_SEL Hi-Z Hi-Z VCC Figure 3. Stand Alone Timing Characteristics www.onsemi.com 7 Ch 3 SC Ch 4 BV Ch 4 SC Ch 1 BV Ch 1 SC VBUS To Load www.onsemi.com 8 GND SH_Ox GND_FET BS_INx SH_IN_Px VCC SH_IN_Nx 0V MODE_SEL BG_REF_OUT MUX_SEL NCP45491 Device A 100kΩ EN DIFF_OUT_N DIFF_OUT_P BS_OK SKIP Differential to ADC Pull to 3.3V or 0V to set SKIP logic EN DIFF_OUT_N DIFF_OUT_P BS_OK SKIP MUX_SEL NCP45491 Device B +3.3V +3.3V MODE_SEL BS_REF VCC BS_REF +3.3V GND SH_Ox GND_FET BS_INx SH_IN_Px SH_IN_Nx To Load VBUS NCP45491 Figure 4. Six−Channel Paired Device Operation BG_REF_OUT CM_REF_IN CM_REF_IN NCP45491 Power-Up Time 14.75us < Td < 24.29us MUX_SEL (tied) Diff. Out (Device A) Diff. Out (Device B) ADC Input (tied Diff. Outs) Hi-Z Ch 1 BV Ch 1 SC Ch 2 BV Ch 2 SC Ch 3 BV Ch 3 SC Hi-Z Ch 4 BV Ch 4 SC Ch 5 BV Ch 5 SC Ch 6 BV Ch 6 SC Ch 1 BV Ch 1 SC Hi-Z Ch 1 BV Ch 1 SC Ch 2 BV Ch 2 SC Ch 3 BV Ch 3 SC Ch 4 BV Ch 4 SC Ch 5 BV Ch 5 SC Ch 6 BV Ch 6 SC Ch 1 BV Ch 1 SC EN (tied) MODE_SEL (Device A) MODE_SEL (Device B) VCC (tied) Figure 5. Six−Channel Paired Device Timing Characteristics www.onsemi.com 9 NCP45491 AUXILIARY FUNCTIONS Bus Comparator (BS_OK) Connecting the SH_IN_Px and SH_IN_Nx pins for unused channels to the respective SH_IN_Px and SH_IN_Nx of previous active channels is an acceptable way to provide the bias voltages needed. If the SH_Ox pin is left floating, then that channel and all subsequent channels will be skipped in the DIFF_OUT readout. For example, if SH_O3 is left floating, SH_O3 and SH_O4 will be bypassed. If devices are in paired mode, the number of unused channels on both devices must be matched. However, bus voltage on those unused channels (as measured on the BS_INx pins) will still be compared to the BS_REF voltage and included in the BS_OK output logic. If SKIP = 0 V, then the BS_INx voltages are ignored. In this case the unused BS_INx pins can be tied to any voltage less than VCC. A real−time indication that VCC and all bus voltages (as measured on the BS_INx pins) are valid is provided on the BS_OK pin. BS_OK remains low until all used BS_INx pins are above a user−defined threshold voltage. The threshold voltage for the valid condition of BS_INx pins is set by the voltage provided to the BS_REF pin and must be less than 0.2 V. This can be done via an external resistor divider and the bandgap reference. If desired, the user can use the SKIP pin to modify the logic as shown in the corresponding table (H=high, L=low, Z=tristate, X=don’t care). The SKIP pin can also be used to hold BS_OK = L in the absence of VCC. Reset/Timeout Normal operation can be interrupted and device returned to standby mode by holding the MUX_SEL pin HIGH or LOW longer than the reset period TRP. EN X X H Z/L Z/L Z/L Bandgap Reference The BG_REF_OUT pin provides a high−accuracy voltage from which BS_REF and CM_REF_IN voltages can be supplied via external voltage dividers. Ground FET The GND_FET pin is a switch that connects the bus voltage dividers to ground. In order that these voltage dividers not consume current when not needed (as in device shutdown), a low−impedance open−drain FET disconnects the low−side of these resistor dividers when the EN pin is at a logic HIGH level. Level LOW Tri−state (floating) Enable Function HIGH The EN pin controls device operation according to the corresponding table. The MODE_SEL pin controls multiplexer operation according to the corresponding table. Note that MODE_SEL is left floating in stand−alone operation. Reduced Channel Count If an application requires less than 4 channels, then pins for unused channels must be connected in the following manner for correct operation of the BS_OK output. Connection BS_INx Connect to BS_IN pin of previous channel SH_Ox Float SH_IN_Px Connect to VCC voltage or higher SH_IN_Nx Connect to VCC voltage or higher Note: “x” refers to the unused channel number www.onsemi.com 10 SKIP Logic BS_INx X X X L H X SKIP H X X H H L BS_OK L L L L H (open drain) H (open drain) EN Logic Device Operation Fully Functional Limited Function: BG_REF_OUT is valid, GND_FET is turned ON, BS_OK comparators and output are functional. All other functions to be disabled. DIFF_OUT to be Hi−Z and multiplexer select logic is held in reset. Standby: As described in Limited Function above with GND_FET turned OFF Level LOW Tri−state (floating) HIGH Mode Select Function PINS for Unused Channels VCC Z(unpowered) L (POR) X H H H MODE_SEL Logic Multiplexer Operation Device A Stand−Alone Device B NCP45491 LAYOUT GUIDELINES Ground: A solid connection to the back ground pad of the NCP45491 to a ground plane will help to reduce noise, in addition to the decoupling capacitor. Using the ground plane to shield sensitive analog signals is good practice. Differential Output: To achieve a low noise result, the DIFF_OUT_P and the DIFF_OUT_N should be routed close together with matched lengths. Shielding these lines with GND will provide additional protection from noise. Minimizing the distance traveled by the differential output pair to get to the digitizing ADC is also a good way to avoid additional noise. The DIFF_OUT_x signals should not be routed in close proximity to other digital signals in the system application. Routing of Digital Signals: MUX_SEL, MODE_SEL, SKIP, and ENABLE should be routed to avoid direct coupling with any of the analog input and output signals of the NCP45491. In most applications, these digital signals are static and are of lesser concern. References: Connections to BS_REF, BG_REF_OUT, and CM_REF_IN should be kept close to the NCP45491 for best noise performance. Thermal Layout Considerations: As the load current does not flow through the NCP45491, thermal dissipation is of minimal concern. Connecting the GND pad on the back of the part to a ground plane is ample. Selection of R1, R2, R3, R4, and Rshunt may require higher power ratings above the 0.1W standard for small SMD passives. Electrical Layout Considerations Correct physical layout is important for proper low noise accurate operation of the NCP45491. Power Paths: Use wide and short traces for bus voltage source to load path to reduce parasitic resistance and loss of power through the primary current path. The load current (traveling from source to load through Rshunt) does not pass through the NCP45491, but careful consideration of this path is critical. Power Supply Decoupling: A decoupling capacitor of 0.1 mF from VCC to ground is recommended. Keep capacitor as close to the NCP45491 VCC pin as possible, with a direct connection to the GND pad. Rshunt layout: A correct 4−wire Kelvin connection to the Rshunt resistor (also commonly known as the Rsense resistor) is critical to achieving accurate bus current and voltage measurements. The Rshunt resistor should have a low tolerance specification with adequate power ratings depending on the application. Any shared traces between the force and sense connections to the Rshunt resistor will result in additional un−accounted for resistance in the mW that will add error to the bus current and voltage measurements. The figure below demonstrates correct Rshunt connection. Correct layout: To VBUS To Load Rsense To SH_IN* through R 1 To SH_IN_N* Incorrect layout: To VBUS To Load Rsense To SH _IN* through R 1 To SH _IN_N* www.onsemi.com 11 NCP45491 PACKAGE DIMENSIONS QFN32 4x4, 0.4P CASE 485CD ISSUE A B A D ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ L1 DETAIL A E ALTERNATE TERMINAL CONSTRUCTIONS EXPOSED Cu TOP VIEW A 0.05 C MOLD CMPD DETAIL B ALTERNATE CONSTRUCTION A3 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.15 0.25 4.00 BSC 2.60 2.80 4.00 BSC 2.60 2.80 0.40 BSC 0.30 REF 0.45 REF 0.25 0.45 −−− 0.15 DIM A A1 A3 b D D2 E E2 e K K2 L L1 ÉÉ ÉÉ 0.10 C 0.10 C L L PIN ONE REFERENCE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 0.05 C DETAIL B NOTE 4 A1 SIDE VIEW SEATING PLANE C RECOMMENDED MOUNTING FOOTPRINT 0.10 C A B DETAIL A D2 9 K 4X 17 32X 4.30 2.80 K2 PACKAGE OUTLINE L 32X 0.58 1 DETAIL C CORNER LEAD CONSTRUCTION E2 2.80 1 DETAIL C 4.30 0.10 C A B 25 e 32X BOTTOM VIEW b 0.07 M C A B 0.05 M C 8X C0.08 0.40 PITCH NOTE 3 32X 0.25 DIMENSIONS: MILLIMETERS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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