NCP4672DR2G

NCP4672 Linear Voltage Regulator Dual, Vin and Vout Voltage Detector The NCP4672 is a dual linear voltage regulator with input voltage and output voltage detectors. This part is useful in systems where multiple voltages are required such as for core and I/O. The NCP4672 is very accurate at 2% over full input voltage and full load current. The NCP4672 eliminates the need for external voltage supervision due to the two built in voltage detectors. The voltage detector on the input is set to 7.0 V. The output voltage detector is for channel 1 and is set to 2.9 V. An external capacitor is used to set the duration of this reset signal. Other features include short circuit protection and thermal shutdown protection. The NCP4672 has been designed to work with a 4.7 mF output capacitor having an ESR between 0.1 W and 5.0 W. Features • • • • • • • MARKING DIAGRAM 8 SOIC−8 NB SUFFIX CASE 751 8 1 4672 A L Y W G Accuracy: 2% at Full Voltage and Load Excellent Ripple Rejection: 70 dB @ 1 kHz Voltage Detector for Input Voltage Voltage Detector for Output Voltage Programmable Delay of Reset Signal Thermal Short Circuit Protection This is a Pb−Free Device 1 4672 ALYW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONFIGURATION Typical Application • • • • http://onsemi.com Small Core and I/O Power Consumer Equipment Measurement Equipment Industrial Equipment Vin Rst 1 8 Vout1 Vout Rst 2 7 GND1 CD 3 6 GND2 Vin 4 5 Vout2 (Top View) Vin RST Vin ORDERING INFORMATION 10 KW Vin Rst Vout1 Vout1 Cout2 4.7 mF Vout Rst GND1 10 nF Vin CD GND2 Vin Vout2 Cin 0.1 mF Vout2 Device Package NCP4672DR2G SOIC−8 (Pb−Free) Shipping† 2500 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Cout2 4.7 mF Figure 1. Typical Application Circuit © Semiconductor Components Industries, LLC, 2006 October, 2019 − Rev. 4 1 Publication Order Number: NCP4672/D NCP4672 MAXIMUM RATINGS Rating Input Voltage Symbol Value Unit Vinmax −0.3 ~ 18 V Vout −0.3 to Vin + 0.3 V Iout1max Iout2max 30 80 mA mA − Infinite − PD RqJA Internally Limited W °C/W °C/W °C/W Output Voltage Output Current 1 Output Current 2 Output Short Circuit Duration Power Dissipation and Thermal Characteristics − SOIC−8 Power Dissipation Thermal Resistance, Junction−to−Ambient Minimum Pad Size 200 mm2 Pad Size (Note 1) Thermal Resistance, Junction−to−Case RqJC 190 160 25 Operating Junction Temperature Range Tstg −40 to 125 °C Tsolder −55 to 150 °C Storage Temperature Range Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Refer to Figure 4 for more information. PIN DESCRIPTION Pin Number Symbol 1 Vin RST Open−collector, active−low output of the input voltage detector with hysteresis. Threshold levels are typical 7.0 V/ 7.35 V at VCC pin. 2 Vo RST Active−low output of the reset generator. Reset generator is based on sensing of the Vout1 voltage. Sensing is with hysteresis − threshold levels are typically 2.9 V/ 2.95 V at Vout1. Reset is generated at rising edge of the Vout1 and it’s duration is set by external capacitor connected to CD pin. 3 CD Programmable delay of the reset generator. Delay is adjusted by inserting a capacitor between CD and GND (typically 10 ms for 10 nF capacitor). 4 VCC Supply Voltage 5 Vout2 1.8 V/ 80 mA LDO Regulator Output 6 GND2 Ground for Vout2 (internally connected with GND1) 7 GND1 Ground for Vout1 (internally connected with GND2) 8 Vout1 3.5 V/30 mA LDO Regulator Output Description RECOMMENDED CONDITIONS (TA = 25°C, Cin = 0.1 mF Ceramic, Cout = 4.7 mF) Characteristics Symbol Min Typ Max Unit Input Voltage Vin 3.8 12 16 V Output Current (where Vout remains within accuracy) Iout1 Iout2 0 0 − − 20 70 mA http://onsemi.com 2 NCP4672 Vin Vout1 2.9 V − + 7.0 V VIn RST + − Vref − + Vref Vref + − Vo RST CD Vref Thermal Shutdown Vout2 − + Vref Thermal Shutdown GND1 GND2 Figure 1. http://onsemi.com 3 NCP4672 ELECTRICAL CHARACTERISTICS (Cin = 0.1 mF Ceramic, Cout = 4.7 mF with ESR = 0.1 − 5.0 W, Vin = 12 V, TA = 25°C) Characteristics Symbol Output Voltage Vout1 (Vin = 4.5 V, Iout1 = 20 mA) Vout2 (Vin = 4.5 V, Iout2 = 40 mA) Vadj Line Regulation Vout1 (Vin = 4.5 V , Iout1 = 20 mA) Vout2 (Vin = 4.5 V to 10 V, Iout2 = 40 mA) Regline Load Regulation Vout1 (Vin = 4.5 V, Iout1 = 0.1 mA to 20 mA) Vout2 (Vin = 4.5 V, Iout2 = 0.1 mA to 70 mA) Regload Dropout Voltage Vout1 (Vin = 3.3 V, Iout1 = 20 mA) Vin − Vout1 Ground Pin Current (Vin = 8.0 V, Iout1 = Iout2 = 0 mA) (Vin = 2.7 V, Iout1 = Iout2 = 0 mA, Rpu = infinite) IGND Short Current Limit Vout1 Vout2 ISC Thermal Shutdown Temperature Coefficient Vout1 (TJ = −30 to 85°C, Vin = 4.5 V, Iout1 = 20 mA) Vout2 (TJ = −30 to 85°C, Vin = 4.5 V, Iout2 = 40 mA) TC Ripple Rejection (Note 6) Vout1 (Vin = 4.5 V, Vripple = 1.0 V, Iout1 = 20 mA, 120 Hz) Vout2 (Vin = 4.5 V, Vripple = 1.0 V, Iout2 = 40 mA, 120 Hz) RR Output Noise Voltage Vout1 (Vin = 4.5 V, f = 20 Hz − 80 kHz, Iout1 = 20 mA) Vout2 (Vin = 4.5 V, f = 20 Hz − 80 kHz, Iout2 = 40 mA) Vn Min Typ Max 3.43 1.764 3.5 1.8 3.57 1.836 − − 3.0 3.0 30 30 − − 3.0 2.0 40 40 − 150 300 − − 1.0 3.0 2.0 − 30 80 60 150 − − − 165 − − − 100 100 − − − − 65 70 − − − − 80 50 − − Unit V mV mV mV mA mA °C ppm/°C dB mVrms Vin Detect Detecting Voltage L (Vin = H to L) VSLin 6.72 7.0 7.28 V Detecting Voltage H (Vin = L to H) VSHin − 7.35 − V Hysteresis Voltage (Vin = H to L to H) D VSin 140 350 560 mV VSlin TC − 100 − ppm/°C VOLin1 VOLin2 − − 100 − 200 0.4 mV V Detecting Voltage L (Vin = H to L) VSLout 2.78 2.9 3.020 V Detecting Voltage H (Vin = L to H) VSHout − 2.95 − V Hysteresis Voltage (Vin = H to L to H) D VSout 25 50 100 mV VSLin Temperature Coefficient (TJ = −30°C to +85°C) VSLin TC − 100 − ppm/°C Low−Level Output Voltage (Vout1 = 2.6 V) Threshold Operating Voltage (VOPLout = 0.85 V) VOLout1 VOLout2 − − 100 − 200 0.4 mV V Reset Delay Time (CD = 10 nF) tPLH 5 10 15 ms “L” Transmission Delay Time (CD = 10 nF) tPHL − 30 90 ms VSLin Temperature Coefficient (TJ = −30°C to +85°C) Low−Level Output Voltage (Vin = 6.0 V, Vt1 = 5.0 V, Rt1 = 10 kW) (Note 5) Threshold Operating Voltage (VOPLin = Vt1 = 1.0 V) Vout Detect 2. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL−STD−883, Method 3015 Machine Model Method 200 V. T * TA 3. The maximum package power dissipation is: PD + J(max) RqJA 4. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 5. Refer to Figure 3. 6. Guaranteed by design. http://onsemi.com 4 NCP4672 VSHin DVSin VSLin VOPLin* Vi (Pin4) VOPLin* Vin RST (Pin1) VSLout DVSout VSHout Vout1 (Pin8) VOPLout* VOPLout* Vo RST (Pin2) tPLH tPHL tPLH *; VOPLout shows theoretical on this chart. VOPLout spec. must be specified on Pin 2 voltage (0.4 V) *; VOPLin shows theoretical on this chart. VOPLin spec. must be specified on Pin 1 voltage (0.4 V) Figure 2. Dual Regulator Timing Vin RST 1 Vin 4 VOPLin = 1.0 Vtyp 10 kW VOLin = 0.4 V + − + − GND1 7.0 V 7 Figure 3. Threshold Operating Voltage VOPLin Under Condition VOLin = 0.4 V http://onsemi.com 5 Vt1 Vtyp = 5.0 V Vmax = 16 V NCP4672 Rq JA , THERMAL RESISTANCE JUNCTION−TO−AIR (° C/W) 200.0 180.0 160.0 140.0 120.0 100.0 80.0 0 200 100 300 400 COPPER AREA 1 oz 500 600 (mm2) 4.0 1.4 3.5 Vout, OUTPUT VOLTAGE (V) 1.6 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 Vout1 2.5 Vout2 2.0 1.5 1.0 0.5 0 16 14 3.0 0 20 40 60 80 100 120 Vin, INPUT VOLTAGE (V) Iout, OUTPUT CURRENT (mA) Figure 5. Quiescent Current versus Input Voltage Figure 6. Peak Current Limit 1000 DELAY TIME (ms) IQ, QUIESCENT CURRENT (mA) Figure 4. SOP−8 Thermal Resistance versus P.C.B. Copper Area 100 10 1 0.001 0.01 0.1 CD, CAPACITANCE (mF) Figure 7. Delay Time versus Capacitance http://onsemi.com 6 1 140 160 NCP4672 4 10 RPU = 10 kW 3 6 VOLTAGE VOLTAGE 8 Vin 4 10 15 20 25 30 35 0 40 70 60 50 40 Vin = 12 V Vout1 = 3.5 V Iout1 = 10 mA Cout1 = 4.7 mF 10 8 10 12 16 14 0.1 1 10 40 30 Vin = 12 V Vout2 = 1.8 V Iout2 = 10 mA Cout2 = 4.7 mF 20 0.01 0.1 1 10 FREQUENCY (kHz) FREQUENCY (kHz) Figure 10. Vout1 Ripple Rejection Figure 11. Vout2 Ripple Rejection http://onsemi.com 7 20 50 0 100 18 60 10 0.01 6 Figure 9. Vo and Vo RST versus Time 70 0 4 Figure 8. Vin and Vin RST versus Time 80 20 2 TIME (ms) 80 30 0 TIME (ms) RIPPLE REJECTION (dB) RIPPLE REJECTION (dB) 5 2 1 2 0 Vo RST CD = 10 nF Vin RST 0 Vo 100 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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