NCP4894

NCP4894 1.8 Watt Differential Audio Power Amplifier with Selectable Shutdown The NCP4894 is a differential audio power amplifier designed for portable communication device applications. This feature and the excellent audio characteristics of the NCP4894 are a guarantee of a high quality sound, for example, in mobile phones applications. With a 10% THD+N value the NCP4894 is capable of delivering 1.8 W of continuous average power to an 8.0 W load from a 5.5 V power supply. With the same load conditions and a 5.0 V battery voltage, it ensures 1.0 W to be delivered with less than 0.01% distortion. The NCP4894 provides high quality audio while requiring few external components and minimal power consumption. It features a low−power consumption shutdown mode. To be flexible, shutdown may be enabled by either a logic high or low depending on the voltage applied on the SD MODE pin. The NCP4894 contains circuitry to prevent from “pop and click” noise that would otherwise occur during turn−on and turn−off transitions. For maximum flexibility, the NCP4894 provides an externally controlled gain (with resistors), as well as an externally controlled turn−on time (with bypass capacitor). Due to its excellent PSRR, it can be directly connected to the battery, saving the use of an LDO. This device is available in 9−Pin Flip−Chip, Micro−10 and DFN10 3x3 mm packages. Features http://onsemi.com MARKING DIAGRAMS 9−PIN FLIP−CHIP FC SUFFIX CASE 499AL A3 1 xxx G AYWW C1 A1 8 1 Micro−10 DM SUFFIX CASE 846B xxxx AYWG G DFN10 MN SUFFIX CASE 485C 1 1 xxx ALYWG G • • • • • • • • • • • Differential Amplification Shutdown High or Low Selectivity 1.0 W to an 8.0 W Load from a 5.0 V Power Supply Superior PSRR: Direct Connection to the Battery “Pop and Click” Noise Protection Circuit Ultra Low Current Shutdown Mode 2.2 V−5.5 V Operation External Gain Configuration Capability External Turn−on Configuration Capability Thermal Overload Protection Circuitry Pb−Free Packages are Available xxxx = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W, WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. Typical Applications • Portable Electronic Devices • PDAs • Mobile Phones © Semiconductor Components Industries, LLC, 2005 1 November, 2005 − Rev. 8 Publication Order Number: NCP4894/D NCP4894 Rf1 20 kW VP Cs Ci1 Negative Diff Input from DAC Ri1 VP BYPASS VP BYPASS Cb SHUTDOWN CONTROL SD MODE 0 0 1 1 SD SELECT 0 1 0 1 Ci2 Status Shutdown On On Shutdown Ri2 SD SELECT SHUTDOWN CONTROL SD MODE INP BYPASS VM + − OUTB 1 mF VMC BRIDGE RL 8W − + OUTA 1 mF INM 390 nF 20 kW Positive Diff Input from DAC 390 nF 20 kW 20 kW Rf2 Figure 1. Typical NCP4894 Application Circuit with Differential Input http://onsemi.com 2 NCP4894 PIN CONNECTIONS 9−Pin Flip−Chip A1 INP B1 VP C1 INM A2 BYPASS B2 SD MODE C2 A3 OUTB B3 VM C3 (Top View) SD SELECT OUTA (Top View) BYPASS 5 (Top View) 6 OUTB SD SELECT INM SD MODE INP BYPASS 1 2 3 4 5 10 OUTA 9 8 7 6 VP NC VM OUTB Micro−10 SD SELECT 1 INM SD MODE INP 2 3 4 DFN10 10 OUTA 9 VP 8 NC 7 VM PIN DESCRIPTION 9−Pin Flip−Chip A1 A2 A3 B1 B2 B3 C1 C2 C3 Micro−10/DFN10 4 5 6 9 3 7 2 1 10 Type I O I I I I I O I Symbol INP BYPASS OUTB VP SD MODE VM INM SD SELECT OUTA Positive Differential Input Bypass Capacitor Pin which Provides the Common Mode Voltage Negative BTL Output Positive Analog Supply of the Cell Shutdown High or Low Selectivity (Note 1) Ground Negative Differential Input (Note 1) Positive BTL Output Description 1. The SD SELECT pin must be toggled to the same state as the SD MODE pin to force the device in shutdown mode. http://onsemi.com 3 NCP4894 MAXIMUM RATINGS (Note 2) Rating Supply Voltage Operating Supply Voltage Input Voltage Max Output Current Power Dissipation (Note 3) Operating Ambient Temperature Max Junction Temperature Storage Temperature Range Thermal Resistance Junction−to−Air Micro−10 DFN 3x3 mm 9−Pin Flip−Chip Symbol VP Op VP Vin Iout Pd TA TJ Tstg RqJA Value 6.0 2.2 to 5.5 V −0.3 to Vcc +0.3 500 Internally Limited −40 to +85 150 −65 to +150 200 70 (Note 4) > 2000 > 200 100 mA Unit V − V mA − °C °C °C °C/W ESD Protection Human Body Model (HBM) (Note 5) Machine Model (MM) (Note 6) − − V Latchup Current at TA = 85°C (Note 7) Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 2. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25°C. 3. The thermal shutdown set to 160°C (typical) avoids irreversible damage on the device due to power dissipation. For further information see page 6. 4. For the 9−Pin Flip−Chip CSP package, the RqJA is highly dependent of the PCB Heatsink area. For example, RqJA can equal 195°C/W with 50 mm2 total area and also 135°C/W with 500 mm2. For further information see page 10. The bumps have the same thermal resistance and all need to be connected to optimize the power dissipation. 5. Human Body Model, 100 pF discharge through a 1.5 kW resistor following specification JESD22/A114. 6. Machine Model, 200 pF discharged through all pins following specification JESD22/A115. 7. Maximum ratings per JEDEC standard JESD78. http://onsemi.com 4 NCP4894 ELECTRICAL CHARACTERISTICS Limits apply for TA between −40°C to +85°C (Unless otherwise noted). Characteristic Supply Quiescent Current Symbol Idd Conditions VP = 3.0 V, No Load VP = 5.0 V, No Load VP = 3.0 V, 8.0 W VP = 5.0 V, 8.0 W Common Mode Voltage Shutdown Current Vcm ISD − For VP between 2.2 V to 5.5 V SDM = SDS = GND TA = 25°C TA = −40°C to +85°C − − Cby = 1.0 mF − VP = 3.0 V, RL = 8.0 W VP = 5.0 V, RL = 8.0 W (Note 9) TA = 25°C TA = −40°C to +85°C Rms Output Power PO VP = 3.0 V, RL = 8.0 W THD + N < 0.1% VP = 3.3 V, RL = 8.0 W THD + N < 0.1% VP = 5.0 V, RL = 8.0 W THD + N < 0.1% For VP between 2.2 V to 5.5 V G = 2.0, RL = 8.0 W VPripple_pp = 200 mV Cby = 1.0 mF Input Terminated with 10 W F = 217 Hz VP = 5.0 V VP = 3.0 V F = 1.0 kHz VP = 5.0 V VP = 3.0 V Efficiency Thermal Shutdown Temperature Total Harmonic Distortion h Tsd THD VP = 3.0 V, F = 1.0 kHz RL = 8.0 W, AV = 2.0 PO = 0.32 W VP = 5.0 V, F = 1.0 kHz RL = 8.0 W, AV = 2.0 PO = 1.0 W VP = 3.0 V, Porms = 380 mW VP = 5.0 V, Porms = 1.0 W − − − − − − − − − − − − − −80 −80 −85 −85 64 63 160 − 0.007 − − 0.006 − − − − − − − − − − − − − − % °C % Min (Note 8) − − − − − Typ 1.9 2.1 2.0 2.2 VP/2 Max (Note 8) − − − 4.0 − V Unit mA − − 1.4 − − − − 4.0 3.85 − − − −30 20 − − − 140 20 2.5 4.3 − 0.39 0.48 1.08 1.0 600 2.0 − 0.4 − − − − − − − − 30 nA mA V V ms ms V V SD SELECT Threshold High SD SELECT Threshold Low Turning On Time (Note 10) Turning Off Time (Note 10) Output Swing VSDIH VSDIL TWU TSD Vloadpeak W Output Offset Voltage Power Supply Rejection Ratio VOS PSRR V+ mV dB 8. Min/Max limits are guaranteed by design, test or statistical analysis. 9. This parameter is not tested in production for 9−Pin Flip−Chip CSP package in case of a 5.0 V power supply, however it is correlated based on a 3.0 V power supply testing. 10. See page 11 for a theoretical approach of these parameters. http://onsemi.com 5 NCP4894 TYPICAL PERFORMANCE CHARACTERISTICS 0.100 VP = 5 V RL = 8 W Pout = 400 mW THD+N(%) THD+N(%) 0.100 VP = 3 V RL = 8 W Pout = 250 mW 0.010 0.010 0.001 10 100 1000 FREQUENCY (Hz) 10000 100000 0.001 10 100 1000 FREQUENCY (Hz) 10000 100000 Figure 2. THDN versus Frequency Figure 3. THDN versus Frequency 0.100 VP = 2.6 V RL = 8 W Pout = 150 mW THD+N(%) THD+N(%) 0.100 VP = 3.6 V RL = 4 W Pout = 300 mW 0.010 0.010 0.001 10 100 1000 FREQUENCY (Hz) 10000 100000 0.001 10 100 1000 FREQUENCY (Hz) 10000 100000 Figure 4. THDN versus Frequency Figure 5. THDN versus Frequency 10 10 1 THD+N(%) 0.1 THD+N(%) VP = 5 V RL = 8 W f = 1 kHz 1 VP = 3 V RL = 8 W f = 1 kHz 0.1 0.01 0.01 0.001 0 200 400 600 800 1000 1200 OUTPUT POWER (mW) 0.001 0 100 200 300 400 500 OUTPUT POWER (mW) Figure 6. THDN versus Output Power Figure 7. THDN versus Output Power http://onsemi.com 6 NCP4894 TYPICAL PERFORMANCE CHARACTERISTICS 10 10 1 THD+N(%) THD+N(%) VP = 2.6 V RL = 8 W f = 1 kHz 1 VP = 3.6 V RL = 4 W f = 1 kHz 0.1 0.1 0.01 0.01 0.001 0 100 200 300 OUTPUT POWER (mW) 0.001 0 200 400 600 800 1000 OUTPUT POWER (mW) Figure 8. THDN versus Output Power Figure 9. THDN versus Output Power 2000 1800 OUTPUT POWER (mW) 1600 1400 PSSR(dB) 1200 1000 800 600 400 200 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 THD+N = 1% THD+N = 10% RL = 8 W f = 1 kHz 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 100 1000 10000 100000 VP = 5 V RL = 8 W Vripple = 200 mV pk−pk Inputs grounded with 10 W Av = 1 Cb = 1 mF POIWER SUPPLY (V) FREQUENCY (Hz) Figure 10. THDN versus Output Power Figure 11. PSRR @ VP = 5 V 0 −10 −20 −30 PSSR(dB) −40 −50 −60 −70 −80 −90 −100 100 1000 10000 100000 VP = 3 V RL = 8 W Vripple = 200 mV pk=pk Inputs grounded with 10 W Av = 1 Cb = 1 mF 0 −10 −20 −30 PSSR(dB) −40 −50 −60 −70 −80 −90 −100 100 1000 10000 100000 VP = 2.2 V RL = 8 W Vripple = 200 mV pk−pk Inputs grounded with 10 W Av = 1 Cb = 1 mF FREQUENCY (Hz) FREQUENCY (Hz) Figure 12. PSRR @ VP = 3 V Figure 13. PSRR @ VP = 2.2 V http://onsemi.com 7 NCP4894 TYPICAL PERFORMANCE CHARACTERISTICS 0 −10 −20 −30 PSSR(dB) −40 −50 −60 −70 −80 −90 −100 100 1000 Cb = 0.47 mF 10000 100000 Cb = 1 mF Cb = 4.7 mF VP = 3 V RL = 8 W Vripple = 200 mV pk−pk Inputs grounded with 10 W Av = 1 0 −10 −20 −30 PSRR(dB) −40 −50 −60 −70 −80 −90 −100 100 1000 Av = 1 10000 100000 VP = 3 V RL = 8 W Vripple = 200 mV pk−pk Inputs grounded with 10 W Av = 5 FREQUENCY (Hz) FREQUENCY (Hz) Figure 19. PSRR versus Cb @ VP = 3 V −20 VP = 5 V RL = 8 W Av = 1 Cb = 1 mF Figure 14. PSRR versus Av @ VP = 3 V −20 −30 CMRR(dB) −30 CMRR(dB) VP = 3 V RL = 8 W Av = 1 Cb = 1 mF −40 −40 −50 −50 −60 100 1000 10000 100000 −60 100 1000 10000 100000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 15. CMRR @ VP = 5 V Figure 16. CMRR @ VP = 3 V −20 VP = 2.2V RL = 8 W Av = 1 Cb = 1 mF 100 OUTPUT NOISE VOLTAGE (mVrms) VP = 3.6 V RL = 8 W Av = 1 Cb = 1 mF −30 CMRR(dB) NCP4894 ON −40 10 NCP4894 OFF −50 −60 100 1000 10000 100000 1 10 100 1000 FREQUENCY (Hz) 10000 100000 FREQUENCY (Hz) Figure 17. CMMR @ VP = 2.2 V Figure 18. Noise Floor @ VP = 3.6 V http://onsemi.com 8 NCP4894 TYPICAL PERFORMANCE CHARACTERISTICS Ch1 = OUTA Ch2 = OUTB Ch3 = Shutdown & Math1 = OUTA−OUTB Ch1 = OUTA Ch2 = OUTB Ch3 = Shutdown & Math1 = OUTA−OUTB Figure 20. Turning−on Sequence @ VP = 5 V and f = 1 kHz Figure 21. Turning−on Sequence Zoom @ VP = 5 V and f = 1 kHz Ch1 = OUTA Ch2 = OUTB Ch3 = Shutdown & Math1 = OUTA−OUTB Ch1 = OUTA Ch2 = OUTB Ch3 = Shutdown & Math1 = OUTA−OUTB Figure 22. Turning−off Sequence @ VP = 5 V and f = 1 kHz Figure 23. Turning−off Sequence Zoom @ VP = 5 V and f = 1 kHz http://onsemi.com 9 NCP4894 TYPICAL PERFORMANCE CHARACTERISTICS 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.2 0.4 0.6 0.8 1 1.2 Pout, OUTPUT POWER (W) VP = 5 V RL = 8 W F = 1 kHz THD + N < 0.1% PD, POWER DISSIPATION (W) PD, POWER DISSIPATION (W) 0.3 0.25 0.2 0.15 0.1 0.05 0 0 0.1 0.2 0.3 0.4 0.5 Pout, OUTPUT POWER (W) VP = 3.3 V RL = 8 W F = 1 kHz THD + N < 0.1% Figure 24. Power Dissipation versus Output Power 0.25 PD, POWER DISSIPATION (W) PD, POWER DISSIPATION (W) 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 0 0.1 0.2 0.3 0.4 0 Figure 25. Power Dissipation versus Output Power 0.2 RL = 4 W 0.15 VP = 3 V RL = 8 W F = 1 kHz THD + N < 0.1% RL = 8 W 0.1 0.05 0 Pout, OUTPUT POWER (W) VP = 2.6 V F = 1 kHz THD + N < 0.1% 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Pout, OUTPUT POWER (W) Figure 26. Power Dissipation versus Output Power 700 PD, POWER DISSIPATION (mW) 600 200 mm2 500 50 mm2 400 300 200 100 0 0 PDmax = 633 mW for VP = 5 V, RL = 8 W 20 40 60 80 100 120 140 TA, AMBIENT TEMPERATURE (°C) 500 mm2 PCB Heatsink Area DIE TEMPERATURE (°C) @ AMBIENT TEMPERATURE 25°C 180 Figure 27. Power Dissipation versus Output Power Maximum Die Temperature 150°C 160 140 120 VP = 4.2 V 100 80 60 40 VP = 2.6 V 50 100 150 200 250 300 PCB HEATSINK AREA (mm2) VP = 3.3 V VP = 5 V 160 Figure 28. Power Derating − 9−Pin Flip−Chip CSP Figure 29. Maximum Die Temperature versus PCB Heatsink Area http://onsemi.com 10 NCP4894 APPLICATION INFORMATION Detailed Description The NCP4894 audio amplifier can operate under 2.6 V until 5.5 V power supply. It delivers 320 mW rms output power to 4.0 W load (VP = 2.6 V) and 1.0 W rms output power to 8.0 W load (VP = 5.0 V). The structure of the NCP4894 is basically composed of two identical internal power amplifiers. Both are externally configurable with gain−setting resistors Rin and Rf (the closed−loop gain is fixed by the ratios of these resistors). The load is driven differentially through OUTA and OUTB outputs. This configuration eliminates the need for an output coupling capacitor. Internal Power Amplifier During the shutdown state, the DC quiescent current has a typical value of 10 nA. Current Limit Circuit The maximum output power of the circuit (Porms = 1.0 W, VP = 5.0 V, RL = 8.0 W) requires a peak current in the load of 500 mA. In order to limit the excessive power dissipation in the load when a short−circuit occurs between both outputs, the current limit in the load is fixed to 800 mA. Thermal Overload Protection The output PMOS and NMOS transistors of the amplifier were designed to deliver the output power of the specifications without clipping. The channel resistance (Ron) of the NMOS and PMOS transistors does not exceed 0.6 W when they drive current. The structure of the internal power amplifier is composed of three symmetrical gain stages, first and medium gain stages are transconductance gain stages to obtain maximum bandwidth and DC gain. Turn−On and Turn−Off Transitions A cycle with a turn−on and turn−off transition is illustrated with plots that show both single ended signals on the previous page. In order to eliminate “pop and click” noises during transitions, output power in the load must be slowly established or cut. When logic high is applied to the shutdown pin, the bypass voltage begins to rise exponentially and once the output DC level is around the common mode voltage, the gain is established slowly (20 ms). Using this turn−on mode, the device is optimized in terms of rejection of “pop and click” noises. A theoretical value of turn−on time at 25°C is given by the following formula. Cby: bypass capacitor R: internal 150 k resistor with a 25% accuracy Ton = 0.95 * R * Cby The device has the same behavior when it is turned−off by a logic low on the shutdown pin. During the shutdown mode, amplifier outputs are connected to the ground. However, to totally cut the output audio signal, you only need to wait for 20 ms. Shutdown Function Internal amplifiers are switched off when the temperature exceeds 160°C, and will be switched on again only when the temperature decreases below 140°C. The NCP4894 is unity−gain stable and requires no external components besides gain−setting resistors, an input coupling capacitor and a proper bypassing capacitor in the typical application. Both internal amplifiers are externally configurable (Rf and Rin) with gain configuration. The differential−ended amplifier presents two major advantages: − The possible output power is four times larger (the output swing is doubled) as compared to a single−ended amplifier under the same conditions. − Output pins (OUTA and OUTB) are biased at the same potential VP/2, this eliminates the need for an output coupling capacitor required with a single−ended amplifier configuration. The differential closed loop−gain of the amplifier is given by Avd + * V Rf + orms . Vorms is the rms value of Rin Vinrms the voltage seen by the load and Vinrms is the rms value of the input differential signal. Output power delivered to the load is given by Porms + (Vopeak)2 (Vopeak is the peak differential 2 * RL output voltage). When choosing gain configuration to obtain the desired output power, check that the amplifier is not current limited or clipped. The maximum current which can be delivered to the load is 500 mA Iopeak + Vopeak . RL The device enters shutdown mode once the SD SELECT and SD MODE pins are in the same logic state. This brings flexibility to the design, as the SD MODE pin must be permanently connected to VP or GND on the PCB. If the SD SELECT pin is not connected to the output of a microcontroller or microprocessor, it’s not advisable to let it float. A pulldown or pullup resistor is then suitable. http://onsemi.com 11 NCP4894 Gain−Setting Resistor Selection (Rin and Rf) Rin and Rf set the closed−loop gain of both amplifiers. In order to optimize device and system performance, the NCP4894 should be used in low gain configurations. The low gain configuration minimizes THD + noise values and maximizes the signal to noise ratio, and the amplifier can still be used without running into the bandwidth limitations. A closed loop gain in the range from 2 to 5 is recommended to optimize overall system performance. An input resistor (Rin) value of 22 kW is realistic in most applications, and doesn’t require the use of a very large capacitor Cin. Input Capacitor Selection (Cin) The size of the capacitor must be large enough to couple in low frequencies without severe attenuation. However a large input coupling capacitor requires more time to reach its quiescent DC voltage (VP/2) and can increase the turn−on pops. An input capacitor value between 0.1 m and 0.39 mF performs well in many applications (With Rin = 22 kW). Bypass Capacitor Selection (Cby) The input coupling capacitor blocks the DC voltage at the amplifier input terminal. This capacitor creates a high−pass filter with Rin, the cut−off frequency is given by fc + 1 . 2 * P * Rin * Cin The bypass capacitor Cby provides half−supply filtering and determines how fast the NCP4894 turns on. This capacitor is a critical component to minimize the turn−on pop. A 1.0 mF bypass capacitor value (Cin = < 0.39 mF) should produce clickless and popless shutdown transitions. The amplifier is still functional with a 0.1 mF capacitor value but is more susceptible to “pop and click” noises. Thus, a 1.0 mF bypassing capacitor is recommended. R4 J1 VP 20 kW VP C4 GND C2 1 mF R2 20 kW INM BYPASS VP BYPASS J2 100 kW R3 J5 C3 VP J4 SD SELECT SHUTDOWN CONTROL SD MODE C1 1 mF R1 20 kW INP BYPASS VM + − OUTB 1 mF VMC BRIDGE VP − + OUTA 1 mF J3 RL 8W J10 20 kW R5 Figure 30. Demonstration Board Schematic http://onsemi.com 12 NCP4894 Silkscreen Layer Top Layer Bottom Layer Figure 31. Demonstration Board for 9−Pin Flip−Chip CSP Device − PCB Layers http://onsemi.com 13 NCP4894 BILL OF MATERIAL Item 1 2 3 4 5 6 7 8 Part Description NCP4894 Audio Amplifier SMD Resistor 100 kW SMD Resistor 20 kW Ceramic Capacitor 1.0 mF 6.3 V X5R Jumper Header Vertical Mount, 2*1, 100 mils Jumper Connector, 400 mils I/O Connector. It can be plugged by MC−1,5/3−ST−3,81 (Phoenix Contact Reference) I/O Connector. It can be plugged by BLZ5.08/2 (Weidmüller Reference) Ref − R3 R1, R2 R4, R5 C1, C2 C3, C4 J4, J5 J10 J2 J1, J3 PCB Footprint − 0603 0603 0603 − − − − Manufacturer ON Semiconductor Vishay−Draloric Vishay−Draloric Murata − − Phoenix Contact Weidmüller Manufacturer Reference NCP4894 CRCW0603 Series CRCW0603 Series GRM188 Series − − MC−1,5/3−G SL5.08/2/90B ORDERING INFORMATION Device NCP4894FCT1 NCP4894FCT1G NCP4894DMR2 NCP4894DMR2G NCP4894MNR2 NCP4894MNR2G Marking MAI MAI MAK MAK 4894 4894 Package 9−Pin Flip−Chip 9−Pin Flip−Chip (Pb−Free) Micro−10 Micro−10 (Pb−Free) DFN10 DFN10 (Pb−Free) Shipping† 3000 / Tape & Reel 3000 / Tape & Reel 4000 / Tape & Reel 4000 / Tape & Reel 3000 / Tape & Reel 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. NOTE: This product is offered with either autectic (SnPb−tin/lead) or lead−free solder bumps (G suffix) depending on the PCB assembly process. The NCP4894FCT1G, NCP4894DMR2G, NCP4894MNR2G version requires a lead−free solder paste and should not be used with a SnPb solder paste. http://onsemi.com 14 NCP4894 PACKAGE DIMENSIONS 9−PIN FLIP−CHIP FC SUFFIX CASE 499AL−01 ISSUE O 4X −A− D −B− E 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. MILLIMETERS MIN MAX 0.540 0.660 0.210 0.270 0.330 0.390 1.450 BSC 1.450 BSC 0.290 0.340 0.500 BSC 1.000 BSC 1.000 BSC TOP VIEW 0.10 C 0.05 C −C− SEATING PLANE A DIM A A1 A2 D E b e D1 E1 A2 A1 SIDE VIEW D1 e C B e A 9X E1 b 1 2 3 0.05 C A B 0.03 C BOTTOM VIEW SOLDERING FOOTPRINT* 0.50 0.0197 0.50 0.0197 0.265 0.01 SCALE 20:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 15 NCP4894 PACKAGE DIMENSIONS Micro−10 DM SUFFIX CASE 846B−03 ISSUE D NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION “A” DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION “B” DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. 846B−01 OBSOLETE. NEW STANDARD 846B−02 DIM A B C D G H J K L MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.95 1.10 0.20 0.30 0.50 BSC 0.05 0.15 0.10 0.21 4.75 5.05 0.40 0.70 INCHES MIN MAX 0.114 0.122 0.114 0.122 0.037 0.043 0.008 0.012 0.020 BSC 0.002 0.006 0.004 0.008 0.187 0.199 0.016 0.028 −A− K −B− PIN 1 ID G D 8 PL 0.08 (0.003) M TB S A S 0.038 (0.0015) −T− SEATING PLANE C H J L SOLDERING FOOTPRINT* 10X 1.04 0.041 0.32 0.0126 10X 3.20 0.126 4.24 0.167 5.28 0.208 8X 0.50 0.0196 SCALE 8:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 16 NCP4894 PACKAGE DIMENSIONS DFN10 MN SUFFIX CASE 485C−01 ISSUE A D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS ONTO BOTTOM SURFACE OF TERMINAL b. 6. DETAILS A AND B SHOW OPTIONAL VIEWS FOR END OF TERMINAL LEAD AT EDGE OF PACKAGE. DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 2.45 2.55 3.00 BSC 1.75 1.85 0.50 BSC 0.19 TYP 0.35 0.45 0.00 0.03 EDGE OF PACKAGE E L1 DETAIL A Bottom View (Optional) PIN 1 REFERENCE 2X 2X 0.15 C 0.15 C 0.10 C 10X 0.08 C SIDE VIEW A1 C 1 5 A1 E2 10X K DETAIL B Side View (Optional) 10 10X 6 b BOTTOM VIEW 0.10 C A B 0.05 C NOTE 3 0.5651 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 17 ÉÉ ÉÉ ÉÉ 10X L ÇÇÇ ÇÇÇ ÇÇÇ DETAIL B TOP VIEW (A3) A SEATING PLANE EXPOSED Cu D2 e DETAIL A MOLD CMPD A3 SOLDERING FOOTPRINT* 2.6016 2.1746 1.8508 3.3048 10X 10X 0.3008 0.5000 PITCH DIMENSIONS: MILLIMETERS NCP4894 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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