NCP4896FCT1G

NCP4896 1.0 Watt Audio Power Amplifier with Earpiece Driving Capability The NCP4896 is an audio power amplifier designed for portable communication device applications such as mobile phones. This part is capable of delivering 1.0 W of continuous average power to an 8.0  BTL load from a 5.0 V power supply and, 250 mW to a 4.0  BTL from 2.6 V power supply. It also provides the control of driving a single−ended earpiece and delivers 90 mW from a 5.0 V power supply to a 32  load. This device provides high quality audio while requiring few external components and minimal power consumption. It features a low−power consumption shutdown mode, which is achieved by driving the shutdown pin with logic Low. The NCP4896 contains circuitry to prevent from “pop and click” noise that would otherwise occur during turn−on and turn−off transitions. It is also efficient when switching modes from BTL to SE and SE to BTL. For maximum flexibility, the part provides an externally controlled gain (with resistors), as well as an externally controlled turn−on time (with bypass capacitor). Due to its excellent PSRR, it can be directly connected to the battery, saving the use of an LDO. Features • • • • • • • • • • • Single−Ended or Differential Control 1.0 W to an 8.0  BTL Load from a 5.0 V Power Supply Excellent PSRR: Direct Connection to the Battery Ultra Low Current Shutdown Mode 2.2 V−5.5 V Operation External Gain Configuration Capability External Turn−on Time Configuration Capability Thermal Overload Protection Circuitry Up to 1.0 nF Capacitive Load Driving Capability “Pop and Click” Noise Protection Circuit This is a Pb−Free Device http://onsemi.com MARKING DIAGRAM 1 A3 XXX AYWW 9−PIN FLIP−CHIP FC SUFFIX CASE 499AL C1 A1 XXX A Y WW = Specific Device Code = Assembly Location = Year = Work Week PIN CONNECTIONS 9−PIN FLIP−CHIP CSP A1 A2 A3 SE/BTL BYP OUTB B1 B2 B3 VP NC VM C1 C2 C3 INM SD OUTA (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet. Typical Applications • Portable Electronic Devices • PDAs • Mobile Phones  Semiconductor Components Industries, LLC, 2005 March, 2005 − Rev. 3 1 Publication Order Number: NCP4896/D NCP4896 RF 20 k VP 1 F Cs Cin Rin VP INM 390 nF 20 k − + BYPASS OUTA Co MONO JACK 47 F VP BYPASS Audio Input Cb VIH SHUTDOWN SE VIL VMC BRIDGE 1 F R1 20 k 8.0  LOUD SPEAKER 16  or 32  EARPIECE SHUTDOWN CONTROL SE/BTL 20 k D − + BYPASS R2 OUTB VM Figure 1. Typical NCP4896 Application Circuit with Single−Ended Input PIN DESCRIPTION Pin Type Symbol Description A1 I SE/BTL When this pin is Low , the audio amplifier is in differential mode. If a High level is applied, the configuration is in Single−Ended Mode A2 I BYP A3 O OUTB B1 I VP Positive analog supply of the cell. NC Not connected. B2 Bypass capacitor pin which provides the common mode voltage (VP/2). Positive output of the amplifier. In high impedance state when the device is in Single−Ended mode. B3 I VM Ground. C1 I INM Audio Input Signal. C2 I SD The device enters in shutdown mode when a low level is applied to this pin. C3 O OUTA Negative output of the amplifier. This is the active output dedicated to a SE load when this configuration is activated. http://onsemi.com 2 NCP4896 MAXIMUM RATINGS (Note 1) Rating Symbol Value Unit VP 6.0 V Supply Voltage Operating Supply Voltage Op VP 2.2 to 5.5 V − Input Voltage Vin −0.3 to Vcc +0.3 V Max Output Current Iout 500 mA Power Dissipation (Note 2) Pd Internally Limited − Operating Ambient Temperature TA −40 to +85 °C Max Junction Temperature TJ 150 °C Storage Temperature Range Tstg −65 to +150 °C Thermal Resistance Junction−to−Air RJA 90 (Note 3) °C/W − > 2000 > 200 V −
100 mA − ESD Protection Human Body Model (HBM) (Note 4) Machine Model (MM) (Note 5) Latch Up Current at TA = 85°C (Note 6) Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25°C. 2. The thermal shutdown set to 160°C (typical) avoids irreversible damage on the device due to power dissipation. 3. For the 9−Pin Flip−Chip CSP package, the RJA is highly dependent of the PCB Heatsink area. For example, RJA can equal 195°C/W with 50 mm2 total area and also 135°C/W with a 500 mm2 area. 4. Human Body Model, 100 pF discharge through a 1.5 k resistor following specification JESD22/A114. 5. Machine Model, 200 pF discharged through all pins following specification JESD22/A115. 6. Maximum ratings per JEDEC Standard JESD78. http://onsemi.com 3 NCP4896 ELECTRICAL CHARACTERISTICS Limits apply for TA between −40°C to +85°C (Unless otherwise noted). Characteristic Supply Quiescent Current Symbol Conditions Min (Note 7) Typ Max (Note 7) Unit Idd VP = 3.0 V, No Load VP = 5.0 V, No Load BTL − − 1.7 1.8 − mA VP = 3.0 V, 8.0  BTL VP = 5.0 V, 8.0  BTL − − 1.8 2.0 − 4.0 VP = 5.0 V, No Load, SE − 1.0 2.5 VP = 5.0 V, 32  SE − 1.1 − mA VP/2 − V Common Mode Voltage Vcm − Shutdown Current ISD For VP Between 2.2 V to 5.5 V SD = Low TA = +25°C TA = −40°C to +85°C − − − − 20 − − 600 2.0 nA A Shutdown Voltage High VSDIH − 1.4 − − V Shutdown Voltage Low VSDIL − − − 0.4 V SE Select VBTL/SE − 1.4 − − V DE Select VSE/BTL − − − 0.4 V Turning On Time (Note 8) TWU Cby = 1.0 F − 140 − ms Turning Off Time (Note 8) TSD − − 20 − ms Vloadpeak VP = 3.0 V, 8.0 , BTL VP = 5.0 V, 8.0  BTL 2.3 − 2.57 4.3 − − V VP = 5.0 V, 32  SE − 4.9 − V VP = 5.0 V, 32  SE THD + N < 0.1% VP = 5.0 V, 16 , SE THD + N < 0.1% VP = 5.0 V, 8.0 , BTL THD + N < 0.1% − 92 − mW − 176 − − 1080 − Vos For VP between 2.2 V to 5.5 V BTL and SE −30 1.0 30 PSRR V+ RF = Ri  20 k VPripple_pp = 200 mV Cby = 1.0 F Input Terminated with 10  Output Swing Rms Output Power Output Offset Voltage Power Supply Rejection Ratio Efficiency Thermal Shutdown Temperature Total Harmonic Distortion PO  dB f = 217 Hz to 1.0 khz VP = 5.0 V, 8.0  BTL VP = 3.0 V, 8.0  BTL − − −66 −67 − − VP = 5.0 V, 32  SE VP = 3.0 V, 32  SE − − −69 −70 − − − 64 − − 63 − − 160 − VP = 3.0 V, 8.0  BTL Porms = 380 mW VP = 5.0 V, 8.0  BTL Porms = 1.0 W Tsd − THD + N RF = Ri  20 k VP = 3.6 V, f = 1.0 kHz Pout = 400 mW, 8.0 , BTL Pout = 40 mW, 16 , BTL Pout = 40 mW, 32  SE 7. Min/Max limits are guaranteed by design, test or statistical analysis. 8. See section “Application Information” for a theoretical approach of this parameter. http://onsemi.com 4 mV % °C % − − − 0.02 0.01 0.003 − − − NCP4896 TYPICAL PERFORMANCE CHARACTERISTICS 10 10 VP = 5.0 V RF = Ri  20 k BTL Mode RL = 8  f = 1.0 kHz VP = 3.0 V RF = Ri  20 k BTL Mode RL = 8  f = 1.0 kHz 1 THD + N (%) THD + N (%) 1 0.1 0.1 0.01 0.01 0.001 0.001 0 200 400 600 800 1000 1200 0 Pout, POWER OUT (mW) 200 400 300 500 Pout, POWER OUT (mW) Figure 2. THD + N vs. Power Out (BTL Mode) Figure 3. THD + N vs. Power Out (BTL Mode) 1 10 VP = 2.6 V RF = Ri  20 k BTL Mode RL = 4  f = 1.0 kHz 1 THD + N (%) THD + N (%) 100 0.1 VP = 5.0 V RF = Ri  20 k BTL Mode RL = 8  Pout = 250 mW 0.1 0.01 0.001 0.01 0 100 200 300 400 10 500 100 1000 10,000 100,000 FREQUENCY (Hz) Pout, POWER OUT (mW) Figure 5. THD + N vs. Frequency (BTL Mode) Figure 4. THD + N vs. Power Out (BTL Mode) VP = 3.0 V RF = Ri  20 k BTL Mode RL = 8  Pout = 250 mW 0.1 THD + N (%) THD + N (%) 1 0.01 0.001 VP = 2.6 V RF = Ri  20 k BTL Mode RL = 8  Pout = 100 mW 0.1 0.01 0.001 10 100 1000 10,000 100,000 10 FREQUENCY (Hz) 100 1000 10,000 FREQUENCY (Hz) Figure 6. THD + N vs. Frequency (BTL Mode) Figure 7. THD + N vs. Frequency (BTL Mode) http://onsemi.com 5 100,000 NCP4896 TYPICAL PERFORMANCE CHARACTERISTICS 10.000 VP = 5.0 V RF = Ri  20 k SE Mode RL = 32  f = 1.0 kHz 1.000 THD + N (%) THD + N (%) 1.000 10.000 0.100 0.010 0.001 0 VP = 3.0 V RF = Ri  20 k SE Mode RL = 32  f = 1.0 kHz 0.100 0.010 20 40 60 0.001 0 100 80 10 OUTPUT POWER (mW) 40 Figure 9. THD + N vs. Output Power (SE Mode) 1.000 10.000 VP = 2.6 V RF = Ri  20 k SE Mode RL = 32  f = 1.0 kHz THD + N (%) THD + N (%) 30 OUTPUT POWER (mW) Figure 8. THD + N vs. Output Power (SE Mode) 1.000 20 0.100 VP = 4.2 V RF = Ri  20 k SE Mode RL = 32  Pout = 50 mW 0.100 0.010 0.010 0.001 0 5.0 10 15 20 25 0.001 10 30 100 0 0 −10 −10 VP = 2.6 V RF = Ri  20 k, Cb = 1.0 F BTL Mode RL = 8  Vripple = 200 mV pk−pk −20 −30 PSRR (dB) PSRR (dB) −40 −50 −60 −40 −60 −70 −80 −80 −90 −90 100 1000 10000 100000 VP = 3.6 V RF = Ri  20 k, Cb = 1.0 F BTL Mode RL = 8  Vripple = 200 mV pk−pk −50 −70 −100 10 100000 Figure 11. THD + N vs. Frequency (SE Mode) Figure 10. THD + N vs. Output Power (SE Mode) −30 10000 FREQUENCY (Hz) OUTPUT POWER (mW) −20 1000 −100 10 100 1000 10000 100000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 12. PSRR (BTL Mode) @ VP = 2.6 V Figure 13. PSRR (BTL Mode) @ VP = 3.6 V http://onsemi.com 6 NCP4896 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 −10 −10 PSRR (dB) −30 −40 VP = 5.0 V RF = Ri  20 k, Cb = 1.0 F BTL Mode RL = 8  Vripple = 200 mV pk−pk −30 −50 −60 −40 −50 −70 −80 −80 −90 −90 Cb=1.0 F 100 1000 10000 −100 10 100000 −30 −40 −50 10000 100000 Figure 15. PSRR vs. Cb (BTL Mode) @ VP = 3.6 V 0 VP = 3.6 V RF = Ri  20 k and RF = Ri  100 k BTL Mode RL = 8  Vripple = 200 mV pk−pk −10 −20 −30 GAIN = 5 −40 VP = 2.6 V RF = Ri  20 k, Cb = 1.0 F SE Mode RL = 32  Vripple = 200 mV pk−pk −50 −60 −70 −70 −80 GAIN = 1 −90 −90 −100 10 1000 Figure 14. PSRR (BTL Mode) @ VP = 5.0 V −60 −80 100 FREQUENCY (Hz) PSRR (dB) −20 Cb= 4.7 F FREQUENCY (Hz) 0 −10 PSRR (dB) Cb=0.47 F −60 −70 −100 10 100 1000 10000 −100 10 100000 100 1000 10000 100000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 16. PSRR vs. Gain (BTL Mode) @ VP = 3.6 V Figure 17. PSRR (SE Mode) @ VP = 2.6 V 0 −20 −30 −40 0 −10 VP = 3.6 V RF = Ri  20 k, Cb = 1.0 F SE Mode RL = 32  Vripple = 200 mV pk−pk −20 −30 PSRR (dB)R −10 PSRR (dB) VP = 3.6 V RF = Ri  20 k BTL Mode RL = 8  Vripple = 200 mV pk−pk −20 PSRR (dB) −20 −50 −60 −40 −50 −60 −70 −70 −80 −80 −90 −90 −100 10 100 1000 10000 100000 VP = 5.0 V RF = Ri  20 k, Cb = 1.0 F SE Mode RL = 32  Vripple = 200 mV pk−pk −100 10 100 1000 10000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 18. PSRR (SE Mode) @ VP = 3.6 V Figure 19. PSRR (SE Mode) @ VP = 5.0 V http://onsemi.com 7 100000 NCP4896 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 −10 −10 VP = 3.6 V RF = Ri  20 k SE Mode RL = 32  Vripple = 200 mV pk−pk PSRR (dB) −30 −40 −50 −30 Cb=0.47 F −60 −40 GAIN = 5 −50 −60 −70 −70 −80 −100 10 −80 Cb= 4.7 F −90 Cb=1.0 F 100 GAIN = 1 −90 1000 10000 100000 −100 10 100 1000 10000 100000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 20. PSRR vs. Cb (SE Mode) @ VP = 3.6 V Figure 21. PSRR vs. Gain (SE Mode) @ VP = 3.6 V 50 OUTPUT NOISE VOLTAGE ( Vrms) 50 OUTPUT NOISE VOLTAGE ( Vrms) VP = 3.6 V RF = Ri  20 k and RF = Ri  100 k SE Mode RL = 8  Vripple = 200 mV pk−pk −20 PSRR (dB) −20 NCP4896 ON 40 30 20 VP = 3.6 V RF = Ri  20 k BTL Mode RL = 8  10 NCP4896 OFF 0 10 100 1000 VP = 3.6 V RF = Ri  20 k SE Mode RL = 32  40 30 20 NCP4896 ON 10 NCP4896 OFF 0 10 10000 100 1000 10000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 22. Output Noise Voltage (BTL Mode) @ VP = 3.6 V Figure 23. Output Noise Voltage (SE Mode) @ VP = 3.6 V 3.2 2.0 1.9 3.0 1.8 VP = 5.5 V 1.7 VP = 5.0 V Idd, (mA) Idd, (mA) 2.8 2.6 VP = 3.0 V 2.4 2.2 RF = Ri = 20  BTL MODE RL = 8  VP = 2.2 V 2.0 −40 −15 10 35 60 VP = 5.5 V VP = 5.0 V 1.6 1.5 1.4 VP = 3.0 V 1.3 1.2 RF = Ri = 20  SE MODE RL =32  VP = 2.2 V 1.1 1.0 −40 85 TEMPERATURE (C°) −15 10 35 60 85 TEMPERATURE (C°) Figure 24. Quiescent Current (BTL Mode) vs. VP Figure 25. Quiescent Current (SE Mode) vs. VP http://onsemi.com 8 NCP4896 TYPICAL PERFORMANCE CHARACTERISTICS VP = 3.6 V RF = Ri  20 k, Cb = 1.0 F BTL Mode RL = 8  Figure 26. Turn On Sequence (BTL Mode) @ VP = 3.6 V http://onsemi.com 9 NCP4896 TYPICAL PERFORMANCE CHARACTERISTICS 0.3 PD, POWER DISSIPATION (W) PD, POWER DISSIPATION (W) 0.7 0.6 0.5 0.4 VP = 5 V RL = 8  F = 1 kHz THD + N < 0.1% 0.3 0.2 0.1 0 0.25 0.2 0.15 VP = 3.3 V RL = 8  F = 1 kHz THD + N < 0.1% 0.1 0.05 0 0 0.2 0.4 0.6 0.8 1 1.2 0 0.1 0.2 Pout, OUTPUT POWER (W) Figure 27. Power Dissipation vs. Output Power 0.5 0.4 PD, POWER DISSIPATION (W) PD, POWER DISSIPATION (W) 0.4 Figure 28. Power Dissipation vs. Output Power 0.25 0.2 0.15 VP = 3 V RL = 8  F = 1 kHz THD + N < 0.1% 0.1 0.05 0 0.35 RL = 4  0.3 0.25 0.2 RL = 8  0.15 0.1 VP = 2.6 V F = 1 kHz THD + N < 0.1% 0.05 0 0 0.1 0.2 0.3 0.4 0 0.05 0.1 Pout, OUTPUT POWER (W) 0.15 0.2 0.25 0.3 0.35 0.4 Pout, OUTPUT POWER (W) Figure 29. Power Dissipation vs. Output Power Figure 30. Power Dissipation vs. Output Power 180 DIE TEMPERATURE (°C) @ AMBIENT TEMPERATURE 25°C 700 PD, POWER DISSIPATION (mW) 0.3 Pout, OUTPUT POWER (W) PCB Heatsink Area 600 200 mm2 500 50 mm2 500 mm2 400 300 200 PDmax = 633 mW for VP = 5 V, RL = 8  100 0 0 20 40 Maximum Die Temperature 150°C 160 140 120 VP = 4.2 V 100 80 80 100 120 140 160 VP = 3.3 V 60 40 60 VP = 5 V VP = 2.6 V 50 100 150 200 250 PCB HEATSINK AREA (mm2) TA, AMBIENT TEMPERATURE (°C) Figure 31. Power Derating − 9−Pin Flip−Chip CSP Figure 32. Maximum Die Temperature vs. PCB Heatsink Area http://onsemi.com 10 300 NCP4896 APPLICATION INFORMATION Detailed Description Shutdown Function The NCP4896 audio amplifier can operate from 2.2 V until 5.5 V power supply. It delivers 320 mW rms output power to 4.0  load (VP = 2.6 V) and 1.0 W rms output power to 8.0  load (VP = 5.0 V). The structure of the NCP4896 is basically composed of two identical internal power amplifiers. Both are externally configurable with gain−setting resistors Rin and RF (the closed−loop gain is fixed by the ratios of these resistors). So the load is driven differentially through OUTA and OUTB outputs. This configuration eliminates the need for an output coupling capacitor. The device enters shutdown mode when the shutdown signal is low. During the shutdown mode, the Dc quiescent current of the circuit is typically 10 nA. Current Limit Circuit The maximum output power of the circuit (Porms = 1.0 W, VP = 5.0 V, RL = 8.0 ) requires a peak current in the load of 500 mA. In order to limit the excessive power dissipation in the load when a short−circuit occurs, the current limit in the load is fixed to 800 mA. The current in the four output MOS transistors are real−time controlled, and when one current exceeds 800 mA, the gate voltage of the MOS transistor is clipped and no more current can be delivered. Internal Power Amplifier The output Pmos and Nmos transistors of the amplifier were designed to deliver the output power of the specifications without clipping. The channel resistance (Ron) of the Nmos and Pmos transistors does not exceed 0.6
 when they drive current. The structure of the internal power amplifier is composed of three symmetrical gain stages, first and medium gain stages are transconductance gain stages to obtain maximum bandwidth and DC gain. Single−Ended Operation In SE mode, the load is driven from the primary amplifier output (OUTA). The gain is set by the ration between RF and Ri.   SE Gain
− Rf Ri In this SE mode, an output capacitor (Co) is required to block the common mode voltage at the output of the amplifier, thus avoiding DC currents in the load. As for the high pass filter due to the input capacitor and the Ri resistor, the load gives with Co another first order high pass filter, the cut−off frequency of which is given by: Turn−On and Turn−Off Transitions A cycle with a turn−on and turn−off transition is illustrated with plots that show both single ended signals on the previous page. In order to eliminate “pop and click” noises during transitions, output power in the load must be slowly established or cut. When logic high is applied to the shutdown pin, the bypass voltage begins to rise exponentially and once the output DC level is around the common mode voltage, the gain is established slowly (20 ms). This way to turn−on the device is optimized in terms of rejection of “pop and click” noises. A theoretical value of turn−on time at 25°C is given by the following formula. Cby: bypass capacitor R: internal 150 k resistor with a 25% accuracy Ton = 0.95 * R * Cby The device has the same behavior when it is turned−off by a logic low on the shutdown pin. During the shutdown mode, amplifier outputs are connected to the ground. However, to cut totally the output audio signal, you only need to wait for 20 ms. Fc
1 2 RL  Co SE/BTL Operation Due to the internal control of each amplifier through SE/BTL pin, the NCP4896 allows a cost saving for application which requires to drive a example an 8.0  BTL and a   Single−Ended load. The internal circuitry avoids “pop and click” noises that could occur in both BTL and Singled−Ended loads during transitions from SE to BTL and BTL to SE. http://onsemi.com 11 NCP4896 Thermal Overload Protection Gain−Setting Resistor Selection (Rin and RF) Internal amplifiers are switched off when the temperature exceeds 160°C, and will be switched on again only when the temperature decreases below 140°C. The NCP4896 is unity−gain stable and requires no external components besides gain−setting resistors, an input coupling capacitor and a proper bypassing capacitor in the typical application. Both internal amplifiers are externally configurable (RF and Rin) with gain configuration. The differential−ended amplifier presents two major advantages: − The possible output power is four times larger (the output swing is doubled) as compared to a single−ended amplifier under the same conditions. − Output pins (OUTA and OUTB) are biased at the same potential VP/2, this eliminates the need for an output coupling capacitor required with a single−ended amplifier configuration. The differential closed loop−gain of the amplifier is Rin and RF set the closed−loop gain of both amplifier. In order to optimize device and system performance, the NCP4896 should be used in low gain configurations. The low gain configuration minimizes THD + noise values and maximizes the signal to noise ratio, and the amplifier can still be used without running into the bandwidth limitations. A closed loop gain in the range from 2 to 5 is recommended to optimize overall system performance. An input resistor (Rin) value of 22 k is realistic in most of applications, and doesn’t require the use of a too large capacitor Cin. given by Avd
* Input Capacitor Selection (Cin) The input coupling capacitor blocks the DC voltage at the amplifier input terminal. This capacitor creates a high−pass filter with Rin, the cut−off frequency is given by fc
The value of the capacitor must be high enough to ensure good coupling at low frequencies without attenuation. However a large input coupling capacitor requires more time to reach its quiescent DC voltage (VP/2) and can increase the turn−on pops. An input capacitor value between 0.1 and 0.39 F performs well in many applications (With Rin = 22 k). V Rf
orms . Vorms is the rms value of Rin Vinrms the voltage seen by the load and Vinrms is the rms value of the input differential signal. Output power delivered to the load is given by Porms
(Vopeak)2 (Vopeak is the peak differential 2 * RL output voltage). When choosing gain configuration to obtain the desired output power, check that the amplifier is not current limited or clipped. The maximum current which can be delivered to the load is 500 mA Iopeak
1 . 2 *  * Rin * Cin Bypass Capacitor Selection (Cby) The bypass capacitor Cby provides half−supply filtering and determines how fast the NCP4896 turns on. This capacitor is a critical component to minimize the turn−on pop. A 1.0 F bypass capacitor value (Cin = < 0.39 F) should produce clickless and popless shutdown transitions. The amplifier is still functional with a 0.1 F capacitor value but is more susceptible to “pop and click” noises. Thus, a 1.0 F bypassing capacitor is recommended. Vopeak . RL http://onsemi.com 12 NCP4896 R1 VP J1 20 k VP GND 1 F Cs J18 U1 C2 R2 INM Audio Input 1 F TP3 TP5 VP 20 k − + BYPASS Co OUTA 47 F R5 VP J5 1 k BYPASS Audio Input VMC BRIDGE 1 F C4 20 k 16  or 32  EARPIECE IN U2 OR J5 VP J9 100 k R4 J12 J13 SHUTDOWN J6 BIAS CONTROL Shutdown Input J20 J8 RL 8 20 k TP4 SE/BTL J10 J11 VP J19 − + BYPASS OUTB SE/BTL Input VM C5 100 nF R7 100 k R6 VP 100 k Figure 33. Typical NCP4896 Application Circuit with Single−Ended Input http://onsemi.com 13 U2 NCP4896 Silkscreen Layer Top Layer Bottom Layer Figure 34. Demonstration Board for 9−Pin Flip−Chip CSP Device − PCB Layers http://onsemi.com 14 NCP4896 BILL OF MATERIAL Item Part Description PCB Footprint Ref 1 NCP4896 Audio Amplifier U1 2 3.5 mm PCB Jack Connector U2 3 SMD Resistor 20 k R1, R2 4 SMD Resistor 100 k R4, R6, R7 5 SMD Resistor 1.0 k 6 Ceramic Capacitor 1.0 F, 16 V, X7R 7 Manufacturer Reference Manufacturer NCP4896 Decelect−Forgos (Eurosab) IEM101−3 0805 Vishnay−Draloric CRCW0805 0805 Vishnay−Draloric CRCW0805 R5 0805 Vishnay−Draloric CRCW0805 C1, C2, C4 0805 Murata GRM21 Series GRM21BR71C105KA01L Tantalum Capacitor 47 F, 6.3 V C3 B Size AVX TPS Series 8 Ceramic Capcitor 100 nF, 50 V, X7R C5 0805 Murata GRM21 Series GRM21BR71H104KA01L 9 Jumper Header Vertical Mount, 2*1, 100 mils 10 Jumper Connector, 400 mils 11 I/O Connector. It Can be Plugged by BLZ5.08/2 (Weidmuller Reference) Weidmuller SL5.08/2/90B 12 SMB Connector J4, J8, J9 Radiall R114665000 13 Test Point TP3, TP4, TP5 Keystone 5000 J10, J11, J12, J13, J19, J20 J18 J1, J5, J6 ORDERING INFORMATION Device NCP4896FCT1G Marking Package Shipping† MAM 9−Pin Flip−Chip (Pb−Free) 3000/Tape and Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 15 NCP4896 PACKAGE DIMENSIONS 9−PIN FLIP−CHIP FC SUFFIX CASE 499AL−01 ISSUE O −A− 4X NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. D 0.10 C −B− E DIM A A1 A2 D E b e D1 E1 TOP VIEW A 0.10 C 0.05 C −C− A2 A1 SIDE VIEW SEATING PLANE MILLIMETERS MIN MAX 0.540 0.660 0.210 0.270 0.330 0.390 1.450 BSC 1.450 BSC 0.290 0.340 0.500 BSC 1.000 BSC 1.000 BSC D1 e C B e E1 SOLDERING FOOTPRINT* A 9X b 1 2 3 0.05 C A B 0.03 C 0.50 0.0197 BOTTOM VIEW 0.50 0.0197 0.265 0.01 SCALE 20:1 mm  inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: orderlit@onsemi.com http://onsemi.com 16 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NCP4896/D