NCP502, NCV502
Voltage Regulator - CMOS
Low Iq, Low-Dropout
80 mA
The NCP502 series of fixed output linear regulators are designed for
handheld communication equipment and portable battery powered
applications which require low quiescent. The NCP502 series features
an ultra−low quiescent current of 40 A. Each device contains a
voltage reference unit, an error amplifier, a PMOS power transistor,
resistors for setting output voltage, current limit, and temperature limit
protection circuits.
The NCP502 has been designed to be used with low cost ceramic
capacitors. The device is housed in the micro−miniature SC70−5 and
TSOP−5 surface mount packages. Standard voltage versions are 1.5 V,
1.8 V, 2.5 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V, 3.3 V, 3.4 V, 3.5 V, 3.6 V,
3.7 V and 5.0 V. Other voltages are available in 100 mV steps.
•
•
•
5
4
12
1
Low Quiescent Current of 40 A Typical
Excellent Line and Load Regulation
Low Output Voltage Option
Output Voltage Accuracy of 2.0%
Industrial Temperature Range of −40°C to 85°C,
NCV502, TA = −40°C to 125°C
NCP502: 1.3 V Enable Threshold High, 0.3 V Enable Threshold Low
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These are Pb−Free Devices
Typical Applications
•
•
•
•
MARKING
DIAGRAM
5
Features
•
•
•
•
•
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Cellular Phones
Battery Powered Consumer Products
Hand−Held Instruments
Camcorders and Cameras
Battery or
Unregulated
Voltage
C1
+
1
3
3
xxx MG
G
1
TSOP−5
(SOT23−5, SC59−5)
SN SUFFIX
CASE 483
5
xxx AYWG
G
1
xxx = Specific Device Code
A
= Assembly Location
Y
= Year
W
= Work Week
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
Vin
1
GND
2
Enable
3
5
Vout
4
N/C
(Top View)
ORDERING INFORMATION
Vout
5
+
2
ON
5
SC70−5
SQ SUFFIX
CASE 419A
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
C2
4
OFF
This device contains 86 active transistors
Figure 1. Typical Application Diagram
© Semiconductor Components Industries, LLC, 2016
October, 2019 − Rev. 21
1
Publication Order Number:
NCP502/D
NCP502, NCV502
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
1
Vin
Description
2
GND
3
Enable
4
N/C
No internal connection.
5
Vout
Regulated output voltage.
Positive power supply input voltage.
Power supply ground.
This input is used to place the device into low−power standby. When this input is pulled low, the device is
disabled. If this function is not used, Enable should be connected to Vin.
MAXIMUM RATINGS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Rating
Symbol
Value
Unit
Vin
12
V
Enable Voltage
Enable
−0.3 to Vin +0.3
V
Output Voltage
Vout
−0.3 to Vin +0.3
V
Power Dissipation and Thermal Characteristics
Power Dissipation
PD
Internally Limited
W
Operating Junction Temperature
TJ
+150
°C
TA
−40 to +85
−40 to +125
°C
Tstg
−55 to +150
°C
Input Voltage
Operating Ambient Temperature
NCP502
NCV502
Storage Temperature
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Latchup capability (85°C) ±100 mA DC with trigger voltage.
THERMAL CHARACTERISTICS
Rating
Symbol
Thermal Characteristics, TSOP−5 (Note 2)
Thermal Resistance, Junction−to−Air (Note 3)
RJA
Thermal Resistance, Junction−to−Ambient, SC70−5
RJA
Test Conditions
1 oz Copper Thickness, 100 mm2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
NOTE:
Value
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
205
400
Single component mounted on a 80 x 80 x 15 mm FR4 PCB with stated copper head spreading area. Using the following
boundary conditions as stated in EIA/JESD 51−1, 2, 3, 7, 12.
2. True no connect. Printed circuit board traces are allowable.
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per MIL−STD−883, Method 3015.
Machine Model Method 200 V..
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2
Unit
°C/W
W
°C/W
NCP502, NCV502
ELECTRICAL CHARACTERISTICS
(Vin = Vout(nom.) + 2.0 V, Venable = Vin, Cin = 1.0 F, Cout = 1.0 F, TJ = 25°C, unless otherwise noted.)
Symbol
Characteristic
Output Voltage (TA = 25°C, Iout = 10 mA) Vin = Vout (nom.) +1.0 V
1.5 V
1.8 V
2.5 V
2.7 V
2.8 V
2.9 V
3.0 V
3.1 V
3.3 V
3.4 V
3.5 V
3.6 V
3.7 V
5.0 V
Vout
Output Voltage (TA = Tlow to Thigh, Iout = 10 mA) Vin = Vout (nom.)
1.5 V
1.8 V
2.5 V
2.7 V
2.8 V
2.9 V
3.0 V
3.1 V
3.3 V
3.4 V
3.5 V
3.6 V
3.7 V
5.0 V
Vout
Min
Typ
Max
1.455
1.746
2.425
2.646
2.744
2.842
2.94
3.038
3.234
3.332
3.43
3.528
3.626
4.900
1.5
1.8
2.5
2.7
2.8
2.9
3.0
3.1
3.3
3.4
3.5
3.6
3.7
5.0
1.545
1.854
2.575
2.754
2.856
2.958
3.06
3.162
3.366
3.468
3.57
3.672
3.774
5.100
1.455
1.746
2.425
2.619
2.716
2.813
2.910
3.007
3.201
3.298
3.43
3.528
3.626
4.900
1.5
1.8
2.5
2.7
2.8
2.9
3.0
3.1
3.3
3.4
3.5
3.6
3.7
5.0
1.545
1.854
2.575
2.781
2.884
2.987
3.09
3.193
3.399
3.502
3.57
3.672
3.774
5.100
Unit
V
V
Line Regulation (Vin = Vout + 1.0 V to 12 V, Iout = 10 mA)
Regline
−
0.4
3.0
mV/V
Load Regulation (Iout = 1.0 mA to 80 mA)
Regload
−
0.2
0.8
mV/mA
Output Current (Vout = (Vout at Iout = 80 mA) −3%)
Io(nom.)
80
180
−
mA
Dropout Voltage (TA = Tlow to Thigh, Iout = 80 mA, Measured at Vout
−3.0%)
1.5 V−1.7 V
1.8 V−2.4 V
2.5 V−2.6 V
2.7 V−2.9 V
3.0 V−4.0 V
4.1 V−5.0 V
NCV502 − 5.0 V
Vin−Vout
Quiescent Current
(Enable Input = 0 V)
(Enable Input = Vin, Iout = 1.0 mA to Io(nom.))
IQ
Output Short Circuit Current (Vout = 0 V)
mV
−
−
−
−
−
−
−
1500
1300
1000
850
850
600
700
1900
1700
1400
1300
1200
900
1100
−
−
0.1
40
1.0
90
A
Iout(max)
90
200
500
Ripple Rejection (f = 1.0 kHz, 15 mA)
RR
−
55
−
dB
Output Voltage Noise (f = 100 Hz to 100 kHz)
Vn
−
180
−
Vrms
1.3
−
−
−
−
0.3
−
100
−
Enable Input Threshold Voltage (NCP502)
(Voltage Increasing, Output Turns On, Logic High)
(Voltage Decreasing, Output Turns Off, Logic Low)
Vth(en)
Output Voltage Temperature Coefficient
TC
V
4. Maximum package power dissipation limits must be observed.
T
*TA
PD + J(max)
RJA
5. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
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3
mA
ppm/°C
NCP502, NCV502
45
40
IQ, QUIESCENT CURRENT (A)
VOUT = 3.0 V
35
30
25
20
15
10
5
IOUT, OUTPUT
CURRENT (mA)
0
1
4
3
5
6
40
37.5
35
32.5
30
−60
7
−40
−20
0
40
20
60
80
100
T, TEMPERATURE (°C)
Figure 2. Quiescent Current versus Input Voltage
Figure 3. Quiescent Current versus Temperature
6
VIN = 4.0 V to 5.0 V
5
4
60
COUT = 1.0 F
IOUT = 30 mA
40
20
0
−20
−40
ENABLE
VOLTAGE (V)
VIN, INPUT VOLTAGE (V)
0
10
20
30
40
50
60
70
80
90
VIN = 4.0 V
VENABLE = 0 to 4.0 V
5
0
3.0
2.0
IOUT = 30 mA
COUT = 1.0 F
1.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
t, TIME (s)
t, TIME (ms)
Figure 4. Line Transient Response
Figure 5. Enable Response
0.9 1.0
70
30
0
COUT = 1.0 F
VOUT = 3.0 V
VIN = 4.0 V
50
0
−50
−100
10
0
0
100
60
100
OUTPUT VOLTAGE
DEVIATION (mV)
2
VIN = 5.0 V
VOUT = 3.0 V
42.5
VOUT, OUTPUT
VOLTAGE (V)
OUTPUT VOLTAGE
DEVIATION (mV)
VIN, INPUT
VOLTAGE (V)
0
RIPPLE REJECTION (dB)
IQ, QUIESCENT CURRENT (A)
45
0
50
100
150
200
250
300
350
400
450
60
50
40
30
20
0.01
VIN = 4.5 V + 0.5 VP−P
VOUT = 3.0 V
IOUT = 30 mA
COUT = 1.0 F
0.1
1.0
10
t, TIME (s)
FREQUENCY (kHz)
Figure 6. Load Transient Response
Figure 7. Ripple Rejection/Frequency
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4
100
NCP502, NCV502
VOUT, OUTPUT VOLTAGE (V)
2.995
VIN = 12 V
IOUT = 10 mA
2.99
2.985
VIN = 4.0 V
2.98
2.975
2.97
2.965
2.96
−60
−40
0
−20
20
40
80
60
100
T, TEMPERATURE (°C)
Figure 8. Output Voltage versus Temperature
VOUT, OUTPUT VOLTAGE (V)
3.5
CIN = 1.0 F
COUT = 1.0 F
VENABLE = VIN
3
2.5
2
1.5
1
0.5
0
0
1
2
3
4
6
5
VIN, INPUT VOLTAGE (V)
Figure 9. Output Voltage versus Input Voltage
VIN − VOUT, DROPOUT VOLTAGE (mV)
1200
1000
80 mA LOAD
800
600
40 mA LOAD
400
200
0
10 mA LOAD
−50
−25
0
50
25
75
100
125
T, TEMPERATURE (°C)
Figure 10. Dropout Voltage versus Temperature
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5
NCP502, NCV502
DEFINITIONS
Load Regulation
Line Regulation
The change in output voltage for a change in output
current at a constant temperature.
The change in output voltage for a change in input voltage.
The measurement is made under conditions of low
dissipation or by using pulse technique such that the average
chip temperature is not significantly affected.
Dropout Voltage
The input/output differential at which the regulator output
no longer maintains regulation against further reductions in
input voltage. Measured when the output drops 3.0% below
its nominal. The junction temperature, load current, and
minimum input supply requirements affect the dropout level.
Line Transient Response
Typical over and undershoot response when input voltage
is excited with a given slope.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated at typically 160°C,
the regulator turns off. This feature is provided to prevent
failures from accidental overheating.
Maximum Power Dissipation
The maximum total dissipation for which the regulator
will operate within its specifications.
Quiescent Current
The quiescent current is the current which flows through
the ground when the LDO operates without a load on its
output: internal IC operation, bias, etc. When the LDO
becomes loaded, this term is called the Ground current. It is
actually the difference between the input current (measured
through the LDO input pin) and the output current.
Maximum Package Power Dissipation
The maximum power package dissipation is the power
dissipation level at which the junction temperature reaches
its maximum operating value, i.e. 125°C. Depending on the
ambient power dissipation and thus the maximum available
output current.
APPLICATIONS INFORMATION
A typical application circuit for the NCP502 series is
shown in Figure 1, front page.
threshold are covered in the electrical specification section
of this data sheet. If the enable is not used then the pin should
be connected to Vin.
Input Decoupling (C1)
A 1.0 F capacitor either ceramic or tantalum is
recommended and should be connected close to the NCP502
package. Higher values and lower ESR will improve the
overall line transient response. If large line or load transients
are not expected, then it is possible to operate the regulator
without the use of a capacitor.
TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K
Hints
Please be sure the Vin and GND lines are sufficiently
wide. When the impedance of these lines is high, there is a
chance to pick up noise or cause the regulator to
malfunction.
Set external components, especially the output capacitor,
as close as possible to the circuit, and make leads as short as
possible.
Output Decoupling (C2)
The NCP502 is a stable regulator and does not require any
specific Equivalent Series Resistance (ESR) or a minimum
output current. Capacitors exhibiting ESRs ranging from a
few m up to 5.0 can thus safely be used. The minimum
decoupling value is 1.0 F and can be augmented to fulfill
stringent load transient requirements. The regulator accepts
ceramic chip capacitors as well as tantalum devices. Larger
values improve noise rejection and load regulation transient
response.
TDK capacitor: C2012X5R1C105K, C1608X5R1A105K,
or C3216X7R1C105K
Thermal
As power across the NCP502 increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material and also the ambient
temperature effect the rate of temperature rise for the part.
This is stating that when the NCP502 has good thermal
conductivity through the PCB, the junction temperature will
be relatively low with high power dissipation applications.
Enable Operation
The enable pin will turn on the regulator when pulled high
and turn off the regulator when pulled low. These limits of
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6
NCP502, NCV502
The maximum dissipation the package can handle is
given by:
Ptot + ƪVin * Ignd (Iout)ƫ ) [Vin * Vout] * Iout
or
T
*TA
PD + J(max)
RJA
P ) Vout * Iout
VinMAX + tot
Ignd ) Iout
If junction temperature is not allowed above the
maximum 125°C, then the NCP502 can dissipate up to
250 mW @ 25°C.
The power dissipated by the NCP502 can be calculated
from the following equation:
If an 80 mA output current is needed then the ground
current from the data sheet is 40A. For an NCP502 (3.0 V),
the maximum input voltage will then be 6.12 V.
ORDERING INFORMATION
Nominal
Output Voltage
Marking
NCP502SQ15T2G
1.5
LCC
NCP502SQ18T2G
1.8
LCD
NCP502SQ25T2G
2.5
LCE
NCP502SQ27T2G
2.7
LCF
NCP502SQ28T2G
2.8
LCG
NCP502SQ29T2G
2.9
LJI
NCP502SQ30T2G
3.0
LCH
NCP502SQ31T2G
3.1
LJJ
NCP502SQ33T2G
3.3
LCI
NCP502SQ34T2G
3.4
LJK
NCP502SQ35T2G
3.5
LGO
NCP502SQ36T2G
3.6
LIU
NCP502SQ37T2G
3.7
LJQ
NCP502SQ50T2G
5.0
LCJ
NCP502SN28T1G
2.8
LKD
NCP502SN29T1G
2.9
LJN
NCP502SN30T1G
3.0
LKE
NCP502SN31T1G
3.1
LJO
NCP502SN33T1G
3.3
LKF
NCV502SN33T1G*
3.3
LKF
NCP502SN34T1G
3.4
LJK
NCP502SN35T1G
3.5
LJ6
NCP502SN36T1G
3.6
AC4
NCP502SN37T1G
3.7
LKC
NCP502SN50T1G
5.0
LKG
NCV502SN50T1G*
5.0
LKG
Device
Package
Shipping†
SC70−5
(Pb−Free)
3000 / Tape & Reel
TSOP−5
(Pb−Free)
3000 / Tape & Reel
Additional voltages in 100 mV steps are available upon request by contacting your ON Semiconductor representative.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
SCALE 2:1
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
G
5
4
−B−
S
1
2
DATE 17 JAN 2013
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
B
M
M
N
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
J
GENERIC MARKING
DIAGRAM*
C
K
H
XXXMG
G
SOLDER FOOTPRINT
0.50
0.0197
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
mm Ǔ
ǒinches
STYLE 1:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 2:
PIN 1. ANODE
2. EMITTER
3. BASE
4. COLLECTOR
5. CATHODE
STYLE 3:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. CATHODE 1
STYLE 4:
PIN 1. SOURCE 1
2. DRAIN 1/2
3. SOURCE 1
4. GATE 1
5. GATE 2
STYLE 6:
PIN 1. EMITTER 2
2. BASE 2
3. EMITTER 1
4. COLLECTOR
5. COLLECTOR 2/BASE 1
STYLE 7:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 8:
PIN 1. CATHODE
2. COLLECTOR
3. N/C
4. BASE
5. EMITTER
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. ANODE
5. ANODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42984B
STYLE 5:
PIN 1. CATHODE
2. COMMON ANODE
3. CATHODE 2
4. CATHODE 3
5. CATHODE 4
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SC−88A (SC−70−5/SOT−353)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
NOTE 5
2X
DATE 12 AUG 2020
0.20 C A B
0.10 T
M
2X
0.20 T
5
B
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
C
SIDE VIEW
SEATING
PLANE
END VIEW
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.95
0.037
MILLIMETERS
MIN
MAX
2.85
3.15
1.35
1.65
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
1.9
0.074
5
5
XXXAYWG
G
1
1
Analog
2.4
0.094
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
1.0
0.039
XXX MG
G
Discrete/Logic
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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