NCP5104

NCP5104 High Voltage, Half Bridge Driver The NCP5104 is a High Voltage Power gate Driver providing two outputs for direct drive of 2 N-channel power MOSFETs or IGBTs arranged in a half-bridge configuration. It uses the bootstrap technique to insure a proper drive of the High-side power switch. Features http://onsemi.com MARKING DIAGRAMS 1 SOIC-8 D SUFFIX CASE 751 8 P5104 ALYW G 1 • • • • • • • • • • • • • High Voltage Range: up to 600 V dV/dt Immunity ±50 V/nsec Gate Drive Supply Range from 10 V to 20 V High and Low Drive Outputs Output Source / Sink Current Capability 250 mA / 500 mA 3.3 V and 5 V Input Logic Compatible Up to VCC Swing on Input Pins Extended Allowable Negative Bridge Pin Voltage Swing to -10 V for Signal Propagation Matched Propagation Delays between Both Channels 1 Input with Internal Fixed Dead Time (520 ns) Under VCC LockOut (UVLO) for Both Channels Pin to Pin Compatible with Industry Standards These are Pb-Free Devices 1 PDIP-8 P SUFFIX CASE 626 NCP5104 A L or WL Y or YY W or WW G or G NCP5104 AWLG YYWW Typical Applications • Half-Bridge Power Converters = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package PINOUT INFORMATION VCC IN SD GND 1 2 3 4 8 7 6 5 VBOOT DRV_HI BRIDGE DRV_LO 8 Pin Package ORDERING INFORMATION Device NCP5104PG NCP5104DR2G Package PDIP-8 (Pb-Free) SOIC-8 (Pb-Free) Shipping† 50 Units / Rail 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2008 1 March, 2008 - Rev. 2 Publication Order Number: NCP5104/D NCP5104 Vbulk + C1 D4 Q1 C3 GND NCP1395 U1 8 VBOOT Vcc 2 7 IN DRV_HI 3 6 SD Bridge 4 5 GND DRV_LO 1 NCP5104 GND GND D3 GND U2 R1 C4 Lf OutD2 Q2 C6 T1 D1 L1 + C3 Out+ GND Vcc GND Figure 1. Typical Application Resonant Converter (LLC type) + Vbulk C1 D4 Q1 C3 GND 1 2 3 4 T1 U1 8 VBOOT Vcc 7 IN DRV_HI 6 Bridge SD 5 GND DRV_LO NCP5104 C4 D1 C5 L1 + C3 OutD2 C6 Q2 GND D3 GND U2 R1 Out+ GND Vcc SG3526 MC34025 TL594 NCP1561 GND GND Figure 2. Typical Application Half Bridge Converter VCC VCC UV DETECT PULSE TRIGGER LEVEL SHIFTER SQ RQ UV DETECT VBOOT DRV_HI IN DEAD TIME GENERATION BRIDGE VCC GND GND SD DELAY DRV_LO GND GND GND Figure 3. Detailed Block Diagram http://onsemi.com 2 NCP5104 PIN DESCRIPTION Pin Name VCC IN Description Low Side and Main Power Supply Logic Input MAXIMUM RATINGS Rating VCC VCC_transient VBOOT VBRIDGE VBRIDGE VBOOT-VBRIDGE VDRV_HI VDRV_LO dVBRIDGE/dt VIN, VSD RqJA TJ_max Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á SD Logic Input for Shutdown Ground GND DRV_LO VBOOT Low Side Gate Drive Output Bootstrap Power Supply DRV_HI High Side Gate Drive Output BRIDGE Bootstrap Return or High Side Floating Supply Return Symbol Main power supply voltage Main transient power supply voltage: IVCC_max = 5 mA during 10 ms VHV: High Voltage BOOT Pin VHV: High Voltage BRIDGE pin Allowable Negative Bridge Pin Voltage for IN Signal Propagation to DRV_LO VHV: Floating supply voltage VHV: High side output voltage Low side output voltage Allowable output slew rate Inputs IN & SD ESD Capability: - HBM model (all pins except pins 6-7-8 in 8) - Machine model (all pins except pins 6-7-8) Latch up capability per JEDEC JESD78 Power dissipation and Thermal characteristics PDIP-8: Thermal Resistance, Junction-to-Air SO-8: Thermal Resistance, Junction-to-Air Maximum Operating Junction Temperature 23 -10 50 2 200 100 178 Value Unit V V V V V V V V V/ns V kV V -0.3 to 20 -1 to 620 -1 to 600 -0.3 to 20 VBRIDGE - 0.3 to VBOOT + 0.3 -0.3 to VCC + 0.3 -1.0 to VCC + 0.3 °C/W +150 °C http://onsemi.com 3 NCP5104 ELECTRICAL CHARACTERISTIC (VCC = Vboot = 15 V, VGND = Vbridge, -40°C < TJ < 125°C, Outputs loaded with 1 nF) TJ -40°C to 125°C Rating OUTPUT SECTION Output high short circuit pulsed current VDRV = 0 V, PW v 10 ms (Note 1) Output low short circuit pulsed current VDRV = Vcc, PW v 10 ms (Note 1) Output resistor (Typical value @ 25°C) Source Output resistor (Typical value @ 25°C) Sink High level output voltage, VBIAS-VDRV_XX @ IDRV_XX = 20 mA Low level output voltage VDRV_XX @ IDRV_XX = 20 mA DYNAMIC OUTPUT SECTION Turn-on propagation delay (Vbridge = 0 V) (Note 2) Turn-off propagation delay (Vbridge = 0 V or 50 V) (Note 3) Shutdown propagation delay, when Shutdown is enabled Shutdown propagation delay, when Shutdown is disabled Output voltage rise time (from 10% to 90% @ VCC = 15 V) with 1 nF load Output voltage fall time (from 90% to 10% @ VCC = 15 V) with 1 nF load Propagation delay matching between the High side and the Low side @ 25°C (Note 4) Internal fixed dead time (Note 5) INPUT SECTION Low level input voltage threshold Input pull-down resistor (VIN < 0.5 V) High level input voltage threshold Logic “1” input bias current @ VIN = 5 V @ 25°C Logic “0” input bias current @ VIN = 0 V @ 25°C SUPPLY SECTION Vcc UV Start-up voltage threshold Vcc UV Shut-down voltage threshold Hysteresis on Vcc Vboot Start-up voltage threshold reference to bridge pin (Vboot_stup = Vboot - Vbridge) Vboot UV Shut-down voltage threshold Hysteresis on Vboot Leakage current on high voltage pins to GND (VBOOT = VBRIDGE = DRV_HI = 600 V) Consumption in active mode (Vcc = Vboot, fsw = 100 kHz and 1 nF load on both driver outputs) Consumption in inhibition mode (Vcc = Vboot) Vcc current consumption in inhibition mode Vboot current consumption in inhibition mode 1. 2. 3. 4. 5. Vcc_stup Vcc_shtdwn Vcc_hyst Vboot_stup Vboot_shtdwn Vboot_shtdwn IHV_LEAK ICC1 ICC2 ICC3 ICC4 8.0 7.3 0.3 8.0 7.3 0.3 8.9 8.2 0.7 8.9 8.2 0.7 5 4 250 200 50 9.8 9.0 9.8 9.0 40 5 400 V V V V V V mA mA mA mA mA VIN RIN VIN IIN+ IIN2.3 200 5 0.8 25 2.0 V kW V mA mA tON tOFF tsd_en tsd_dis tr tf Dt DT 400 620 100 100 620 85 35 10 520 800 170 170 800 160 75 45 650 ns ns ns ns ns ns ns ns IDRVsource IDRVsink ROH ROL VDRV_H VDRV_L 250 500 30 10 0.7 0.2 60 20 1.6 0.6 mA mA W W V V Symbol Min Typ Max Units Parameter guaranteed by design. TON = TOFF + DT Turn-off propagation delay @ Vbridge = 600 V is guaranteed by design. See characterization curve for Dt parameters variation on the full range temperature. Timing diagram definition see: Figure 4, Figure 5 and Figure 6. http://onsemi.com 4 NCP5104 IN SD DRV_HI DRV_LO Figure 4. Input/Output Timing Diagram Note: DRV_HI output is in phase with the input IN 50% 50% ton Dead time DRV_HI toff tf tr toff tf 90% 90% 10% 10% Dead time tr 90% ton 90% DRV_LO 10% Ton = Toff + DT 10% Figure 5. Timing Definitions http://onsemi.com 5 NCP5104 IN 50% 50% toff_HI DeadTime1 DRV_HI 10% toff_LO DeadTime2 90% DRV_LO 90% Matching Delay1=toff_HI-toff_LO Matching Delay 2=(toff_LO+DT1)-(toff_HI+DT2) 10% Figure 6. Matching Propagation Delay Definition 50% SD tsd_en 90% 50% tsd_dis DRV_HI DRV_LO 10% Figure 7. Shutdown Waveform Definition http://onsemi.com 6 NCP5104 CHARACTERIZATION CURVES 800 TON, PROPAGATION DELAY (ns) 750 700 650 600 550 TON High Side 500 450 400 10 12 14 16 VCC, VOLTAGE (V) 18 20 TON Low Side TON, PROPAGATION DELAY (ns) 900 850 800 750 700 650 600 550 500 450 400 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 TON High Side TON Low Side Figure 8. Turn ON Propagation Delay vs. Supply Voltage (VCC = VBOOT) 160 TOFF, PROPAGATION DELAY (ns) 140 120 100 80 60 40 20 0 10 12 14 16 VCC, VOLTAGE (V) 18 20 TOFF Low Side TOFF, PROPAGATION DELAY (ns) TOFF High Side 160 140 120 100 80 60 40 20 0 -40 Figure 9. Turn ON Propagation Delay vs. Temperature TOFF High Side TOFF Low Side -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 Figure 10. Turn OFF Propagation Delay vs. Supply Voltage (VCC = VBOOT) 800 TOFF, PROPAGATION DELAY (ns) TON, PROPAGATION DELAY (ns) 700 600 500 400 300 200 100 0 0 10 20 30 40 50 VBRIDGE VOLTAGE (V) 160 140 120 100 80 60 40 20 0 0 Figure 11. Turn OFF Propagation Delay vs. Temperature 10 20 30 40 50 VBRIDGE VOLTAGE (V) Figure 12. High Side Turn ON Propagation Delay vs. VBRIDGE Voltage (VCC = VBOOT) Figure 13. High Side Turn OFF Propagation Delay vs. VBRIDGE Voltage (VCC = VBOOT) http://onsemi.com 7 NCP5104 CHARACTERIZATION CURVES 160 tr Low Side TON, RISETIME (ns) 140 120 100 80 60 40 20 10 12 14 16 VCC, VOLTAGE (V) 18 20 0 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 tr Low Side tr High Side 160 140 TON, RISETIME (ns) 120 100 80 60 40 20 0 tr High Side Figure 14. Turn ON Risetime vs. Supply Voltage (VCC = VBOOT) 80 70 TOFF, FALLTIME (ns) TOFF, FALLTIME (ns) 60 50 tf Low Side 40 30 20 10 0 10 12 14 16 VCC, VOLTAGE (V) 18 20 tf High Side 60 50 40 30 20 10 0 -40 Figure 15. Turn ON Risetime vs. Temperature tf High Side tf Low Side -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 Figure 16. Turn OFF Falltime vs. Supply Voltage (VCC = VBOOT) PROPAGATION DELAY MATCHING (ns) 20 15 10 5 0 -5 -10 -15 -20 -40 -20 0 20 40 60 80 100 120 400 -40 Delay Matching 2 Delay Matching 1 DEAD TIME (ns) 550 600 Figure 17. Turn OFF Falltime vs. Temperature 500 450 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. Propagation Delay Matching Between High Side and Low Side Driver vs. Temperature http://onsemi.com 8 Figure 19. Dead Time vs. Temperature NCP5104 CHARACTERIZATION CURVES 1.4 LOW LEVEL INPUT VOLTAGE THRESHOLD (V) 10 12 14 16 18 20 1.2 1.0 0.8 0.6 0.4 0.2 0 VCC, VOLTAGE (V) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 LOW LEVEL INPUT VOLTAGE THRESHOLD (V) Figure 20. Low Level Input Voltage Threshold vs. Supply Voltage (VCC = VBOOT) 2.5 HIGH LEVEL INPUT VOLTAGE THRESHOLD (V) HIGH LEVEL INPUT VOLTAGE THRESHOLD (V) 2.5 Figure 21. Low Level Input Voltage Threshold vs. Temperature 2.0 2.0 1.5 1.5 1.0 1.0 0.5 0 10 12 14 16 VCC, VOLTAGE (V) 18 20 0.5 0 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 Figure 22. High Level Input Voltage Threshold vs. Supply Voltage (VCC = VBOOT) 4.0 LOGIC “0” INPUT CURRENT (mA) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 10 12 14 16 VCC, VOLTAGE (V) 18 20 LOGIC “0” INPUT CURRENT (mA) 10 Figure 23. High Level Input Voltage Threshold vs. Temperature 8.0 6.0 4.0 2.0 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 24. Logic “0” Input Current vs. Supply Voltage (VCC = VBOOT) Figure 25. Logic “0” Input Current vs. Temperature http://onsemi.com 9 NCP5104 CHARACTERIZATION CURVES 8 LOGIC “1” INPUT CURRENT (mA) 7 6 5 4 3 2 1 0 10 12 14 16 VCC, VOLTAGE (V) 18 20 LOGIC “1” INPUT CURRENT (mA) 10 8.0 6.0 4.0 2.0 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 26. Logic “1” Input Current vs. Supply Voltage (VCC = VBOOT) 1.0 LOW LEVEL OUTPUT VOLTAGE (V) LOW LEVEL OUTPUT VOLTAGE THRESHOLD (V) 1.0 Figure 27. Logic “1” Input Current vs. Temperature 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0 10 12 14 16 VCC, VOLTAGE (V) 18 20 0.2 0 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 Figure 28. Low Level Output Voltage vs. Supply Voltage (VCC = VBOOT) 1.6 HIGH LEVEL OUTPUT VOLTAGE (V) HIGH LEVEL OUTPUT VOLTAGE THRESHOLD (V) 1.0 Figure 29. Low Level Output Voltage vs. Temperature 1.2 0.8 0.6 0.8 0.4 0.4 0.2 0 -40 0 10 12 14 16 VCC, VOLTAGE (V) 18 20 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 Figure 30. High Level Output Voltage vs. Supply Voltage (VCC = VBOOT) Figure 31. High Level Output Voltage vs. Temperature http://onsemi.com 10 NCP5104 CHARACTERIZATION CURVES 400 OUTPUT SOURCE CURRENT (mA) 350 300 Isrc Low Side 250 200 150 100 50 0 10 12 14 16 VCC, VOLTAGE (V) 18 20 Isrc High Side OUTPUT SOURCE CURRENT (mA) 400 350 300 250 200 150 100 50 0 -40 -20 0 20 40 60 80 100 120 Isrc Low Side Isrc High Side TEMPERATURE (°C) Figure 32. Output Source Current vs. Supply Voltage (VCC = VBOOT) Figure 33. Output Source Current vs. Temperature 600 Isink High Side OUTPUT SINK CURRENT (mA) OUTPUT SINK CURRENT (mA) 500 Isink Low Side 400 300 200 100 0 10 12 14 16 18 20 VCC, VOLTAGE (V) 600 Isink High Side 500 400 300 200 100 0 -40 -20 Isink Low Side 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 34. Output Sink Current vs. Supply Voltage (VCC = VBOOT) HIGH SIDE LEAKAGE CURRENT ON HV PINS TO GND (mA) 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 0 100 200 300 400 500 HV PINS VOLTAGE (V) LEAKAGE CURRENT ON HIGH VOLTAGE PINS (600 V) to GND (mA) 20 Figure 35. Output Sink Current vs. Temperature 15 10 5.0 600 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 36. Leakage Current on High Voltage Pins (600 V) to Ground vs. VBRIDGE Voltage (VBRIDGE = VBOOT = VDRV_HI) http://onsemi.com 11 Figure 37. Leakage Current on High Voltage Pins (600 V) to Ground vs. Temperature (VBRIDGE = VBOOT = VDRv_HI = 600 V) NCP5104 CHARACTERIZATION CURVES 100 VBOOT SUPPLY CURRENT (mA) VBOOT CURRENT SUPPLY (mA) 0 4.0 8.0 12 16 20 100 80 80 60 60 40 40 20 0 VBOOT, VOLTAGE (V) 20 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 38. VBOOT Supply Current vs. Bootstrap Supply Voltage (VCC = VBOOT) 240 VCC SUPPLY CURRENT (mA) 200 160 120 80 40 0 0 4.0 8.0 12 16 20 VCC, VOLTAGE (V) VCC CURRENT SUPPLY (mA) 400 350 300 250 200 150 100 50 0 -40 Figure 39. VBOOT Supply Current vs. Temperature -20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 40. VCC Supply Current vs. VCC Supply Voltage (VCC = VBOOT) 10 UVLO STARTUP VOLTAGE (V) 9.8 9.6 9.4 9.2 9.0 8.8 8.6 8.4 8.2 8.0 -40 VBOOT UVLO Startup VCC UVLO Startup UVLO SHUTDOWN VOLTAGE (V) 9.0 8.8 8.6 8.4 8.2 8.0 7.8 7.6 7.4 Figure 41. VCC Supply Current vs. Temperature VCC UVLO Shutdown VBOOT UVLO Shutdown -20 0 20 40 60 80 100 120 7.2 7.0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 42. UVLO Startup Voltage vs. Temperature Figure 43. UVLO Shutdown Voltage vs. Temperature http://onsemi.com 12 NCP5104 CHARACTERIZATION CURVES 25 ICC+ IBOOT CURRENT SUPPLY (mA) ICC+ IBOOT CURRENT SUPPLY (mA) CLOAD = 1 nF/Q = 15 nC 20 40 35 30 25 20 15 10 5.0 0 0 100 200 300 400 500 600 0 100 SWITCHING FREQUENCY (kHz) 200 300 400 500 SWITCHING FREQUENCY (kHz) 600 RGATE = 22 R CLOAD = 2.2 nF/Q = 33 nC RGATE = 0 R RGATE = 10 R 15 10 5.0 RGATE = 0 R to 22 R 0 Figure 44. ICC1 Consumption vs. Switching Frequency with 15 nC Load on Each Driver @ VCC = 15 V 60 ICC+ IBOOT CURRENT SUPPLY (mA) ICC+ IBOOT CURRENT SUPPLY (mA) CLOAD = 3.3 nF/Q = 50 nC 50 RGATE = 10 R 40 30 20 10 0 0 100 200 300 400 500 600 SWITCHING FREQUENCY (kHz) RGATE = 22 R RGATE = 0 R 80 70 60 50 Figure 45. ICC1 Consumption vs. Switching Frequency with 33 nC Load on Each Driver @ VCC = 15 V CLOAD = 6.6 nF/Q = 100 nC RGATE = 0 R RGATE = 10 R 40 RGATE = 22 R 30 20 10 0 0 100 200 300 400 500 SWITCHING FREQUENCY (kHz) 600 Figure 46. ICC1 Consumption vs. Switching Frequency with 50 nC Load on Each Driver @ VCC = 15 V Figure 47. ICC1 Consumption vs. Switching Frequency with 100 nC Load on Each Driver @ VCC = 15 V http://onsemi.com 13 NCP5104 PACKAGE DIMENSIONS SOIC-8 NB CASE 751-07 ISSUE AJ -XA 8 5 B 1 4 S 0.25 (0.010) M Y M -YG C -ZH D 0.25 (0.010) M SEATING PLANE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 N X 45 _ 0.10 (0.004) M ZY S J X S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 14 NCP5104 PACKAGE DIMENSIONS 8 LEAD PDIP CASE 626-05 ISSUE L 8 5 -B1 4 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --10_ 0.030 0.040 F NOTE 2 -AL C -TSEATING PLANE J N D K M M TA B H G 0.13 (0.005) M M ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT:  Literature Distribution Center for ON Semiconductor  P.O. Box 5163, Denver, Colorado 80217 USA  Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada  Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada  Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free  USA/Canada Europe, Middle East and Africa Technical Support:  Phone: 421 33 790 2910 Japan Customer Focus Center  Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca Sales Representative http://onsemi.com 15 NCP5104/D