NCP512
Voltage Regulator - CMOS,
Low Iq
80 mA
Features
•
•
•
•
•
•
Low Quiescent Current of 40 A Typical
Low Dropout Voltage of 180 mV at 80 mA and 3.0 V Vout
Low Output Voltage Option
Output Voltage Accuracy of 2.0%
Industrial Temperature Range of −40°C to 85°C
These are Pb−Free Devices
MARKING
DIAGRAM
5
1
SC70−5/SC−88A/
SOT−353
SQ SUFFIX
CASE 419A
xxx M G
G
xxx = Device Code
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
PIN CONNECTIONS
Typical Applications
•
•
•
•
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M
The NCP512 series of fixed output linear regulators are designed for
handheld communication equipment and portable battery powered
applications which require low quiescent. The NCP512 series features
an ultra−low quiescent current of 40 A. Each device contains a
voltage reference unit, an error amplifier, a PMOS power transistor,
resistors for setting output voltage, current limit, and temperature limit
protection circuits.
The NCP512 has been designed to be used with low cost ceramic
capacitors. The device is housed in the micro−miniature SC70−5
surface mount package. Standard voltage versions are 1.3, 1.5, 1.8,
2.2, 2.5, 2.7, 2.8, 3.0, 3.1, 3.3, and 5.0 V. Other voltages are available
in 100 mV steps.
Cellular Phones
Battery Powered Consumer Products
Hand−Held Instruments
Camcorders and Cameras
Vin
1
GND
2
Enable
3
5
Vout
4
N/C
(Top View)
Battery or
Unregulated
Voltage
C1
+
1
+
2
ON
3
Vout
5
C2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
4
OFF
This device contains 86 active transistors
Figure 1. Typical Application Diagram
© Semiconductor Components Industries, LLC, 2009
October, 2019 − Rev. 15
1
Publication Order Number:
NCP512/D
NCP512
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PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
1
Vin
Description
2
GND
3
Enable
4
N/C
No internal connection.
5
Vout
Regulated output voltage.
Positive power supply input voltage.
Power supply ground.
This input is used to place the device into low−power standby. When this input is pulled low, the device is
disabled. If this function is not used, Enable should be connected to Vin.
MAXIMUM RATINGS
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Rating
Symbol
Value
Unit
Vin
0 to 6.0
V
Enable Voltage
Enable
−0.3 to Vin +0.3
V
Output Voltage
Vout
−0.3 to Vin +0.3
V
Power Dissipation and Thermal Characteristics
Power Dissipation
Thermal Resistance, Junction−to−Ambient
PD
RJA
Internally Limited
400
W
°C/W
Operating Junction Temperature
TJ
+150
°C
Maximum Junction Temperature
TJ(max)
+150
°C
Operating Ambient Temperature
TA
−40 to +85
°C
Storage Temperature
Tstg
−55 to +150
°C
Input Voltage
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per MIL−STD−883, Method 3015
Machine Model Method 200 V
2. Latch−up capability (85°C) "200 mA DC with trigger voltage.
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2
NCP512
ELECTRICAL CHARACTERISTICS (Vin = Vout(nom.) + 1.0 V, Venable = Vin, Cin = 1.0 F, Cout = 1.0 F, TJ = 25°C, unless
otherwise noted.)
Characteristic
Symbol
Output Voltage (TA = 25°C, Iout = 10 mA)
1.3 V
1.5 V
1.8 V
2.2 V
2.5 V
2.7 V
2.8 V
3.0 V
3.1 V
3.3 V
5.0 V
Output Voltage (TA = −40°C to 85°C, Iout = 10 mA)
1.3 V
1.5 V
1.8 V
2.2 V
2.5 V
2.7 V
2.8 V
3.0 V
3.1 V
3.3 V
5.0 V
Line Regulation (Iout = 10 mA)
1.3 V−4.4 V (Vin = Vout(nom.) + 1.0 V to 6.0 V)
4.5 V−5.0 V (Vin = 5.5 V to 6.0 V)
Vout
Vout
Regline
Load Regulation (Iout = 1.0 mA to 80 mA)
Output Current (Vout = (Vout at Iout = 80 mA) −3%)
1.3 V−3.9 V (Vin = Vout(nom.) + 2.0 V)
4.0 V−5.0 V (Vin = 6.0 V)
Regload
Io(nom.)
Dropout Voltage (TA = −40°C to 85°C, Iout = 80 mA,
Measured at Vout = Vout(nom) −3.0%)
1.3 V
1.5 V
1.8 V
2.2 V
2.5 V
2.7 V
2.8 V
3.0 V
3.1 V
3.3 V
5.0 V
Vin−Vout
Ground Current (Enable Input = Vin, Iout = 1.0 mA to Io(nom.))
Quiescent Current (TA = −40°C to 85°C)
(Enable Input = 0 V)
(Enable Input = Vin, Iout = 1.0 mA to Io(nom.))
IGND
IQ
Output Short Circuit Current (Vout = 0 V)
1.3 V−3.9 V (Vin = Vout(nom.) + 2.0 V)
4.0 V−5.0 V (Vin = 6.0 V)
Iout(max)
Output Voltage Noise (f = 100 Hz to 100 kHz, Iout = 30 mA, Cout = 1 F)
Ripple Rejection (f = 1.0 kHz, 60 mA)
Enable Input Threshold Voltage
(Voltage Increasing, Output Turns On, Logic High)
(Voltage Decreasing, Output Turns Off, Logic Low)
Vn
RR
Vth(en)
Output Voltage Temperature Coefficient
TC
Min
Typ
Max
1.261
1.455
1.746
2.134
2.425
2.646
2.744
2.94
3.038
3.234
4.900
1.3
1.5
1.8
2.2
2.5
2.7
2.8
3.0
3.1
3.3
5.0
1.339
1.545
1.854
2.266
2.575
2.754
2.856
3.06
3.162
3.366
5.100
1.261
1.455
1.746
2.134
2.425
2.619
2.716
2.910
3.007
3.201
4.900
1.3
1.5
1.8
2.2
2.5
2.7
2.8
3.0
3.1
3.3
5.0
1.339
1.545
1.854
2.266
2.575
2.781
2.884
3.09
3.193
3.399
5.100
−
−
1.0
1.0
3.0
3.0
−
0.3
0.8
80
80
200
200
−
−
V
V
mV/V
−
−
−
−
−
−
−
−
−
−
520
450
350
240
220
200
200
180
170
160
120
700
550
450
300
300
300
300
300
300
300
300
−
40
90
−
−
0.1
40
1.0
90
150
150
250
250
400
400
−
−
180
50
−
−
1.3
−
−
−
−
0.3
−
"100
−
A
A
mA
T
*TA
PD + J(max)
RJA
4. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
3
mV/mA
mA
mV
3. Maximum package power dissipation limits must be observed.
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Unit
VRMS
dB
V
ppm/°C
NCP512
3.020
300
NCP512SQ30
Vout, OUTPUT VOLTAGE (V)
Vin − Vout, DROPOUT VOLTAGE (mV)
TYPICAL CHARACTERISTICS
250
Io = 80 mA
200
150
Io = 40 mA
100
50
Io = 10 mA
0
−50
−25
0
25
50
75
100
3.015
Vin = 6.0 V
3.010
Vin = 4.0 V
3.005
3.000
2.995
2.990
2.985
−60
125
−40
−20
0
TEMPERATURE (°C)
Iq, QUIESCENT CURRENT (A)
Iq, QUIESCENT CURRENT (A)
44
42
40
−60
100
−40
−20
0
20
40
60
80
Vout = 3.0 V
Cin = 1.0 F
Cout = 1.0 F
TA = 25°C
50
40
30
20
10
0
0
100
1.0
2.0
3.0
4.0
5.0
6.0
7.0
Vin, INPUT VOLTAGE (V)
TEMPERATURE (°C)
Figure 5. Quiescent Current vs. Input Voltage
Figure 4. Quiescent Current vs. Temperature
60
70
Vout = 3.0 V
Cin = 1.0 F
Cout = 1.0 F
Iout = 30 mA
TA = 25°C
30
20
10
1.0
Vin = 4.0 V
Cout = 1.0 F
Iout = 30 mA
60
RIPPLE REJECTION (dB)
Ignd, GROUND CURRENT (A)
80
Figure 3. Output Voltage vs. Temperature
Iout = 0 mA
Vin = 4.0 V
Vout = 3.0 V
46
0
0
60
60
48
40
40
TEMPERATURE (°C)
Figure 2. Dropout Voltage vs. Temperature
50
20
2.0
3.0
4.0
5.0
6.0
50
40
30
20
10
0
100
7.0
1.0k
10k
100k
Vin, INPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 6. Ground Pin Current vs. Input Voltage
Figure 7. Ripple Rejection vs. Frequency
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4
1.0M
NCP512
TYPICAL CHARACTERISTICS
7
6
5
Vin, INPUT
VOLTAGE (V)
Vin = 4.0 V
Cout = 1.0 F
Iout = 30 mA
4
3
2
1
0
10
1.0k
100
10k
100k
1.0M
OUTPUT VOLTAGE
DEVIATION (mV)
OUTPUT VOLTAGE NOISE (V/ǰHz)
7
6
Cout = 1.0 F
Iout = 10 mA
5
4
3
200
100
0
−100
0
50
100 150 200 250
Figure 9. Line Transient Response
Figure 8. Output Noise Density
Vin, INPUT
VOLTAGE (V)
6
60 mA
0
200
OUTPUT VOLTAGE
(V)
0
Iout = 1 mA to 60 mA
Vin = 4.0 V
Cin = 1.0 F
Cout = 1.0 F
−100
−200
0
4
2
0
4
100
100
200
300
400
500
600
700
Iout = 10 mA
Vin = 4.0 V
Cin = 1.0 F
Cout = 1.0 F
3
2
1
0
0
800
0.2
0.4
0.6 0.8
1.0
1.2 1.4
1.6
TIME (s)
TIME (ms)
Figure 10. Load Transient Response
Figure 11. Turn−on Response
3.5
Vout, OUTPUT VOLTAGE (V)
Io, OUTPUT
CURRENT (mA)
500
TIME (s)
FREQUENCY (Hz)
OUTPUT VOLTAGE
DEVIATION (mV)
300 350 400 450
3.0
2.5
2.0
1.5
1.0
0.5
0
0
1.0
2.0
3.0
4.0
5.0
Vin, INPUT VOLTAGE (V)
Figure 12. Output Voltage vs. Input Voltage
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5
6.0
1.8
2.0
NCP512
DEFINITIONS
Load Regulation
Line Regulation
The change in output voltage for a change in output
current at a constant temperature.
The change in output voltage for a change in input voltage.
The measurement is made under conditions of low
dissipation or by using pulse technique such that the average
chip temperature is not significantly affected.
Dropout Voltage
The input/output differential at which the regulator output
no longer maintains regulation against further reductions in
input voltage. Measured when the output drops 3.0% below
its nominal. The junction temperature, load current, and
minimum input supply requirements affect the dropout level.
Line Transient Response
Typical over and undershoot response when input voltage
is excited with a given slope.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated at typically 160°C,
the regulator turns off. This feature is provided to prevent
failures from accidental overheating.
Maximum Power Dissipation
The maximum total dissipation for which the regulator
will operate within its specifications.
Quiescent Current
The quiescent current is the current which flows through
the ground when the LDO operates without a load on its
output: internal IC operation, bias, etc. When the LDO
becomes loaded, this term is called the Ground current. It is
actually the difference between the input current (measured
through the LDO input pin) and the output current.
Maximum Package Power Dissipation
The maximum power package dissipation is the power
dissipation level at which the junction temperature reaches
its maximum operating value, i.e. 125°C. Depending on the
ambient power dissipation and thus the maximum available
output current.
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6
NCP512
APPLICATIONS INFORMATION
Set external components, especially the output capacitor,
as close as possible to the circuit, and make leads as short as
possible.
A typical application circuit for the NCP512 series is
shown in Figure 1, front page.
Input Decoupling (C1)
A 1.0 F capacitor either ceramic or tantalum is
recommended and should be connected close to the NCP512
package. Higher values and lower ESR will improve the
overall line transient response.
TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K
Thermal
As power across the NCP512 increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material and also the ambient
temperature effect the rate of temperature rise for the part.
This is stating that when the NCP512 has good thermal
conductivity through the PCB, the junction temperature will
be relatively low with high power dissipation applications.
The maximum dissipation the package can handle is
given by:
Output Decoupling (C2)
The NCP512 is a stable regulator and does not require any
specific Equivalent Series Resistance (ESR) or a minimum
output current. Capacitors exhibiting ESRs ranging from a
few m up to 5.0 can thus safely be used. The minimum
decoupling value is 1.0 F and can be augmented to fulfill
stringent load transient requirements. The regulator accepts
ceramic chip capacitors as well as tantalum capacitors.
Larger values improve noise rejection and load regulation
transient response.
TDK capacitor: C2012X5R1C105K, C1608X5R1A105K,
or C3216X7R1C105K
T
*TA
PD + J(max)
RJA
If junction temperature is not allowed above the
maximum 125°C, then the NCP512 can dissipate up to
250 mW @ 25°C.
The power dissipated by the NCP512 can be calculated
from the following equation:
Enable Operation
The enable pin will turn on the regulator when pulled high
and turn off the regulator when pulled low. These limits of
threshold are covered in the electrical specification section
of this data sheet. If the enable is not used then the pin should
be connected to Vin.
Ptot + ƪVin * Ignd (Iout)ƫ ) [Vin * Vout] * Iout
or
P ) Vout * Iout
VinMAX + tot
Ignd ) Iout
If an 80 mA output current is needed then the ground
current from the data sheet is 40 A. For an NCP512 (3.0 V),
the maximum input voltage will then be 6.12 V.
Hints
Please be sure the Vin and GND lines are sufficiently
wide. When the impedance of these lines is high, there is a
chance to pick up noise or cause the regulator to
malfunction.
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7
NCP512
ORDERING INFORMATION
Device
NCP512SQ13T1G
Nominal
Output Voltage*
Marking
1.3
LIW
1.5
LCK
1.8
LCL
2.2
LIA
2.5
LCM
2.7
LCN
2.8
LCO
3.0
LCP
3.1
LFO
3.3
LCQ
5.0
LCR
Package
Shipping†
SC−88A (SOT−353)
(Pb−Free)
3000 Units/
7″ Tape & Reel
NCP512SQ13T2G
NCP512SQ15T1G
NCP512SQ15T2G
NCP512SQ18T1G
NCP512SQ18T2G
NCP512SQ22T1G
NCP512SQ22T2G
NCP512SQ25T1G
NCP512SQ25T2G
NCP512SQ27T1G
NCP512SQ27T2G
NCP512SQ28T1G
NCP512SQ28T2G
NCP512SQ30T1G
NCP512SQ30T2G
NCP512SQ31T1G
NCP512SQ31T2G
NCP512SQ33T1G
NCP512SQ33T2G
NCP512SQ50T1G
NCP512SQ50T2G
*Additional voltages in 100 mV steps are available upon request by contacting your ON Semiconductor representative.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
SCALE 2:1
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
G
5
4
−B−
S
1
2
DATE 17 JAN 2013
DIM
A
B
C
D
G
H
J
K
N
S
3
D 5 PL
0.2 (0.008)
B
M
M
N
INCHES
MIN
MAX
0.071
0.087
0.045
0.053
0.031
0.043
0.004
0.012
0.026 BSC
--0.004
0.004
0.010
0.004
0.012
0.008 REF
0.079
0.087
MILLIMETERS
MIN
MAX
1.80
2.20
1.15
1.35
0.80
1.10
0.10
0.30
0.65 BSC
--0.10
0.10
0.25
0.10
0.30
0.20 REF
2.00
2.20
J
GENERIC MARKING
DIAGRAM*
C
K
H
XXXMG
G
SOLDER FOOTPRINT
0.50
0.0197
XXX = Specific Device Code
M
= Date Code
G
= Pb−Free Package
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
mm Ǔ
ǒinches
STYLE 1:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 2:
PIN 1. ANODE
2. EMITTER
3. BASE
4. COLLECTOR
5. CATHODE
STYLE 3:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. CATHODE 1
STYLE 4:
PIN 1. SOURCE 1
2. DRAIN 1/2
3. SOURCE 1
4. GATE 1
5. GATE 2
STYLE 6:
PIN 1. EMITTER 2
2. BASE 2
3. EMITTER 1
4. COLLECTOR
5. COLLECTOR 2/BASE 1
STYLE 7:
PIN 1. BASE
2. EMITTER
3. BASE
4. COLLECTOR
5. COLLECTOR
STYLE 8:
PIN 1. CATHODE
2. COLLECTOR
3. N/C
4. BASE
5. EMITTER
STYLE 9:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. ANODE
5. ANODE
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42984B
STYLE 5:
PIN 1. CATHODE
2. COMMON ANODE
3. CATHODE 2
4. CATHODE 3
5. CATHODE 4
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SC−88A (SC−70−5/SOT−353)
PAGE 1 OF 1
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