High and Low Side Gate
Driver, High Performance,
700 V, with 3.5 A Source
and 3 A Sink Currents
NCP51530
NCP51530 is a 700 V high side and low side driver with 3.5 A
source & 3 A sink current drive capability for AC−DC power supplies
and inverters. NCP51530 offers best in class propagation delay, low
quiescent current and low switching current at high frequencies of
operation. This device is tailored for highly efficient power supplies
operating at high frequencies. NCP51530 is offered in two versions,
NCP51530A/B. NCP51530A has a typical 60 ns propagation delay,
while NCP51530B has a typical propagation delay of 25 ns.
NCP51530 comes in SOIC8 and DFN10 packages.
www.onsemi.com
MARKING
DIAGRAMS
8
1
SOIC−8
D SUFFIX
CASE 751−07
NCP51530x
ALYW
G
1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
High voltage range: Up to 700 V
NCP51530A: Typical 60 ns Propagation Delay
NCP51530B: Typical 25 ns Propagation Delay
Low Quiescent and Operating Currents
15 ns Max Rise and Fall Time
3.5 A Source / 3 A Sink Currents
Under−voltage Lockout for Both Channels
3.3 V and 5 V Input Logic Compatible
High dv/dt Immunity up to 50 V/ns
Pin to Pin Compatible with Industry Standard Half−bridge ICs.
Matched Propagation Delay (7 ns Max)
High Negative Transient Immunity on Bridge Pin
DFN10 Package Offers Both Improved Creepage and Exposed Pad
NCP51530
x
A
WL
YY
WW
G
High−density SMPS for Servers, Telecom and Industrial
Half/Full−bridge & LLC Converters
Active Clamp Flyback/Forward Converters
Solar Inverters & Motor Controls
Electric Power Steering
51530x
ALYWG
G
= Specific Device Code
= A or B version
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PINOUT INFORMATION
HIN
LIN
GND
LO
Applications
•
•
•
•
•
1
DFN10
MN SUFFIX
CASE 506DJ
VB
HO
HB
VCC
1
8 Pin Package
(Top View)
VCC
HIN
LIN
GND
GND
1
VB
HO
HB
NC
LO
10 Pin DFN Package
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information on page 22 of
this data sheet.
© Semiconductor Components Industries, LLC, 2018
September, 2020 − Rev. 4
1
Publication Order Number:
NCP51530/D
NCP51530
HIN
VB
LIN
HO
GND
HB
LO
VCC
VCC
VB
HIN
HO
LIN
HB
GND
NC
GND
LO
SOIC8
(Top View)
DFN10
(Top View)
Table 1. PIN DESCRIPTION SOIC 8 PACKAGE
Pin Out
Name
Function
1
HIN
High side input
2
LIN
Low side input
3
GND
4
LO
5
VCC
6
HB
High side supply return
7
HO
High side output
8
VB
High side voltage supply
Ground reference
Low side output
Low side and logic supply
Table 2. PIN DESCRIPTION DFN10 PACKAGE
Pin Out
Name
Function
1
VCC
Low side and logic supply
2
HIN
High side input
3
LIN
Low side input
4
GND
Ground reference
5
GND
Ground reference
6
LO
Low side output
7
NC
No Connect
8
HB
High side supply return
9
HO
High side output
10
VB
High side voltage supply
www.onsemi.com
2
NCP51530
VHV
ADRV
LDRV
PWM CONTROLLER
COMP
HIN
VB
LIN
HO
NCP51530
GND
HB
LO
VCC
Figure 1. Simplified Applications Schematic for a Half−Bridge Converter (SOIC8)
www.onsemi.com
3
NCP51530
VHV
VCC
VB
HIN
HO
LIN
HB
GND
NC
GND
LO
VCC
HIN
LIN
GND
GND
VB
HO
HB
NC
LO
LIN 1
HIN 1
LIN 2
Micro Controller
Digital Isolator
HIN 2
Figure 2. Simplified Applications Schematic for a Full Bridge Converter (DFN 10)
www.onsemi.com
4
NCP51530
VCC
VB
UV
Detect
Pulse
Trigg er
HIN
Level
Shifter
S
Q
R
Q
HO
r
UV
DETECT
HB
VCC
LO
DELAY
LIN
r
GND
Figure 3. Internal Block Diagram for NCP51530
Table 3. ABSOLUTE MAXIMUM RATINGS All voltages are referenced to GND pin.
Rating
Symbol
Value
Unit
VCC
−0.3 to 20
V
High side boot pin voltage
VB
−0.3 to 720
V
High side floating voltage
VB−VHB
−0.3 to 20
V
VHO
VHB – 0.3 to VB + 0.3
V
Input voltage range
High side drive output voltage
Low side drive output voltage
Allowable hb slew rate
Drive input voltage
Junction temperature
Storage temperature range
ESD Capability (Note 1)
Human Body Model per JEDEC Standard JESD22−A114E.
Charge Device Model per JEDEC Standard JESD22−C101E.
VLO
−0.3 to VCC + 0.3
V
dVHB/dt
50
V/ns
VLIN,
VHIN
−5 to VCC + 0.3
V
TJ(MAX)
150°
C
TSTG
−55° to 150°
C
4000
1000
Lead Temperature Soldering
Reflow (SMD Styles ONLY), Pb−Free Versions (Note 2)
260
V
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and is tested by the following methods. ESD Human Body Model tested per
AEC−Q100−002(EIA/JESD22−A114)
ESD Charged Device Model tested per AEC−Q100−11(EIA/JESD22−C101E)
Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78
2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
www.onsemi.com
5
NCP51530
Table 4. THERMAL CHARACTERSTICS
Symbol
Value
Unit
Thermal Characteristics, SOIC8 (Note 3)
Thermal Resistance, Junction to Air
Rating
RqJA
183
°C/W
Thermal Characteristics, DFN10
Thermal Resistance, Junction to Air (Note 4)
RqJA
162
°C/W
3. Refer to ELECTRICAL CHARACTERSTICS and APPLICATION INFORMATION for Safe Operating Area.
4. Values based on copper area of 50 mm2 of 1 oz thickness and FR4 PCB substrate.
Table 5. RECOMMENDED OPERATING CONDITIONS
Rating
Input Voltage Range
High Side Floating Voltage
Symbol
Min
Max
Unit
VCC
10
17
V
VB−VHB
10
17
V
High Side Bridge pin Voltage
VHB
−1
700
V
High Side Output Voltage
VHO
VHB
VB
V
High Side Output Voltage
VLO
GND
VCC
V
Input Voltage on LIN and HIN pins
VLIN,
VHIN
GND
VCC−2
V
TJ
−40
125
°C
Operating Junction Temperature Range
Table 6. ELECTRICAL CHARACTERISTICS
(−40°C UVLO &
HO Pulse
1st
0.5
8
8.5
V
9
0.5
Tstartup
V
V
10
ms
LO GATE DRIVER
Low level output voltage
ILO = 100 mA
VLOL
0.125
V
High level output voltage
ILO = −100 mA, VLOH = VCC
−VLO
VLOH
0.150
V
Peak source current
VLO = 0 V
ILOpullup
3.5
A
www.onsemi.com
6
NCP51530
Table 6. ELECTRICAL CHARACTERISTICS
(−40°C 2 mF.
+ 14 V * 0.4 mA ) 15 V * 0.4 mA + 11.6 mW
IBO is the operating current for the high side driver
ICCO is the operating current for the low side driver
2. Power loss of driving external FET (Hard
Switching)
Rgate SELECTION
Rgate are selected to limit the peak gate current during
charging and discharging of the gate capacitance. This
resistance also helps to damp the ringing due to the parasitic
inductances.
For example for a Rgate value of 5 W, the peak source and
sink currents would be limited to the following values.
R gate + 5W
I LO_Source +
I LO_Sink +
R Lgate ) R LOH
V CC
R Lgate ) R LOL
I HO_Source +
I HO_Sink +
V CC
+
V CC * V Dboot
R Lgate ) R HOH
V CC * V Dboot
R Lgate ) R HOL
+
+
6.7 W
15 V
6.8 W
+
P drivers +
Qg is total gate charge of the MOSFET
3. Power loss of driving external FET (Soft
Switching)
+ 2.23 A (eq. 7)
6.7 W
ǒǒQgs * VbootǓ ) ǒQgs * VCCǓǓ * f
(eq. 13)
4. Level shifting losses
(eq. 8)
P levelshifting + ǒV r ) V bǓ * Q * f
(eq. 14)
+ 415 V * 0.5 nC * 100 kHz + 20.75 mW
+ 2.09 A (eq. 9)
15 V * 1 V
6.8 W
P drivers +
+ ǒǒ4 nC * 14 VǓ ) ǒ4 nC * 15 VǓǓ * 100 kHz + 11 mW
+ 2.20 A
14 V
ǒǒQg * VboostǓ ) ǒQg * VCCǓǓf
(eq. 12)
+ ǒǒ30 nC * 14 VǓ ) ǒ30 nC * 15 VǓǓ * 100 kHz + 87 mW
(eq. 6)
15 V
(eq. 11)
Vr is the rail voltage
Q is the substrate charge on the level shifter
5. Total Power Loss (Hard Switching)
(eq. 10)
+ 2.06 A
P total + P driver ) P operating ) P levelshifting
(eq. 15)
+ 11.6 mW ) 87 mW ) 20.75 mW + 119.35 mW
TOTAL POWER DISSIPATION
Total power dissipation of NCP51530 can be calculated as
follows.
1. Static power loss of device (excluding drivers)
while switching at an appropriate frequency.
6. Junction temperature increase
t J + R qJA * P total + 183 * 0.14 + 25° C
www.onsemi.com
21
(eq. 16)
NCP51530
LAYOUT RECOMMENDATIONS
NCP51530 is a high speed and high current high side and
low side driver. To avoid any device malfunction during
device operation, it is very important that there is very low
parasitic inductance in the current switching path. It is very
important that the best layout practices are followed for the
PCB layout of the NCP51530. An example layout is shown
in the figure below. Some of the layout rules to be followed
are listed below.
• Keep the low side drive path LO−Q1−GND as small as
possible. This reduces the parasitic inductance in the
path and hence eliminates ringing on the gate terminal
of the low side MOSFET Q1.
• Keep the high side drive loop HO−Q2−HB as small as
possible. This reduces the parasitic inductance in the
•
•
•
path and hence eliminates ringing on the gate terminal
of the low side MOSFET Q1.
Keep CVCC as near to the VCC pin as possible and the
VCC−CVCC−GND loop as small as possible.
Keep CVB as near to VB pin as possible and
VB−CVB−HB loop as small as possible.
Keep the HB−GND−Q1 loop as small as possible. This
loop has the potential to produce a negative voltage
spike on the HB pin. This negative voltage spike can
cause damage to the driver. This negative spike can
increase the boot capacitor voltage above the maximum
rating and hence cause damage to the driver.
Figure 35. Example Layout
ORDERING INFORMATION
Propagation Delay
(ns)
Input filter
Package
Shipping†
NCP51530ADR2G
60
Yes
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP51530BDR2G
25
No
SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP51530AMNTWG
60
Yes
DFN10 4x4
(Pb−Free)
4000 / Tape & Reel
NCP51530BMNTWG
25
No
DFN10 4x4
(Pb−Free)
4000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
www.onsemi.com
22
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DFN10 4x4, 0.8P
CASE 506DJ
ISSUE O
1
DATE 20 MAY 2016
SCALE 2:1
B
A
D
L
PIN ONE
REFERENCE
2X
L1
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ALTERNATE A−1
0.10 C
ALTERNATE TERMINAL
CONSTRUCTIONS
ÉÉ
ÉÉ
ÇÇ
A1
TOP VIEW
A
DETAIL B
0.10 C
ALTERNATE A−2
DETAIL A
E
0.10 C
2X
L
A3
ALTERNATE B−1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE
TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS
WELL AS THE TERMINALS.
5. FOR DEVICE OPN CONTAINING W OPTION, DETAIL A
ALTERNATE CONSTRUCTION A−2 AND DETAIL B ALTERNATE CONSTRUCTION B−2 ARE NOT APPLICABLE.
ÉÉÉ
ÉÉÉ
ÇÇÇ
EXPOSED Cu
MOLD CMPD
ALTERNATE B−2
DETAIL B
ALTERNATE
CONSTRUCTIONS
10X
0.08 C
NOTE 4
SIDE VIEW
A3
A1
C
SEATING
PLANE
1
D2
10X
L
5
XXXXXX
XXXXXX
ALYWG
G
0.10 C A B
E3
E2
K
6
10
10X
e
b
0.10 C A B
0.05 C
BOTTOM VIEW
RECOMMENDED
MOUNTING FOOTPRINT
NOTE 3
XXXXX
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
10X
3.20
PACKAGE
OUTLINE
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.25
0.35
4.00 BSC
2.90
3.10
4.00 BSC
1.85
2.05
0.375 BSC
0.80 BSC
0.90
−−−
0.35
0.45
0.00
0.15
GENERIC
MARKING DIAGRAM*
0.10 C A B
DETAIL A
DIM
A
A1
A3
b
D
D2
E
E2
E3
e
K
L
L1
0.60
2.15
0.75
4.30
1
0.80
PITCH
DOCUMENT NUMBER:
DESCRIPTION:
10X
0.42
DIMENSIONS: MILLIMETERS
98AON12037G
DFN10 4X4, 0.8P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
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