NCP51820AMNTWG

DATA SHEET www.onsemi.com High Speed Half-Bridge Driver for GaN Power Switches NCP51820 QFN15 4x4, 0.5P CASE 485FN MARKING DIAGRAM 51820A ALYW G G 51820A A L YW G = Specific Device Code = Assembly Site = Wafer Lot Number = Assembly Start Week = Pb−Free Package (Note: Microdot may be in either location) PIN ASSIGNMENT VDDH 1 HOSRC 2 HOSNK 3 SW 4 14 VDD 15 VBST The NCP51820 high−speed, gate driver is designed to meet the stringent requirements of driving enhancement mode (e−mode), high electron mobility transistor (HEMT) and gate injection transistor (GIT), gallium nitrade (GaN) power switches in off−line, half−bridge power topologies. The NCP51820 offers short and matched propagation delays with advanced level shift technology providing −3.5 V to +650 V (typical) common mode voltage range for the high−side drive and −3.5 V to +3.5 V common mode voltage range for the low−side drive. In addition, the device provides stable dV/dt operation rated up to 200 V/ns for both driver output stages in high speed switching applications. To fully protect the gate of the GaN power transistor against excessive voltage stress, both drive stages employ a dedicated voltage regulator to accurately maintain the gate−source drive signal amplitude. The circuit actively regulates the driver’s bias rails and thus protects against potential gate−source over−voltage under various operating conditions. The NCP51820 offers important protection functions such as independent under−voltage lockout (UVLO), monitoring VDD bias voltage and VDDH and VDDL driver bias and thermal shutdown based on die junction temperature of the device. Programmable dead−time control can be configured to prevent cross−conduction. 13 EN 12 HIN NCP51820 (Top View) 11 LIN 10 SGND Features 8 DT PGND LOSNK 7 LOSRC 6 9 5 650 V, Integrated High−Side and Low−Side Gate Drivers Recommended for Soft Switching Applications UVLO Protections for VDD High and Low−Side Drivers Dual TTL Compatible Schmitt Trigger Inputs Split Output Allows Independent Turn−ON/Turn−OFF Adjustment Source Capability: 1 A; Sink Capability: 2 A Separated HO and LO Driver Output Stages 1 ns Rise and Fall Times Optimized for GaN Devices SW and PGND: Negative Voltage Transient up to 3.5 V 200 V/ns dV/dt Rating for all SW and PGND Referenced Circuitry Maximum Propagation Delay of Less Than 50 ns Matched Propagation Delays to Less Than 5 ns User Programmable Dead−Time Control Thermal Shutdown (TSD) VDDL • • • • • • • • • • • • • • ORDERING INFORMATION Device Package Shipping† NCP51820AMNTWG QFN15 (Pb−Free) 4000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Typical Applications • Driving GaN Power Transistors used in Soft Switching Full or • • Half−Bridge, LLC, Active Clamp Flyback or Forward, Totem Pole PFC and Synchronous Rectifier Topologies Industrial Inverters and Motor Drives AC to DC Converters © Semiconductor Components Industries, LLC, 2019 March, 2022 − Rev. 6 1 Publication Order Number: NCP51820/D NCP51820 VDD VDDH HOSRC HOSNK SW POWER STAGE 14 15 VDD VBST VIN 1 13 2 12 NCP51820 3 11 (Top View) 4 10 LIN SGND DT 8 7 PWM mC or DSP HIN PGND 6 LOSNK LOSRC VDDL 5 9 EN Figure 1. Typical Application Schematic VDDH REGULATOR VBST VDD VDD UVLO 8.5V/8V (ON/OFF) EN HIN LIN S R Q HOSRC HOSNK SW SCHMITT TRIGGER INPUT VDDL REGULATOR SHOOT THOUGH PREVENTION CYCLE−By− CYCLE EDGE TRIGGERED SHUTDOWN DEAD−TIME MODE CONTROL VDDL UVLO LO LEVEL SHIFTER DELAY SGND VDDL DRIVER DT HO LEVEL SHIFTER DRIVER VDDH UVLO VDDH LOSRC LOSNK PGND Figure 2. Internal Block Diagram www.onsemi.com 2 NCP51820 VBST VDD 15 14 PIN CONNECTIONS VDDH 1 13 EN HOSRC 2 12 HIN HOSNK 3 11 LIN SW 4 10 SGND NCP51820 (Top View) 7 LOSNK 8 6 LOSRC DT PGND 5 VDDL 9 Figure 3. Pin Assignments – 15 Lead QFN (Top View) PIN DESCRIPTION Pin No. Name Description 1 VDDH 2 HOSRC High−side driver sourcing output 3 HOSNK High−side driver sinking output 4 SW High−side driver positive bias voltage output Switch−node / high−side driver return 5 VDDL 6 LOSRC Low−side driver positive bias voltage output Low−side driver sourcing output 7 LOSNK Low−side driver sinking output 8 PGND Power ground / low−side driver return 9 DT 10 SGND 11 LIN Logic input for low−side gate driver output 12 HIN Logic input for high−side gate driver output 13 EN Logic input for disabling the driver (low power mode) 14 VDD Bias voltage for high current driver 15 VBST Bootstrap positive bias voltage Dead time adjustment / mode select Logic / signal ground www.onsemi.com 3 NCP51820 ABSOLUTE MAXIMUM RATINGS (All voltages are referenced to SGND pin unless otherwise noted) Rating Symbol Min Max Unit VDD Low−side and logic−fixed supply voltage (PGND = SGND) −0.3 20 V VDDL Low−side supply voltage VDDL (internally regulated; output only, do not connect to external voltage source, referenced to PGND) −0.3 5.5 V VSW High−side common mode voltage range (SW) −3.5 650 V VDDH High−side floating supply voltage VDDH (internally regulated; output only, do not connect to external voltage source; referenced to SW) −0.3 5.5 V High−side floating supply voltage VBST −0.3 670 V VBST_SW High−side floating supply voltage VBST (referenced to SW) −0.3 20 V VHOSRC, VHOSNK High−side floating driver sourcing/sinking output voltage (referenced to SW) −0.3 VDDH+0.3 V PGND voltage −3.5 3.5 V Low−side driver sourcing/sinking output voltage (referenced to PGND) −0.3 VDDL+0.3 V VIN Logic input voltage (HIN, LIN, and EN) −0.3 VDD+0.3 V VDT Dead−time control voltage (DT) −0.3 VDD+0.3 V VBST_SGND VPGND VLOSRC, VLOSNK dVSW/dt Allowable offset voltage slew rate − 200 V/ns TJ Operating Junction Temperature − 150 °C TSTG Storage Temperature Range Electrostatic Discharge Capability −55 150 °C Human Body Model (Note 3) − 1 kV Charged Device Model (Note 3) − 1 kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 2. VDD – PGND voltage must not exceed 20 V 3. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per ANSI/ESDA/JEDEC JS−001−2012 ESD Charged Device Model tested per JESD22−C101. 4. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78 Class I. THERMAL CHARACTERISTICS Symbol qJA PD Rating Value Unit °C/W Thermal Characteristics, QFN15 4x4 (Note 5) Thermal Resistance Junction−Ambient (Note 6) IS0P 245 IS2P 188 Power Dissipation (Note 6) QFN15 4x4 (Note 5) IS0P 0.51 IS2P 0.665 W 5. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 6. JEDEC standard: JESD51−2, JESD51−3. Mounted on 76.2×114.3×1.6 mm PCB (FR−4 glass epoxy material). IS0P: one single layer with zero power planes IS2P: one single layer with two power planes www.onsemi.com 4 NCP51820 RECOMMENDED OPERATING CONDITIONS (All voltages are referenced to SGND pin unless otherwise noted) Symbol Min Max Unit Low−side and logic−fixed supply voltage Rating 9 17 V SW−SGND maximum dc offset voltage (High−Side driver) − 580 V High−side floating supply voltage VBST − VSW+17 V VHOSRC, VHOSNK High−side floating driver sourcing/sinking output voltage − VDDH V VLOSRC, VLOSNK Low−side driver sourcing/sinking output voltage − VDDL V − 17 V −3.0 3.0 V VDD VSW−SGND VBST VIN Logic input voltage (HIN, LIN, and EN) PGND−SGND PGND−SGND maximum dc offset voltage (Low−Side driver) Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. ELECTRICAL CHARACTERISTICS (VBIAS (VDD, VBST) = 15 V, DT = SGND = PGND and CLOAD = 330 pF for typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, unless otherwise specified.) The VIN and IIN parameters are referenced to SGND. The VO and IO parameters are referenced to VSW and PGND and are applicable to the respective outputs HOSRC, HOSNK, LOSRC, and LOSNK. Symbol Parameter Test Conditions and Description Min Typ Max Unit POWER SUPPLY SECTION (VDD) IQDD Quiescent VDD supply current VLIN = VHIN = 0 V, EN = 0 V − 100 150 mA IPDD Operating VDD supply current fLIN = 500 kHz, average value − 1.5 2.5 mA VDDUV+ VDD UVLO positive going threshold VDD = Sweep 8.0 8.5 9.0 V VDDUV− VDD UVLO negative going threshold VDD = Sweep 7.5 8.0 8.5 V VDDHYS VDD UVLO Hysteresis VDD = Sweep − 0.5 − V tUVDDFLT VDD UVLO Filter Delay Time (Note 7) − 5.3 − ms − 10 mA BOOTSTRAPPED POWER SUPPLY SECTION Offset supply leakage current VBST = VSW = 600 V − IQBST Quiescent VBST supply current VLIN = VHIN = 0 V, EN = 5 V − 35 100 mA IPBST Operating VBST supply current fHIN = 500 kHz, average value − 1.5 2.5 mA VBSTUV+ VBST UVLO positive going threshold VDD = 12 V 6.0 6.5 7.0 V VBSTUV− VBST UVLO negative going threshold VDD = 12 V 5.5 6.0 6.5 V VBST UVLO Hysteresis VDD = 12 V − 0.5 − V 4.94 5.20 5.46 V 4.94 5.20 5.46 V ILK VHYST GATE DRIVER POWER SUPPLY SECTION VDDH VDDH−VSW regulated voltage VDDL VDDL−PGND regulated voltage 0 mA < IO < 10 mA INPUT LOGIC SECTION (HIN, LIN and EN) VINH High Level Input Voltage Threshold − − 2.5 V VINL Low Level Input Voltage Threshold 1.2 − − V − 0.5 − V VIN_HYS Input Logic Voltage Hysteresis IIN+ High Level Logic Input Bias Current VHIN = VLIN = 5 V 9 15 21 mA IIN− Low Level Logic Input Bias Current VHIN = VLIN = 0 V − − 2.2 mA RIN Input Pull−down Resistance VHIN = VLIN = 5 V − 333 − kW 0.45 0.60 0.75 V 22 30 38 ns DEAD−TIME SECTION VDT,MIN Minimum Dead−Time Control Voltage RDT = 30 kW tDT,MIN www.onsemi.com 5 NCP51820 ELECTRICAL CHARACTERISTICS (VBIAS (VDD, VBST) = 15 V, DT = SGND = PGND and CLOAD = 330 pF for typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, unless otherwise specified.) The VIN and IIN parameters are referenced to SGND. The VO and IO parameters are referenced to VSW and PGND and are applicable to the respective outputs HOSRC, HOSNK, LOSRC, and LOSNK. (continued) Symbol Parameter Test Conditions and Description Min Typ Max Unit RDT = 200 kW 3.1 4.0 4.8 V 160 200 240 ns DEAD−TIME SECTION Maximum Dead−Time Control Voltage VDT,MAX tDT,MAX DtDT VDT,0 VDT,OLE Dead−Time mismatch between LO → HO and HO → LO RDT = 30 kW − − 5 ns RDT = 200 kW − − 10 ns Dead−Time Disable Threshold Cross conduction prevention active 0.35 0.40 0.45 V High− & Low−Side Overlap Enable Threshold Cross conduction prevention disabled 5.5 6.0 6.5 V PROTECTION SECTION VUVTH_VDDX+ UVLO Threshold on VDDH and VDDL positive going threshold 4.15 4.40 4.70 V VUVTH_VDDX− UVLO Threshold on VDDH and VDDL negative going threshold 4.0 4.2 4.5 V TSD Thermal Shutdown (Note 7) 150 − − °C hys Hysteresis of Thermal Shutdown (Note 7) − 50 − °C GATE DRIVE OUTPUT SECTION VOH High−level output voltage, VVDDH−VHOSRC or VVDDL−VLOSRC IOSRC = 10 mA − 10 40 mV VOL Low−level output voltage, VHOSNK−VSW or VLOSNK –PGND IOSNK = 10 mA − 5 20 mV IOSRC Peak source current (Note 7) CLOAD = 200 pF, Rgate = 1 W 0.9 1.0 − A IOSNK Peak sink current (Note 7) CLOAD = 200 pF, Rgate = 1 W 1.8 2.0 − A Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 7. Guaranteed by design, is not tested in production. DYNAMIC ELECTRICAL CHARACTERISTICS (VBIAS (VDD, VBST)=15 V, DT=SGND=PGND and CLOAD=330 pF, for typical values TA=25°C, for min/max values TA=−40°C to +125°C, unless otherwise specified.) (Notes 9) Symbol IQDD Parameter Test Conditions Min Typ Max Unit Quiescent VDD supply current VLIN = VHIN = 0 V, EN = 0 V − 100 150 mA tPDLON LOSRC turn−on propagation delay time LIN rising to LOSRC rising (50% to 10%) − 25 50 ns tPDLOFF LOSNK turn−off propagation delay time LIN falling to LOSNK falling (50% to 90%) − 25 50 ns tPDHON HOSRC turn−on propagation delay time HIN rising to HOSRC rising (50% to 10%) SW = PGND − 25 50 ns tPDHOFF HOSNK turn−off propagation delay time HIN falling to HOSNK falling (50% to 90%) SW = PGND − 25 50 ns tRL LOSRC turn−on rising time − 2 4 ns tFL LOSNK turn−off falling time − 1.5 3.0 ns tRH HOSRC turn−on rising time − 2 4 ns tFH HOSNK turn−off falling time − 1.5 3.0 ns SW = PGND www.onsemi.com 6 NCP51820 DYNAMIC ELECTRICAL CHARACTERISTICS (VBIAS (VDD, VBST)=15 V, DT=SGND=PGND and CLOAD=330 pF, for typical values TA=25°C, for min/max values TA=−40°C to +125°C, unless otherwise specified.) (Notes 9) (continued) Symbol Parameter Test Conditions DtDEL Propagation Delay match HIN to HO and LIN to LO, SW = PGND tPW Minimum input pulse width Min Typ Max Unit − − 5 ns − − 10 ns Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 8. This parameter, although guaranteed by design, is not tested in production. 9. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25°C. TIMING DIAGRAM Shown in Figure 4 are the timing waveform definitions matching the specified dynamic electrical characteristics specified in the gate drive output section. 50% HIN (LIN) 90% 10% HO (LO) tPDHON tRH (tPDLON) (tRL) tPDHOFF tFH (tPDLOFF) (tFL) Figure 4. Input to Output Timing Diagram www.onsemi.com 7 NCP51820 60 14 12 8 6 4 30 20 10 2 0 10 1000 100 FHIN = FLIN [kHz] 0 10 10000 Figure 5. Operating VDD Supply Current (IPDD) vs. Frequency (VDD = 12 V, SW = PGND, EN = VDD, Both Outputs Switching) 140 4.0 125 3.0 110 3.0 95 IQDD, EN = 0 V IQBST, EN = 5 V 80 65 100 50 −20 0 20 40 60 80 100 10000 2.5 2.0 1.5 1.0 0.5 35 20 −40 1000 FHIN = FLIN [kHz] Figure 6. Operating VDD Supply Current (IPDD) vs. Frequency (VDD = 12 V, SW = PGND, EN = VDD, Both Outputs Switching) IDD, IBST [mA] IQDD, IQBST [mA] CLOAD = 330 pF CLOAD = 1 nF 40 IPDD [mA] 10 IPDD [mA] 50 CLOAD = 0 pF CLOAD = 100 pF 0.0 −40 120 Temperature [°C] −20 LIN = 100 kHz LIN = 500 kHz LIN = 1 MHz HIN = 100 kHz HIN = 500 kHz HIN = 1 MHz 0 60 20 40 80 100 Temperature [°C] Figure 7. Quiescent Current (IQDD, IQBST) vs. Temperature Figure 8. Operating Current (IPDD, IPBST) vs. Temperature www.onsemi.com 8 120 10.0 5.22 9.5 5.21 9.0 5.20 8.5 5.19 VDDH [V] VDDUVLO [V] NCP51820 8.0 7.5 VDDUV+ VDDUV− 7.0 6.5 6.0 −40 −20 0 20 40 60 80 100 5.18 5.17 VDDH, 0 mA VDDH, 10 mA 5.16 5.15 5.14 −40 120 −20 0 Temperature [°C] Figure 9. VDD UVLO (VDDUVLO+, VDDUVLO−) vs. Temperature Input Logic Threshold [V] 5.21 VDDL [V] 5.20 5.19 5.18 VDDH, 0 mA VDDH, 10 mA 5.16 5.15 5.14 −40 −20 0 20 40 60 80 100 120 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 −40 80 100 120 −20 0 20 40 60 80 100 120 Temperature [°C] Figure 11. VDDL (VDDL) Regulated Output Voltage vs. Temperature Figure 12. Input Logic (HIN, LIN, EN) Threshold vs. Temperature 400 22 LO Propagation Delay [ns] Input Logic Pull−down Resistance [kW] 60 VINH VINL Temperature [°C] 375 350 325 300 275 250 −40 40 Figure 10. VDDH (VDDH) Regulated Output Voltage vs. Temperature 5.22 5.17 20 Temperature [°C] −20 0 20 40 60 80 100 20 18 tPDLOFF 14 12 10 −40 120 tPDLON 16 Temperature [°C] −20 0 20 40 60 80 100 120 Temperature [°C] Figure 13. Input Logic (HIN, LIN, EN) Pull−down Resistance vs. Temperature Figure 14. LIN to LOSRC Propagation Delay vs. Temperature www.onsemi.com 9 NCP51820 3.0 LO Rise and Fall Time [ns] HO Propagation Delay [ns] 22 20 18 tPDHON 16 tPDHOFF 14 12 10 −40 −20 0 20 40 60 80 100 2.5 2.0 1.5 1.0 −40 120 tRL tFL −20 0 Temperature [°C] 40 60 80 100 120 Figure 16. LOSRC Rise Time and LOSNK Fall Time vs. Temperature Figure 15. HIN to HOSRC Propagation Delay vs. Temperature 3.0 4.5 VDDDLUVLO [V] HO Rise and Fall Time [ns] 20 Temperature [°C] 2.5 2.0 1.5 1.0 −40 0 20 40 60 80 100 4.3 4.2 VUVTH_VDDL+ VUVTH_VDDL− 4.1 tRH tFH −20 4.4 4.0 −40 120 −20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 17. HOSRC Rise Time and HOSNK Fall Time vs. Temperature Figure 18. VDDL UVLO vs. Temperature 6.0 4.5 5.5 5.0 ILK [mA] VDDDHUVLO [V] 4.4 4.3 4.2 VUVTH_VDDH+ VUVTH_VDDH− 4.1 4.5 4.0 3.5 3.0 2.5 4.0 −40 −20 0 20 40 60 80 100 2.0 −40 120 −20 0 20 40 60 80 100 Temperature [°C] Temperature [°C] Figure 20. VBST Leakage Current (ILK) vs. Temperature Figure 19. VDDH UVLO vs. Temperature www.onsemi.com 10 120 NCP51820 1.2 DtDT [ns] tDEL_SRC tDEL_SNK 0.6 0.4 0.2 −20 0 20 40 60 80 100 120 −40 −20 0 20 Minimum Dead−time [ns] Figure 21. Propagation Delay Matching (HIN to HO, LIN to LO) vs. Temperature 35 34 33 32 31 30 29 28 27 26 25 −40 0 20 40 60 80 100 120 0.70 0.69 0.68 0.67 0.66 0.65 0.64 0.63 0.62 0.61 0.60 Temperature [°C] Figure 23. Minimum Dead−time (RDT = 30 kW) vs. Temperature 216 4.4 214 4.3 212 4.2 210 4.1 208 4.0 206 3.9 tDT, MIN; HO−LO tDT, MIN; LO−HO VDT, MIN 204 202 200 −40 −20 60 80 100 120 Figure 22. Dead−time Mismatch vs. Temperature tDT, MIN; HO−LO tDT, MIN; LO−HO VDT, MIN −20 40 Temperature [°C] Temperature [°C] 0 20 40 60 80 100 120 3.8 3.7 3.6 Maximum Dead−time Control Voltage [V] 0.0 −40 Delta, tDT (RDT = 30 kW) Delta, tDT (RDT = 200 kW) Minimum Dead−time Control Voltage [V] 0.8 Maximum Dead−time [ns] DtDEL [ns] 1.0 2.5 2.0 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 −2.5 Temperature [°C] Figure 24. Maximum Dead−time (RDT = 200 kW) vs. Temperature www.onsemi.com 11 NCP51820 APPLICATIONS INFORMATION The NCP51820 can be quickly configured by following the steps outlined in this section. The component references made throughout this section refer to the schematic diagram and reference designations shown in Figure 25. CVBST DBST RHBST VDD CVDDH VDDH RHOSRC HOSRC RHOSNK HOSNK QH SW POWER STAGE CVDD REN 14 15 VDD VBST VIN 1 13 2 12 NCP51820 3 4 CENBYP HIN LIN 11 (Top View) EN 10 SGND DT 9 PWM mC or DSP CDTBYP 7 8 PGND 6 LOSNK CVDDL RLOSRC QL LOSRC VDDL 5 RDT RLOSNK Figure 25. Application Schematic, Half−Bridge Example (Kelvin Gate Return Connections Shown) DETAILED PIN FUNCTIONALITY bootstrap capacitor will take longer to fully charge as also determined by the on−time of the low−side GaN. Typically a higher value of CVBST helps with better noise immunity and internal regulator stability. Neglecting the effects of parasitic inductance, the minimum value bootstrap capacitor can be approximated as: Bias Supply Voltage (VDD) A dc voltage applied to VDD provides bias for the digital inputs, internal logic functions, high−side floating bootstrap (VBST) bias supplying the internal high−side regulator (VDDH) as well as providing bias directly to the internal low−side regulator (VDDL). Because the GaN FETs receive source current locally through the dedicated internal regulators, a single VDD bypass capacitor, CVDD, is all that’s required, connected directly between the VDD and SGND pins. The CVDD capacitor should be a ceramic bypass capacitor > 100 nF, located as close as possible to the VDD and SGND pins to properly filter out all glitches while switching. Under voltage lockout (UVLO) is important for protecting the GaN FETs and power stage. The NCP51820 includes UVLO thresholds of VDDUV+ > 8.5 V, ON and VDDUV− < 8 V, OFF, making it well suited for +12 V bias rails. C BST + Where: QG DVBST N VPP VF QG (eq. 1) DV BST = total gate charge required by GaN = VDD − VPP − NxVF > 6 V = number of series diodes connected = allowable VBST droop voltage (typically less than 10% of VDD) = DBST forward voltage drop Choose a low ESR and ESL ceramic capacitor with a voltage rating of twice the applied voltage (2 x DVBST). Once the bootstrap capacitor is selected, the peak charging current can be determined by knowing the frequency and duty cycle of the low−side gate drive. High−Side Bootstrap Voltage (VBST) Three components make up the high side bootstrap voltage bias serving as the input to the VDDH regulator. The bootstrap current limiting resistor and diode, RBST and DBST, series connected between the VDD and VBST pins and the bootstrap capacitor, CVBST, connected directly Switch node between VBST and (SW) pins. The VBST voltage is input to an internal LDO which produces the VDDH voltage. A large value for CVBST means the I PK + C BST dV + C BST dt DV BST F SW D MAX Where: DMAX = Max duty cycle of low−side gate drive FSW = Switching frequency www.onsemi.com 12 (eq. 2) NCP51820 Low−Side Linear Regulator (VDDL) The bootstrap diode, DBST, needs to have a voltage rating greater than VIN, should be high−speed (low reverse recovery), should be low current and should have very low junction capacitance. Diode junction capacitance, CJ, can become more problematic due to the high dV/dt that can appear across the GaN VDS. Symptoms of high dV/dt switching can be mitigated by using a Kelvin source return to SW, as shown in Figure 25. Another method to reduce CJ is to use 2 or more diodes in series such that the sum of the total voltage ratings from each diode is greater than VIN. Each of the individual CJ’s add reciprocally to reduce the total junction capacitance. The additional number of diode forward voltage drops must also be accounted for when calculating CBST. The purpose of the bootstrap resistor, RBST, is to limit peak CBST charging current, IPK, especially during startup. A small resistor may not limit the peak current enough, resulting in excessive ringing which can cause jitter in the high−side gate drive and/or EMI problems. A large resistor will dissipate more power and create a longer RC time constant causing a longer start−up time. A bootstrap resistor in the range of 1 W < RBST < 10 W is usually sufficient. The NCP51820 includes an internal linear regulator dedicated to providing a tightly regulated, 5.2 V gate drive amplitude signal to the low−side GaN FET. The VDDL regulator is fed directly from VDD, providing the most direct interface to the low−side GaN FET. This assures the lowest possible parasitic capacitance, required for meeting high−speed switching requirements of GaN. The VDDL regulator is referenced between VDDL and the power ground (PGND) pins and is capable of operating from common mode voltage range between −3.5 V to +3.5 V. Source current for the low−side GaN FET is provided from the charge stored in the CVDDL connected between VDDL and PGND. The value of the CVDDL capacitor is a function of the gate charge requirement of the low−side GaN FET. CVDDL should be chosen such that CVDD > 10*CVDDL, ie if CVDD cap 1 mF, CVDDL should be less than 100 nF. The VDDL regulator also includes dedicated UVLO thresholds of VUVTH_VDDL+ > 4.5 V, ON and VUVTH_VDDL− < 4.3 V, OFF. Signal Ground (SGND) and Power Ground (PGND) SGND is the GND for all internal control logic and digital inputs. Internally, the SGND and PGND pins are isolated from each other. PGND serves as the low−side, gate drive, return reference. As shown in Figure 2, the low−side level shifter, drive logic, PMOS sink and VDDL regulator are referenced to PGND. For GaN FETs that include a source Kelvin return, a direct connection should be made from PGND to the GaN FET Kelvin return. CVDDL should then be referenced to the PGND but separate from the power stage ground as shown in Figure 25. For GaN FETs that do not include a dedicated source Kelvin pin, best practice PCB layout techniques should be used to isolate the gate drive return current from the power stage, ground return current. Please refer to document AND9932, for NCP51820 and high−speed GaN, PCB layout tips. For half−bridge power topologies or any applications using a current sense transformer, SGND and PGND must be connected together on the PCB. In such applications, it is recommended to connect the SGND and PGND pins together with a short, low−impedance trace on the PCB as close to the NCP51820 as possible. Directly beneath the NCP51820 is an ideal way to make the SGND to PGND connection. For low−power applications, such as the active−clamp flyback or forward shown in Figure 26, a current sensing resistor, RCS, located in the low−side GaN FET source leg is commonly used. In such applications, the NCP51820 PGND and SGND pins must not be connected on the PCB because RCS would essentially be shorted through this connection. The NCP51820 low−side drive circuit is able to withstand −3.5 V to +3.5 V of common mode voltage. Since most current sense voltage signals are less than 1 V, the low−side drive stage can easily “float” above the voltage, High−Side Linear Regulator (VDDH) The NCP51820 includes an internal linear regulator dedicated to providing a tightly regulated, 5.2 V gate drive amplitude signal to the high−side GaN FET. The VDDH regulator appears after the bootstrap, providing the most direct interface to the high−side GaN FET. This assures the lowest possible parasitic capacitance, required for meeting high−speed switching requirements of GaN. The VDDH regulator is referenced between VDDH and the SW pins and can float between a common mode voltage range of −3.5 V up to 650 V. Source current for the high−side GaN FET is provided from the charge stored in CVDDH connected between VDDH and SW. The value of the CVDDH capacitor is a function of the gate charge requirement of the GaN FET. CVDDH should be chosen such that CVBST > 10*CVDDH, ie If CVBST is 1 mF, CVDDH should be less than 100 nF. The VDDH regulator also includes dedicated UVLO thresholds of VUVTH_VDDH+ > 4.5 V, ON and VUVTH_VDDH− < 4.3 V, OFF. Switch Node (SW) The SW pin serves as the high−side, gate drive, return reference. As shown in Figure 2, the high−side level shifter, drive logic, PMOS sink and VDDH regulator are referenced to SW. For GaN FETs that include a source Kelvin return, a direct connection should be made from SW to the GaN FET Kelvin return. CVDDH and CBST should then be referenced to the SW pin but separate from the power stage switch node as shown in Figure 25. For GaN FETs that do not include a dedicated source Kelvin pin, best practice PCB layout techniques should be used to isolate the gate drive return current from the power stage, switch node current. Please refer to document AND9932, for NCP51820 and high−speed GaN, PCB layout tips. www.onsemi.com 13 NCP51820 VRCS, generated by the current sense. For the active clamp example in Figure 26, the entire low−side gate drive, shown in the shaded box, is floating above VRCS. This is important because it ensures no loss of gate drive amplitude so the full 5.2 V, VDDL voltage appears at the low−side GaN FET gate−source terminals. A low impedance current sense resistor is recommended. Please refer to document AND9932, for NCP51820 and high−speed GaN, PCB layout tips. DBST CVBST RHBST VDD CVDDH VDDH RHOSRC HOSRC RHOSNK HOSNK QH SW CVDD REN 14 15 CCL POWER STAGE VDD VBST VIN 1 13 2 12 NCP51820 (Top View) 3 11 4 10 9 EN CENBYP HIN LIN PWM mC or DSP SGND CDTBYP DT 8 6 7 PGND LOSNK CVDDL RLOSRC QL LOSRC VDDL 5 RDT RLOSNK VRCS RCS Figure 26. Application Schematic, Active Clamp, Low−Side, Floating Gate Drive Example Input (HIN, LIN) Enable (EN) Both independent PWM inputs are Schmitt trigger, Transistor−Transistor Logic (TTL) compatible and are internally pulled low to SGND such that each corresponding driver input is defaulted to the inactive (disabled) state. The TTL input thresholds provide buffer and logic level translation functions capable of operating from a variety of PWM signals up to VDD of the NCP51820. TTL levels permit the inputs to be driven from a range of input logic signal levels for which a voltage greater than 2.5 V maximum is considered logic high. Both input thresholds meet industry−standard, TTL−logic defined thresholds and are therefore independent of VDD voltage. A typical hysteresis voltage of 0.5 V is specified for each driver input. For optimal high−speed switching performance, the driving signal for the TTL inputs should have fast rising and falling edges with a slew rate of 6 V/ms or faster, so a rise time from 0 to 3.3 V should be 550 ns or less. Enable (EN) is internally pulled low to SGND so the driver is always defaulted to a disabled output status. Similar to HIN and LIN, EN is a Schmitt trigger TTL compatible input. Pulling the EN pin above 2.5 V maximum, enables the outputs, placing the NCP51820 into an active ready state. Due to the nature of high−speed switching associated with GaN power stages, and for improved noise immunity, it is recommended to connect the EN pin to VDD through a 1 kW (or less) pull−up resistor. For applications where the EN pin is actively controlled, the EN pin can be driven direct but should be bypassed with a 10 nF decoupling capacitor. As shown in Figure 27, if EN is pulled low during normal operation, the driver outputs are immediately disabled, even terminating an active HIN or LIN pulse mid –cycle during the on−time. When EN is toggled high, during normal operation, a cycle−by−cycle, edge−triggered logic function is employed to prevent shortened, erroneous control pulses from being processed by the output. This behavior is highlighted in Figure 27, where EN transitions high at the same time the HIN (or LIN) input pulse is high. In this way, the NCP51820 is intelligent by waiting until the next rising edge to process the full input signal to the output driver stage. www.onsemi.com 14 NCP51820 HIN (LIN) HO (LO) EN External Shutdown Figure 27. Timing Chart of Enable Function Dead−Time Control (DT) MODE B: Connect a 25 kW < RDT < 200 kW Resistor from DT to SGND; Dead−time is programmable by a single resistor connected between the DT and SGND pins. The amount of desired dead−time can be programmed via the dead−time resistor, RDT, between the range of 25 kW < RDT < 200 kW to obtain an equivalent dead−time, proportional to RDT, in the range of 25 ns < tDT < 200 ns. If either edge between HIN and LIN result in a dead−time less than the amount set by RDT, the set DT value shall be dominant. If either edge between HIN and LIN result in a dead−time greater than the amount set by RDT, the controller dead−time shall be dominant. The control voltage range, VDT, for RDT is 0.5 V < VDT < 4 V. DT programmability is summarized and shown graphically in Figure 29. Accurately ensuring some minimal amount of dead−time between the high−side and low−side gate drive output signals is critical for safe, reliable optimized operation of any high−speed, half−bridge power stage. The DT should be bypassed with a 100 nF (CDTBYP) ceramic capacitor placed closest to the pin and directly between DT and SGND. If used, the RDT resistor should then be placed directly in parallel with CDTBYP. The NCP51820 offers four unique mode settings to utilize dead−time in such a way to be fully compatible with any control algorithm. MODE A: Connect DT to SGND; When the DT pin voltage, VDT, is less than 0.5 V typical (RDT = 0 W), the DT programmability is disabled and fixed dead−time, anti−cross−conduction protection is enabled. If HIN and LIN are overlapping by X ns, then X ns of dead−time is automatically inserted. Conversely, if HIN and LIN have greater than 0 ns of dead−time, then the dead−time is not modified by the NCP51820 and is passed through to the output stage as defined by the controller. This type of dead−time control is preferred when the controller will be making the necessary dead−time adjustments but needs to rely on the NCP51820 dead−time control function for anti−cross−conduction protection. MODE C: Connect a 249 kW Resistor from DT to SGND; Connect a 249 kW resistor between DT and SGND to program the maximum dead−time value of 200 ns. The control voltage range, VDT, for assuring tDT = 200 ns is 4 V < VDT < 5 V. DT programmability is summarized and shown graphically in Figure 29. MODE D: Connect DT to VDD; When the DT pin voltage, VDT, is greater than 6 V (pulled up to VDD through 10 kW resistor), anti−cross−conduction protection is disabled, allowing the output signals to overlap. This operating mode is suitable for applications where it is desired to have both driver output stages switching simultaneously. If choosing this operating mode while driving a half−bridge power stage, extreme caution should be taken, as cross conduction can potentially damage power components if not accounted for. This type of dead−time control is preferred when the controller will be making extremely accurate dead−time adjustments and can respond to the potential of over−current faults on a cycle−by−cycle basis. DT programmability is summarized and shown graphically in Figure 29. HIN 50% 50% LIN 50% 50% LO HO DT 50% DT 50% Figure 28. Internal Dead−Time Definitions www.onsemi.com 15 NCP51820 V DT [V] 6 t DT [ns] No dead−time Mode A: VDT < 0.5 V tDT = SGND = 0 V Cross−conduction prevention active 5 Output ENABLED MODE D: 6 V < VDT < VDD (pull−up) tDT = 0 ns Cross−conduction prevention disabled Dead−time Control Range Mode B: 0.5 V < VDT < 4 V tDT = RDT x 1 ns/kW Cross−conduction prevention active 4 Maximum dead−time MODE C: 4 V 40 V) satisfying the second conditioned mentioned above. Synchronous Boost Converter: Similar to flyback the VHB at t=0 is at input voltage (> 40 V) so no Impact Ionization current flows. Phase Shifted Full−bridge: The HB pin can be potentially at less than 40 V when switching starts. This can cause Impact Ionization current to flow during startup and in burst mode. This can be mitigated by adding parallel resistors (>1Meg) across the FETs. Parallel resistors ensure that the switch node voltage is at a voltage greater than 40 V before the switching starts. High Voltage Synchronous Buck Converter: Synchronous buck presents the worst case for the Impact Ionization current. The HB is at a voltage equal to output voltage always at t= 0. Hence at the startup or in the cases of burst mode we see Impact Ionization current when the Vout < 40 V. One potential solution can be pre−charging the output with VCC through a diode and running the system in soft−switching from first pulse itself. However if the regulated Vout is less than 40 V then there is a chance of Impact Ionization current every burst cycle. But as explained earlier this occurs only in case of HV systems. When the bulk voltage is less than 150 V no Impact Ionization current is seen. www.onsemi.com 19 NCP51820 Figure 32. 1 Impact Ionization Current in NCP51820. C1 is HB Node at 50 V/div and C2 is Impact Ionization Current at 50 mA/div www.onsemi.com 20 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS QFN15 4x4, 0.5P CASE 485FN ISSUE B DATE 24 JUL 2019 GENERIC MARKING DIAGRAM* XXXXXX XXXXXX ALYWG G XXXXXX = Specific Device Code A = Assembly Location L = Wafer Lot *This information is generic. Please refer to Y = Year device data sheet for actual part marking. W = Work Week Pb−Free indicator, “G” or microdot “ G”, G = Pb−Free Package may or may not be present. Some products (Note: Microdot may be in either location) may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON81104G QFN15 4x4, 0.5P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com onsemi Website: www.onsemi.com ◊ TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative