NCP5211BDR2G

NCP5211 Low Voltage Synchronous Buck Controller The NCP5211 is a low voltage synchronous buck controller. It contains all required circuitry for a synchronous buck converter using external N−Channel MOSFETs. High current internal gate drivers are capable of driving high gate capacitance of low RDS(on) NFETs for better efficiency. The NCP5211 is in a 14−pin package to allow the designer added flexibility. The NCP5211 provides overcurrent protection, undervoltage lockout, Soft−Start and built in adaptive nonoverlap. The NCP5211 also provides adjustable fixed frequency range of 150 kHz to 750 kHz. This gives the designer more flexibility to make efficiency and component size compromises. The NCP5211 will operate over a 4.5 V to 14 V range using either single or dual input voltage. http://onsemi.com MARKING DIAGRAM 14 SOIC−14 D SUFFIX CASE 751A NCP5211xG AWLYWW 1 Features NCP5211x A WL Y WW G • Switching Regulator Controller ♦ N−Channel Synchronous Buck Design V2 Control Topology ♦ 200 ns Transient Response ♦ Programmable Fixed Frequency of 150 kHz−750 kHz ♦ 1.0 V 1.5% Internal Reference ♦ Lossless Inductor Sensing Overcurrent Protection ♦ Hiccup Mode Short Circuit Protection ♦ Programmable Soft−Start ♦ 40 ns GATE Rise and Fall Times (3.3 nF Load) ♦ 70 ns Adaptive FET Nonoverlap Time ♦ Differential Remote Sense Capability System Power Management ♦ 5.0 V or 12 V Operation ♦ Undervoltage Lockout ♦ On/Off Control Through Use of the COMP Pin Pb−Free Packages are Available* ♦ • • = = = = = = Specific Device Code Assembly Location Wafer Lot Year Work Week Pb−Free Package PIN CONNECTIONS 1 GATE(H) BST LGND VFFB VFB COMP SGND PGND GATE(L) VC IS+ IS− VCC ROSC ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 April, 2006 − Rev. 0 1 Publication Order Number: NCP5211/D NCP5211 5.0 V + 100 mF/10 V × 3 +VOUT BST VC 100 mF/10 V × 2 GATE(L) COMP PGND 0.1 mF ROSC NCP5211 IS+ 51 k 0.1 mF IS− 0.1 mF + 4.7 k GATE(H) VCC 0.1 mF 2.5 V/8.0 A 2.9 mH 0.1 mF SGND VFFB LGND VFB 10 −VOUT Return 4.7 k 1.0% SENSE+ 1.5 k 1.0 k 1.0% 10 680 pF SENSE− Figure 1. Application Diagram, 5.0 V to 2.5 V/8.0 A Converter with Differential Remote Sense ORDERING INFORMATION Device Operating Temperature Range Package Shipping† −40°C < TA < 85°C SOIC−14 (Pb−Free) 2500 / Tape & Reel 0°C < TA < 70°C SOIC−14 (Pb−Free) 2500 / Tape & Reel NCP5211BDR2G NCP5211DR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. MAXIMUM RATINGS Rating Value Unit 150 °C 230 peak °C −65 to +150 °C 30 125 °C/W °C/W ESD Susceptibility (Human Body Model) 2.0 kV JEDEC Moisture Sensitivity 1.0 − Operating Junction Temperature, TJ Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1) Storage Temperature Range, TS Package Thermal Resistance, Junction−to−Case, RqJC Junction−to−Ambient, RqJA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. 60 second maximum above 183°C. http://onsemi.com 2 NCP5211 MAXIMUM RATINGS Pin Name Pin Symbol VMAX VMIN ISOURCE ISINK IC Power Input VCC 16 V −0.3 V N/A 50 mA DC Power input for the low side driver VC 16 V −0.3 V N/A 1.5 A Peak, 200 mA DC BST 20 V −0.3 V N/A 1.5 A Peak, 200 mA DC Compensation Capacitor COMP 6.0 V −0.3 V 1.0 mA 1.0 mA Voltage Feedback Input VFB 6.0 V −0.3 V 1.0 mA 1.0 mA Oscillator Resistor ROSC 6.0 V −0.3 V 1.0 mA 1.0 mA Fast Feedback Input VFFB 6.0 V −0.3 V 1.0 mA 1.0 mA High−Side FET Driver GATE(H) 20 V −0.3 V −2.0 V for 50 ns 1.5 A Peak 200 mA DC 1.5 A Peak, 200 mA DC Low−Side FET Driver GATE(L) 16 V −0.3 V −2.0 V for 50 ns 1.5 A Peak, 200 mA DC 1.5 A Peak, 200 mA DC Positive Current Sense IS+ 6.0 V −0.3 V 1.0 mA 1.0 mA Negative Current Sense IS− 6.0 V −0.3 V 1.0 mA 1.0 mA Power Ground PGND 0.3 V −0.3 V 1.5 A Peak, 200 mA DC N/A Logic Ground LGND 0V 0V 100 mA N/A Sense Ground SGND 0.3 V −0.3 V 1.0 mA 1.0 mA Power Supply input for the high side driver PIN DESCRIPTION PIN NO. PIN SYMBOL FUNCTION 1 GATE(H) 2 BST 3 LGND Reference ground. All control circuits are referenced to this pin. IC substrate connection. 4 VFFB Input for the PWM comparator. 5 VFB Error amplifier input. 6 COMP Error Amp output. PWM Comparator reference input. A capacitor to LGND provides error amp compensation. 7 SGND Internal reference is connected to this ground. Connect directly at the load for ground remote sensing. 8 ROSC A resistor from this pin to SGND sets switching frequency. 9 VCC Input Power Supply Pin. It supplies power to control circuitry. A 0.1 mF Decoupling cap is recommended. 10 IS− Negative input for overcurrent comparator. 11 IS+ Positive input for overcurrent comparator. 12 VC Power supply input for the low side driver. 13 GATE(L) 14 PGND High Side Switch FET driver pin. Capable of delivering peak currents of 1.0 A. Power supply input for the high side driver. Low Side Synchronous FET driver pin. Capable of delivering peak currents of 1.0 A. High Current ground for the GATE(H) and GATE(L) pins. http://onsemi.com 3 NCP5211 ELECTRICAL CHARACTERISTICS (−40°C < TA < 85°C; −40°C < TJ < 125°C; 4.5 V < VCC, VC < 14 V; 7.0 V < BST < 20 V; CGATE(H) = CGATE(L) = 3.3 nF; ROSC = 51 k; CCOMP = 0.1 mF, unless otherwise specified.) (Note 2) Test Conditions Characteristic Min Typ Max Unit Error Amplifier VFB Bias Current VFB = 0 V − 0.1 1.0 mA COMP Source Current VFB = 0.8 V 15 30 60 mA COMP SINK Current VFB = 1.2 V 15 30 60 mA − 98 − dB − 50 − kHz Open Loop Gain Unity Gain Bandwidth − C = 0.1 mF PSRR @ 1.0 kHz − − 70 − dB Output Transconductance − − 32 − mmho Output Impedance − − 2.5 − MW 0.977 0.992 1.007 V VFB = 0.8 V 2.5 3.0 − V VFB = 1.2 V − 0.1 0.2 V VC − 0.5 BST − 0.5 − − V Reference Voltage −0.1 V < SGND < 0.1 V, COMP = VFB, Measure VFB to SGND COMP Max Voltage COMP Min Voltage GATE(H) and GATE(L) High Voltage (AC) GATE(L), GATE(H) 0.5 nF < CGATE(H) = CGATE(L) < 10 nF Low Voltage (AC) GATE(L) or GATE(H) 0.5 nF < CGATE(H); CGATE(L) < 10 nF − − 0.5 V Rise Time VC = BST = 10 V, Measure: 1.0 V < GATE(L) < 9.0 V, 1.0 V < GATE(H) < 9.0 V − 40 80 ns Fall Time VC = BST = 10 V, Measure: 1.0 V < GATE(L) < 9.0 V, 1.0 V < GATE(H) < 9.0 V − 40 80 ns GATE(H) to GATE(L) Delay GATE(H) < 2.0 V, GATE(L) > 2.0 V 40 70 110 ns GATE(L) to GATE(H) Delay GATE(L) < 2.0 V, GATE(H) > 2.0 V 40 70 110 ns GATE(H)/(L) Pull−Down Resistance to PGND 20 50 115 KW OVC Comparator Offset Voltage 0 V < IS+ < VCC, 0 V < IS− < VCC 54 60 66 mV IS+ Bias Current 0 V < IS+ < VCC −1.0 0.1 1.0 mA IS− Bias Current 0 V < IS− < VCC −1.0 0.1 1.0 mA 0.20 0.25 0.30 V 2.0 5.0 8.0 mA − 100 200 ns Overcurrent Protection COMP Discharge Threshold COMP Discharge Current in OVC Fault Mode − COMP = 1.0 V PWM Comparator Transient Response COMP = 0 − 1.5 V, VFFB, 20 mV overdrive PWM Comparator Offset VFB = VFFB = 0 V; Increase COMP until GATE(H) starts switching 0.425 0.475 0.525 V Artificial Ramp Duty Cycle = 90% 40 70 100 mV VFFB Bias Current VFFB = 0 V − 0.1 1.0 mA VFFB Input Range (Note 4) − − 1.1 V − − 200 ns Minimum Pulse Width − Oscillator Switching Frequency ROSC = 18 k 600 750 900 kHz Switching Frequency ROSC = 51 k 240 300 360 kHz Switching Frequency ROSC = 115 kW 120 150 180 kHz 1.21 1.25 1.29 V ROSC Voltage − 2. Guaranteed by design. Not tested in production. http://onsemi.com 4 NCP5211 ELECTRICAL CHARACTERISTICS (continued) (−40°C < TA < 85°C; −40°C < TJ < 125°C; 4.5 V < VCC, VC < 14 V; 7.0 V < BST < 20 V; CGATE(H) = CGATE(L) = 3.3 nF; ROSC = 51 k; CCOMP = 0.1 mF, unless otherwise specified.) (Note 3) Test Conditions Characteristic Min Typ Max Unit General Electrical Specifications VCC Supply Current COMP = 0 V (no switching) − 5.0 8.0 mA BST/VC Supply Current COMP = 0 V (no switching) − 2.0 3.0 mA Start Threshold GATE(H) Switching, COMP Charging 3.90 4.05 4.20 V Stop Threshold GATE(H) Not Switching, COMP Not Charging 3.75 3.90 4.05 V Hysteresis Start−Stop 100 150 200 mV Sense Ground Current (Note 4) − 0.15 1.00 mA 3. Guaranteed by design. Not tested in production. 4. Recommended maximum operating voltage between the three grounds is 200 mV. 0.5 V Σ − + Reset Dominant PWM Comparator + VFFB R Q S Q − COMP ART Ramp VFB OSC ROSC Error Amp − PWM FF + Fault 1.0 V BST GATE(H) VC GATE(L) − + SGND − VSTART Set Dominant UVLO − + OC Comparator S Q R Q − 0.25 V + − 60 mV + IS+ LGND ROSC UVLO Comparator − VCC IS− PGND + + 0.8 V 100 % DC Comparator 5.0 mA COMP Discharge COMP Figure 2. Block Diagram http://onsemi.com 5 Fault NCP5211 THEORY OF OPERATION V2 Control Method sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. Line and load regulations are drastically improved because there are two independent voltage loops. A voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. The V2 method of control maintains a fixed error signal for both line and load variations, since both line and load affect the ramp signal. The V2 method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the value of the DC output voltage. This control scheme inherently compensates for variations in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current. PWM Comparator + GATE(H) − GATE(L) Constant Frequency Operation Ramp Signal Error Amplifier + COMP − Error Signal The NCP5211 uses a constant frequency, trailing edge modulation architecture for generating PWM signal. During normal operation, the oscillator generates a narrow pulse at the beginning of each switching cycle to turn on the main switch. The main switch will be turned off when the ramp signal intersects with the output of the error amplifier (COMP pin voltage). Therefore, the switch duty cycle can be modified to regulate the output voltage to the desired value as line and load conditions change. The major advantage of constant frequency operation is that the component selections, especially the magnetic component design, become very easy. The oscillator frequency of NCP5211 is programmable from 150 kHz to 750 kHz using an external resistor connected from the ROSC pin to ground. Output Voltage Feedback Reference Voltage Figure 3. V2 Control Block Diagram The V2 control method is illustrated in Figure 3. The output voltage is used to generate both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of the change. The ramp signal also contains the DC portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. A change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the V2 control scheme to compensate the duty cycle. Since the change in the inductor current modifies the ramp signal, as in current mode control, the V2 control scheme has the same advantages in line transient response. A change in load current will have an effect on the output voltage, altering the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. Load transient response is determined only by the comparator response time and the transition speed of the main switch. The reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. The error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. The main purpose of this “slow” feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote Startup If there are no fault conditions and the fault latch is reset, the error amplifier will start charging the COMP pin capacitor after the NCP5211 is powered up. The output of the error amplifier (COMP voltage) will ramp up linearly. The COMP capacitance and the source current of the error amplifier determine the slew rate of COMP voltage. The output of the error amplifier is connected internally to the inverting input of the PWM comparator and it is compared with the VFFB pin voltage plus 0.5 V offset at the non−inverting input of the PWM comparator. Since VFFB voltage is zero before the startup, the PWM comparator output will stay high until the COMP pin voltage hits 0.5 V. There is no switching action while the PWM comparator output is high. After the COMP voltage exceeds the 0.5 V offset, the output of PWM comparator toggles and releases the PWM latch. The narrow pulse generated by the oscillator at the beginning of the next oscillator cycle will set the latch so that the main switch can be turned on and the regulator output voltage ramps up. When the output voltage achieves a level http://onsemi.com 6 NCP5211 set by the COMP voltage, the main switch will be turned off. The V2 control loop will adjust the main switch duty cycle as required to ensure the regulator output voltage tracks the COMP voltage. Since the COMP voltage increases gradually, the soft−start can be achieved. The start−up period ends when the output voltage reaches the level set by the external resistor divider. If the values of R and C are chosen such that: L + RC RL Then the voltage across the capacitor C will be: VC + RLIL Therefore, if the time constant of the RC network is equal to that of the inductor, the voltage across the capacitor is proportional to the inductor current by a factor of the inductor ESR. In practice, the user should ensure that under all component tolerances, the RC time constant is larger than the L/R time constant. This will keep the high frequency gain for VC(s)/IL(s) less than the low frequency gain, and avoid unnecessary OCP tripping during short duration overcurrent situations. Compared with conventional resistor sensing, the inductor ESR current sensing technique is lossless, but is not as accurate due to variation in the ESR from inductor to inductor and over temperature. For typical inductor ESR, the 0.39%/°C positive temperature coefficient will reduce the current limit at high temperature, and will help prevent thermal runaway, but will force an increased design target at room temperature. This technique can be more accurate than using a PCB trace, since PCB copper thickness can vary 10−20%, compared to 1% variation in wire diameter thickness typical of inductors. Output Enable Since there can be no switching until the COMP pin exceeds the 0.5 V offset built into the PWM comparator, the COMP pin can also be used for an enable function. Hold the COMP pin below 0.4 V with an open collector circuit to disable the output. When the COMP pin is released to enable startup, the user must ensure there is no leakage current from the enable circuit into COMP. During normal operation the COMP output is driven with only 5.0 mA to 30 mA internally. Hiccup Mode Overcurrent Protection Under normal load conditions, the voltage across the IS+ and IS− pins is less than the 60 mV overcurrent threshold. If the threshold is exceeded, the overcurrent fault latch is set, the high side gate driver is forced low, and the COMP pin is discharged with 5.0 mA. There is no switching until the COMP voltage drops below a 0.25 V threshold. Then, the fault latch is cleared and a soft−start is initiated. The low effective duty cycle during hiccup overcurrent greatly reduces component stress for an extended fault. Remote Voltage Sensing The NCP5211 has the capability to sense the voltage when the load is located far away from the regulator. The SGND pin is dedicated to the differential remote sensing. The negative remote sense line is connected to SGND pin directly, while the positive remote sense line is usually connected to the top of the feedback voltage divider. To prevent overvoltage condition caused by open remote sense lines, the divider should also be locally connected to the output of the regulator through a low value resistor. That resistor is used to compensate for the voltage drop across the output power cables. Inductor Current Sensing Besides using a current sense resistor to sense inductor current, NCP5211 provides the users with the possibility of using lossless inductor sensing technique. This sensing technique utilizes the Equivalent Series Resistance (ESR) of the inductor to sense the current. The output current is sensed through an RC network in parallel with the inductor as shown in Figure 4. The voltage across the small capacitor is then fed to the OC comparator. IS+ VIN IS− C R Q1 L RL Q2 CO Figure 4. Inductor Current Sensing http://onsemi.com 7 NCP5211 APPLICATIONS INFORMATION Input Capacitor Selection and Considerations APPLICATIONS AND COMPONENT SELECTION The input capacitor is used to reduce the current surges caused by conduction of current of the top pass transistor charging the PWM inductor. The input current is pulsing at the switching frequency going from 0 to peak current in the inductor. The duty factor will be a function of the ratio of the input to output voltage and of the efficiency. Inductor Component Selection The output inductor may be the most critical component in the converter because it will directly effect the choice of other components and dictate both the steady−state and transient performance of the converter. When selecting an inductor the designer must consider factors such as DC current, peak current, output voltage ripple, core material, magnetic saturation, temperature, physical size, and cost (usually the primary concern). In general, the output inductance value should be as low and physically small as possible to provide the best transient response and minimum cost. If a large inductance value is used, the converter will not respond quickly to rapid changes in the load current. On the other hand, too low an inductance value will result in very large ripple currents in the power components (MOSFETs, capacitors, etc) resulting in increased dissipation and lower converter efficiency. Also, increased ripple currents will force the designer to use higher rated MOSFETs, oversize the thermal solution, and use more, higher rated input and output capacitors − the converter cost will be adversely effected. One method of calculating an output inductor value is to size the inductor to produce a specified maximum ripple current in the inductor. Lower ripple currents will result in less core and MOSFET losses and higher converter efficiency. The following equation may be used to calculate the minimum inductor value to produce a given maximum ripple current (α ⋅ IO,MAX). The inductor value calculated by this equation is a minimum because values less than this will produce more ripple current than desired. Conversely, higher inductor values will result in less than the maximum ripple current. V DF + O VI The RMS value of the ripple into the input capacitors can now be calculated: IIN(RMS) + IOUT ǸDF * DF2 The input RMS is maximum at 50% DF, so selection of the possible duty factor closest to 50% will give the worst case dissipation in the capacitors. The power dissipation of the input capacitors can be calculated by multiplying the square of the RMS current by the ESR of the capacitor. Output Capacitor The output capacitor filters output inductor ripple current and provides low impedance for load current changes. The effect of the capacitance for handling the power supply induced ripple will be discussed here. Effects of load transient behavior can be considered separately. The principle consideration for the output capacitor is the ripple current induced by the switches through the inductor. This ripple current was calculated as IAC in the above discussion of the inductor. This ripple component will induce heating in the capacitor by a factor of the RMS current squared multiplied by the ESR of the output capacitor section. It will also create output ripple voltage. The ripple voltage will be a vector summation of the ripple current times the ESR of the capacitor, plus the ripple current integrating in the capacitor, and the rate of change in current times the total series inductance of the capacitor and connections. The inductor ripple current acting against the ESR of the output capacitor is the major contributor to the output ripple voltage. This fact can be used as a criterion to select the output capacitor. LoMIN + (Vin * Vout) @ Voutń(a @ IO,MAX @ Vin @ fSW) α is the ripple current as a percentage of the maximum output current (α = 0.15 for ±15%, α = 0.25 for ±25%, etc) and fsw is the switching frequency. If the minimum inductor value is used, the inductor current will swing ±α/2% about Iout. Therefore, the inductor must be designed or selected such that it will not saturate with a peak current of (1 + α/2) ⋅ IO,MAX. Power dissipation in the inductor can now be calculated from the RMS current level. The RMS of the AC component of the inductor is given by the following relationship: VPP + IPP CESR The power dissipation in the output capacitor can be calculated from: P + IAC2 I IAC + PP Ǹ12 CESR where: IAC = AC RMS of the inductor CESR = Effective series resistance of the output capacitor network. where IPP = α ⋅ IO,MAX. The total IRMS of the current will be calculated from: IRMS + Ǹ IOUT2 ) IAC2 The power dissipation for the inductor can be determined from: P + IRMS2 1 Eff MOSFET & Heatsink Selection Power dissipation, package size, and thermal solution drive MOSFET selection. To adequately size the heat sink, RL http://onsemi.com 8 NCP5211 the design must first predict the MOSFET power dissipation. Once the dissipation is known, the heat sink thermal impedance can be calculated to prevent the specified maximum case or junction temperatures from being exceeded at the highest ambient temperature. Power dissipation has two primary contributors: conduction losses and switching losses. The control or upper MOSFET will display both switching and conduction losses. The synchronous or lower MOSFET will exhibit only conduction losses because it switches into nearly zero voltage. However, the body diode in the synchronous MOSFET will suffer diode losses during the non−overlap time of the gate drivers. For the upper or control MOSFET, the power dissipation can be approximated from: ID VGATE VGS_TH QGS1 QGS2 QGD VDRAIN Figure 5. MOSFET Switching Characteristics PD,CONTROL + (IRMS,CNTL2 @ RDS(on)) Ig is the output current from the gate driver IC. VIN is the input voltage to the converter. fsw is the switching frequency of the converter. QG is the MOSFET total gate charge to obtain RDS(on). Commonly specified in the data sheet. Vg is the gate drive voltage. QRR is the reverse recovery charge of the lower MOSFET. Qoss is the MOSFET output charge specified in the data sheet. For the lower or synchronous MOSFET, the power dissipation can be approximated from: ) (ILo,MAX @ QswitchńIg @ VIN @ fSW) ) (Qossń2 @ VIN @ fSW) ) (VIN @ QRR @ fSW) The first term represents the conduction or IR losses when the MOSFET is ON while the second term represents the switching losses. The third term is the losses associated with the control and synchronous MOSFET output charge when the control MOSFET turns ON. The output losses are caused by both the control and synchronous MOSFET but are dissipated only in the control FET. The fourth term is the loss due to the reverse recovery time of the body diode in the synchronous MOSFET. The first two terms are usually adequate to predict the majority of the losses. Where IRMS,CNTL is the RMS value of the trapezoidal current in the control MOSFET: PD,SYNCH + (IRMS,SYNCH2 @ RDS(on)) ) (Vfdiode @ IO,MAXń2 @ t_nonoverlap @ fSW) The first term represents the conduction or IR losses when the MOSFET is ON and the second term represents the diode losses that occur during the gate non−overlap time. All terms were defined in the previous discussion for the control MOSFET with the exception of: IRMS,CNTL + ǸD @ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2)ń3]1ń2 ILo,MAX is the maximum output inductor current: IRMS,SYNCH + Ǹ1 * D @ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2)ń3]1ń2 ILo,MAX + IO,MAXń2 ) DILoń2 ILo,MIN is the minimum output inductor current: where: Vfdiode is the forward voltage of the MOSFET’s intrinsic diode at the converter output current. t_nonoverlap is the non−overlap time between the upper and lower gate drivers to prevent cross conduction. This time is usually specified in the data sheet for the control IC. When the MOSFET power dissipations are known, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case ambient operating temperature ILo,MIN + IO,MAXń2 * DILoń2 IO,MAX is the maximum converter output current. D is the duty cycle of the converter: D + VOUTńVIN DILo is the peak−to−peak ripple current in the output inductor of value Lo: DILo + (VIN * VOUT) @ Dń(Lo @ fSW) RDS(on) is the ON resistance of the MOSFET at the applied gate drive voltage. Qswitch is the post gate threshold portion of the gate−to−source charge plus the gate−to−drain charge. This may be specified in the data sheet or approximated from the gate−charge curve as shown in the Figure 5. qT t (TJ * TA)ńPD where; qT is the total thermal impedance (qJC + qSA). qJC is the junction−to−case thermal impedance of the MOSFET. Qswitch + Qgs2 ) Qgd http://onsemi.com 9 NCP5211 qSA is the sink−to−ambient thermal impedance of the heatsink assuming direct mounting of the MOSFET (no thermal “pad” is used). TJ is the specified maximum allowed junction temperature. TA is the worst case ambient operating temperature. For TO−220 and TO−263 packages, standard FR−4 copper clad circuit boards will have approximate thermal resistances (qSA) as shown below: ROSC Selection The switching frequency is programmed by selecting the resistor connected between the ROSC pin and SGND (pin 7). The grounded side of this resistor should be directly connected to the SGND pin, without any other currents flowing between the bottom of the resistor and the pin. Also, avoid running any noisy signals under the resistor, since injected noise could cause frequency jitter. The graph in Figure 6 shows the required resistance to program the frequency. Below 500 kHz, the following formula is accurate: Pad Size (in2/mm2) Single−Sided 1 oz. Copper 0.5/323 60−65°C/W 0.75/484 55−60°C/W 1.0/645 50−55°C/W 1.5/968 45−50°C/W 120 2.0/1290 38−42°C/W 100 2.5/1612 33−37°C/W R + 17544ńfSW * 4 kW where fSW is the switching frequency in kHz. Resistance (kW) 140 As with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. Variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e. worst case MOSFET RDS(on)). Also, the inductors and capacitors share the MOSFET’s heatsinks and will add heat and raise the temperature of the circuit board and MOSFET. For any new design, its advisable to have as much heatsink area as possible − all too often new designs are found to be too hot and require re−design to add heatsinking. 60 40 20 0 0 100 200 300 400 500 600 Frequency (kHz) 700 800 Figure 6. Frequency vs. ROSC Differential Remote Sense Operation The ability to implement fully differential remote sense is provided by the NCP5211. The positive remote sense is implemented by bringing the output remote sense connection to the positive load connection. A low value resistor is connected from Vout to the feedback point at the regulator to provide feedback in the instance when the remote sense point is not connected. The negative remote sense connection is provided by connecting the SGND of the NCP5211 to the negative of the load return. Again, a low value resistor should be connected between SGND and LGND at the regulator to provide feedback in the instance when the remote sense point is not connected. The maximum voltage differential between the three grounds for this part is 200 mV. Compensation Capacitor Selection The nominal output current capability of the error amp is 30 mA. This current charging the capacitor on the COMP pin is used as soft−start for the converter. The COMP pin is going to ramp up to a voltage level that is within 70 mV of what VFFB is going to be when in regulation. This is the voltage that will determine the soft−start. Therefore, the COMP capacitor can be established by the following relationship: C + 30 mA 80 soft start VFFB(REG) where: soft−start = output ramp−up time VFFB(REG) = VFFB voltage when in regulation 30 mA = COMP output current, typ. The COMP output current range is given in the data sheet and will affect the ramp−up time. The value of the capacitor on the COMP pin will have an effect on the loop response and the transient response of the converter. Transient response can be enhanced by the addition of a parallel combination of a resistor and capacitor between the COMP pin and the comp capacitor. Feedback Divider Selection The feedback voltage measured at VFB during normal regulation will be 1.0 V. This voltage is compared to an internal 1.0 V reference and is used to regulate the output voltage. The bias current into the error amplifier is 1.0 mA max, so select the resistor values so that this current does not add an excessive offset voltage. http://onsemi.com 10 NCP5211 VFFB Feedback Selection Current Sense Component Selection To take full advantage of the V2 control scheme, a small amount of output ripple must be fed back to the VFFB pin, typically 50 mV. For most application, this requirement is simple to achieve and the VFFB can be connected directly to the VFB pin. There are some application that have to meet stringent load transient requirements. One of the key factor in achieving tight dynamic voltage regulation is low ESR. Low ESR at the regulator output results in low output voltage ripple. This situation could result in increase noise sensitivity and a potential for loop instability. In applications where the output ripple is not sufficient, the performance of the NCP5211 can be improved by adding a fixed amount external ramp compensation to the VFFB pin. Refer to Figure 7, the amount of ramp at the VFFB pin depends on the switch node Voltage, Feedback Voltage, R1 and C2. Vramp + (Vsw * VFB) tonń(R1 The current limit threshold is set by sensing a 60 mV voltage differential between the IS+ and IS− pins. Referring to Figure 8, the time constant of the R2,C1 filter should be set larger than the L/R1 time constant under worst case tolerances, to prevent overshoot in the sensed voltage and tripping the current limit too low. Resistor R3 of value equal to R2 is added for bias current cancellation. R2 and R3 should not be made too large, to reduce errors from bias current offsets. For typical L/R time constants, a 0.1 mF capacitor for C1 will allow R2 to be between 1.0 k and 10 kW. The current limit without R4 and R5, which are optional, is given by 60 mV/R1, where R1 is the internal resistance of the inductor, obtained from the manufacturer. The addition of R5 can be used to decrease the current limit to a value given by: ILIM + (60 mV * (VOUT C2) where VOUT is the output voltage. Similiarly, omitting R5 and adding R4 will increase the current limit to a value given by: where: Vramp = amount of ramp needed; Vsw = switch note voltage; VFB = voltage feedback, 1 V; ton = switch on−time. To minimize the lost in efficiency R1 resistance should be large, typically 100 k or larger. With R1 chosen, C2 can be determined by the following; C2 + (Vsw * VFB) R3ń(R3 ) R5))ńR1 ILIM + 60 mVńR1 (1 ) R2ńR4) Essentially, R4 or R5 are used to increase or decrease the inductor voltage drop which corresponds to 60 mV at the IS+ and IS− pins. IS− tonń(R1 Vramp) R3 C1 is used as a bypass capacitor and its value should be equal to or greater than C2. R5 60 mV Trip Vsw IS+ R2 C1 R1 VFFB C2 R4 Switching Node C1 VOUT L1 R2 1.0 k R1 L VFB Figure 8. Current Limit Figure 7. Small RC Filter Providing the Proper Voltage Ramp at the Beginning of Each On−Time Cycle Boost Component Selection for Upper FET Gate Drive The boost (BST) pin provides for application of a higher voltage to drive the upper FET. This voltage may be provided by a fixed higher voltage or it may be generated with a boost capacitor and charging diode, as shown in Figure 10. The voltage in the boost configuration would be the summation of the voltage from the charging diode and the output voltage swing. Care must be taken to keep the peak voltage with respect to ground less than 20 V peak. The capacitor should be large enough to drive the capacitance of the top FET. Maximum Frequency Operation The minimum pulse width may limit the maximum operating frequency. The duty factor, given by the output/input voltage ratio, multiplied by the period determines the pulse width during normal operation. This pulse width must be greater than 200 ns, or duty cycle jitter could become excessive. For low pulse widths below 300 ns, external slope compensation should be added to the VFFB pin to increase the PWM ramp signal and improve stability. 50 mV of added ramp at the VFFB pin is typically enough. http://onsemi.com 11 NCP5211 12 V 12 V 33 + 0.1 mF 33 mF/25 V × 3 18 V 2.9 mH BST VC 5.0 V/8.0 A 0.1 mF PGND 0.1 mF ROSC 0.1 mF 10 NCP5211 IS+ 51 k 100 mF/10 V × 2 GATE(L) COMP 0.1 mF + 4.7 k GATE(H) VCC 4.7 k IS− SGND LGND SENSE+ VFFB 4.02 k 1.0% VFB 1.0 k 1.0% SENSE− 10 Figure 9. Additional Application Diagram, 12 V to 5.0 V/8.0 A Converter with Differential Remote Sense 12 V 5.0 V + 33 mF/25 V × 3 2.9 mH 0.22 mF 3.3 V/8.0 A BST VC 4.7 k GATE(H) VCC PGND 0.1 mF ROSC 0.1 mF 10 NCP5211 IS+ 51 k 100 mF/10 V × 2 GATE(L) COMP 0.1 mF + 4.7 k IS− SGND LGND SENSE+ VFFB 2.32 k 1.0% VFB 1.0 k 1.0% SENSE− 10 Figure 10. Additional Application Diagram, 12 V to 5.0 V Bias to 3.3 V/8.0 A Converter with Differential Remote Sense V2 is a trademark of Switch Power, Inc. http://onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−14 NB CASE 751A−03 ISSUE L 14 1 SCALE 1:1 D DATE 03 FEB 2016 A B 14 8 A3 E H L 1 0.25 B M DETAIL A 7 13X M b 0.25 M C A S B S 0.10 X 45 _ M A1 e DETAIL A h A C SEATING PLANE DIM A A1 A3 b D E e H h L M MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.19 0.25 0.35 0.49 8.55 8.75 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ INCHES MIN MAX 0.054 0.068 0.004 0.010 0.008 0.010 0.014 0.019 0.337 0.344 0.150 0.157 0.050 BSC 0.228 0.244 0.010 0.019 0.016 0.049 0_ 7_ GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 6.50 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 14 14X 1.18 XXXXXXXXXG AWLYWW 1 1 1.27 PITCH XXXXX A WL Y WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 14X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−14 CASE 751A−03 ISSUE L DATE 03 FEB 2016 STYLE 1: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. NO CONNECTION 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. NO CONNECTION 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 2: CANCELLED STYLE 3: PIN 1. NO CONNECTION 2. ANODE 3. ANODE 4. NO CONNECTION 5. ANODE 6. NO CONNECTION 7. ANODE 8. ANODE 9. ANODE 10. NO CONNECTION 11. ANODE 12. ANODE 13. NO CONNECTION 14. COMMON CATHODE STYLE 4: PIN 1. NO CONNECTION 2. CATHODE 3. CATHODE 4. NO CONNECTION 5. CATHODE 6. NO CONNECTION 7. CATHODE 8. CATHODE 9. CATHODE 10. NO CONNECTION 11. CATHODE 12. CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 5: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. NO CONNECTION 7. COMMON ANODE 8. COMMON CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 6: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. ANODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE STYLE 7: PIN 1. ANODE/CATHODE 2. COMMON ANODE 3. COMMON CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. ANODE/CATHODE 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. COMMON CATHODE 12. COMMON ANODE 13. ANODE/CATHODE 14. ANODE/CATHODE STYLE 8: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. ANODE/CATHODE 7. COMMON ANODE 8. COMMON ANODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. NO CONNECTION 12. ANODE/CATHODE 13. ANODE/CATHODE 14. COMMON CATHODE DOCUMENT NUMBER: DESCRIPTION: 98ASB42565B SOIC−14 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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