NCP5355DR2G

NCP5355 12 V Synchronous Buck Power MOSFET Driver The NCP5355 is a dual MOSFET gate driver optimized to drive the gates of both high− and low−side Power MOSFETs in a Synchronous Buck converter. The NCP5355 is an excellent companion to multiphase controllers that do not have integrated gate drivers, such as ON Semiconductor’s NCP5314 or NCP5316. This architecture provides the power supply designer greater flexibility by being able to locate the gate drivers close to the MOSFETs. Driving MOSFETs with a 12 V source as opposed to a 5.0 V can significantly reduce conduction losses. Optimized internal, adaptive nonoverlap circuitry further reduces switching losses by preventing simultaneous conduction of both MOSFETs. The floating top driver design can accommodate MOSFET drain voltages as high as 26 V. Both gate outputs can be driven low by applying a low logic level to the Enable (EN) pin. An Undervoltage Lockout function ensures that both driver outputs are low when the supply voltage is low, and a Thermal Shutdown function provides the IC with overtemperature protection. The NCP5355 has the same pinout as the NCP5351 5.0 V Gate Driver. http://onsemi.com MARKING DIAGRAMS 8 SOIC−8 D SUFFIX CASE 751 8 1 1 8 • • • • • 8.0 V − 14 V Gate Drive Capability 2.0 A Peak Drive Current Rise and Fall Times < 15 ns Typical into 3300 pF Propagation Delay from Inputs to Outputs < 30 ns Adaptive Nonoverlap Time Optimized for Large Power MOSFETs Floating Top Driver Accommodates Applications Up to 26 V Undervoltage Lockout to Prevent Switching when the Input Voltage is Low Thermal Shutdown Protection Against Overtemperature TG to DRN Pulldown Resistor Prevents HV Supply−Induced Turn−On of Top MOSFET BG to PGND Pulldown Resistor Prevents Transient Turn On of Bottom MOSFET Internal Bootstrap Diode Reduces Parts Count and Total Solution Cost Pb−Free Package is Available SOIC−8 EP D SUFFIX CASE 751AC 8 1 5355 ALYW 1 Features • • • • • • • 5355 ALYW A L Y W = Assembly Location = Wafer Lot = Year = Work Week PIN CONNECTIONS DRN 1 8 PGND TG BST BG VS CO EN ORDERING INFORMATION Package Shipping† NCP5355D SOIC−8 98 Units/Rail NCP5355DR2 SOIC−8 2500 / Tape & Reel NCP5355DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel NCP5355PDR2 SOIC−8 EP 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.  Semiconductor Components Industries, LLC, 2004 December, 2004 − Rev. 7 1 Publication Order Number: NCP5355/D NCP5355 5V VS 5 V Regulator BST 5V Overtemp. Shutdown 5V 5V 5V VS TG Level Shift 5V Driver − + 100 k DRN 5V UVLO 8.0/7.0 V 30 k Nonoverlap 30 ns PGND 20 k 5V 5V CO 20 k Nonoverlap 30 ns 5V 5V 2.0 A 5V 30 k VS VS 5V BG Level Shift Driver EN Figure 1. Block Diagram PACKAGE PIN DESCRIPTION Pin Pin Symbol Description 1 DRN 2 TG Driver output to the high−side MOSFET gate. 3 BST Bootstrap supply voltage input. In conjunction with an internal diode to VS, a 0.1 F to 1.0 F ceramic capacitor connected between BST and DRN develops supply voltage for the high−side driver (TG). 4 CO Logic level control input produces complementary output states − no inversion at TG; inversion at BG. 5 EN Logic level enable input forces TG and BG low when EN is low. When EN is high (5.0 V), normal operation ensues. No connect defaults EN high. Note: maximum high input is 5.0 V. 6 VS Power supply input. A 0.1 F to 1.0 F ceramic capacitor should be connected from this pin to PGND. 7 BG Driver output to the low−side (synchronous rectifier) MOSFET gate. 8 PGND The switching node common to the high and low−side FETs. The high−side (TG) driver and supply (BST) are referenced to this pin. Ground. http://onsemi.com 2 NCP5355 MAXIMUM RATINGS Rating Value Unit Internally Limited °C Package Thermal Resistance: SOIC−8 Junction−to−Case, RJC Junction−to−Ambient, RJA 45 165 °C/W °C/W Package Thermal Resistance: SOIC−8 EP Junction−to−Ambient, RJA (Note 1) 50 °C/W Storage Temperature Range, TS −65 to 150 °C Lead Temperature Soldering: Reflow: (SMD styles only) (Note 2) 230 peak °C 1 − Operating Junction Temperature, TJ JEDEC Moisture Sensitivity Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling. 1. Ratings applies when soldered to an appropriate thermal area on the PCB. 2. 60 seconds maximum above 183°C. MAXIMUM RATINGS Pin Symbol Pin Name VMAX VMIN ISOURCE ISINK VS Main Supply Voltage Input 15 V −0.3 V NA 2.0 A Peak (< 100 s) 250 mA DC BST Bootstrap Supply Voltage Input 30 V wrt/PGND 15 V wrt/DRN −0.3 V wrt/DRN NA 2.0 A Peak (< 100 s) 250 mA DC DRN Switching Node (Bootstrap Supply Return) 26 V −1.0 V DC −5.0 V for 100 ns −6.0 V for 20 ns 2.0 A Peak (< 100 s) 250 mA DC NA TG High−Side Driver Output (Top Gate) 30 V wrt/PGND 15 V wrt/DRN −0.3 V wrt/DRN 2.0 A Peak (< 100 s) 250 mA DC 2.0 A Peak (< 100 s) 250 mA DC BG Low−Side Driver Output (Bottom Gate) 15 V −0.3 V 2.0 A Peak (< 100 s) 250 mA DC 2.0 A Peak (< 100 s) 250 mA DC CO TG and BG Control Input 5.5 V −0.3 V 1.0 mA 1.0 mA EN Enable Input 5.5 V −0.3 V 1.0 mA 1.0 mA PGND Ground 0V 0V 2.0 A Peak (< 100 s) 250 mA DC NA NOTE: All voltages are with respect to PGND except where noted. http://onsemi.com 3 NCP5355 ELECTRICAL CHARACTERISTICS (Note 3) (0°C < TJ < 125°C; 9.2 V < VS