NCP561
150 mA CMOS Low Iq
Low-Dropout Voltage
Regulator
The NCP561 series of fixed output low dropout linear regulators are
designed for handheld communication equipment and portable battery
powered applications which require low quiescent. The NCP561
series features an ultralow quiescent current of 3.0 A. Each device
contains a voltage reference unit, an error amplifier, a PMOS power
transistor, resistors for setting output voltage, current limit, and
temperature limit protection circuits.
The NCP561 has been designed to be used with low cost ceramic
capacitors and requires a minimum output capacitor of 1.0 F. The
device is housed in the micro-miniature TSOP-5 surface mount
package. Standard voltage versions are 1.5 V, 1.8 V, 2.5 V, 2.7 V,
2.8 V, 3.0 V, 3.3 V and 5.0 V.
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5
1
TSOP-5
SN SUFFIX
CASE 483
PIN CONNECTIONS AND
MARKING DIAGRAM
Features
VIN
1
GND
2
Enable
3
XXXAYWG
G
•Low Quiescent Current of 3.0 A Typical
•Low Dropout Voltage of 170 mV at 150 mA
•Low Output Voltage Option
•Output Voltage Accuracy of 2.0%
•Industrial Temperature Range of -40°C to 85°C
•Pb-Free Packages are Available
5 VOUT
4 N/C
(Top View)
Typical Applications
XXX
A
Y
W
G
•Battery Powered Instruments
•Hand-Held Instruments
•Camcorders and Cameras
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb-Free Package
(Note: Microdot may be in either location)
VIN
VOUT
1
5
Thermal
Shutdown
ORDERING INFORMATION
Driver w/
Current
Limit
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Enable
ON
3
OFF
GND
2
This device contains 28 active transistors
Figure 1. Representative Block Diagram
© Semiconductor Components Industries, LLC, 2007
August, 2007 - Rev. 5
1
Publication Order Number:
NCP561/D
NCP561
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
1
VIN
2
GND
3
Enable
4
N/C
5
VOUT
Description
Positive power supply input voltage.
Power supply ground.
This input is used to place the device into low-power standby. When this input is pulled low, the device is
disabled. If this function is not used, Enable should be connected to VIN.
No internal connection.
Regulated output voltage.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VIN
6.0
V
Enable Voltage
Enable
-0.3 to VIN +0.3
V
Output Voltage
VOUT
-0.3 to VIN +0.3
V
Power Dissipation and Thermal Characteristics
Power Dissipation
Thermal Resistance, Junction-to-Ambient
PD
RJA
Internally Limited
250
W
°C/W
Operating Junction Temperature
TJ
+150
°C
Operating Ambient Temperature
TA
-40 to +85
°C
Storage Temperature
Tstg
-55 to +150
°C
Input Voltage
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per MIL-STD-883, Method 3015
Machine Model Method 200 V
2. Latchup capability (85°C) "100 mA DC with trigger voltage.
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2
NCP561
ELECTRICAL CHARACTERISTICS (VIN = VOUT(nom) + 1.0 V, Venable = VIN, CIN = 1.0 F, COUT = 1.0 F, TJ = 25°C,
unless otherwise noted.)
Characteristic
Symbol
Output Voltage (TA = 25°C, IOUT = 1.0 mA)
1.5 V
1.8 V
2.5 V
2.7 V
2.8 V
3.0 V
3.3 V
5.0 V
Min
Typ
Max
1.455
1.746
2.425
2.646
2.744
2.940
3.234
4.90
1.5
1.8
2.5
2.7
2.8
3.0
3.3
5.0
1.545
1.854
2.575
2.754
2.856
3.060
3.366
5.10
-
10
10
20
20
-
30
60
150
150
-
-
VOUT
Line Regulation
1.5 V-4.4 V (VIN = Vo(nom) + 1.0 V to 6.0 V)
4.5 V-5.0 V (VIN = 5.5 V to 6.0 V)
Regline
Load Regulation (IOUT = 10 mA to 150 mA)
Regload
Output Current (VOUT = (VOUT at Iout = 150 mA) -3.0%)
1.5 V to 3.9 V (VIN = Vo(nom) + 2.0 V)
4.0 V to 5.0 V (VIN = 6.0 V)
Io(nom)
Dropout Voltage (TA = -40°C to 85°C, IOUT = 150 mA,
Measured at VOUT - 3.0%)
1.5 V - 1.7 V
1.8 V - 2.4 V
2.5 V - 2.7 V
2.8 V - 3.2 V
3.3 V - 4.9 V
5.0 V
V
mV
mV
-
330
240
150
140
130
120
500
360
250
230
200
190
-
0.1
4.0
1.0
8.0
160
160
400
400
800
800
-
60
-
1.3
-
-
0.2
-
"100
-
A
IQ
Output Short Circuit Current
1.5 V to 3.9 V (VIN = Vo(nom) + 2.0 V)
4.0 V to 5.0 V (VIN = 6.0 V)
IOUT(max)
Output Voltage Noise
(f = 20 Hz to 100 kHz, VOUT = 3.0, V IOUT = 1.0 V)
Vn
Enable Input Threshold Voltage
(Voltage Increasing, Output Turns On, Logic High)
(Voltage Decreasing, Output Turns Off, Logic Low)
Vth(en)
Output Voltage Temperature Coefficient
TC
mA
T
*TA
PD + J(max)
RJA
4. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
3
Vrms
V
3. Maximum package power dissipation limits must be observed.
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mV
mA
VIN-VOUT
Quiescent Current
(Enable Input = 0 V)
(Enable Input = VIN, IOUT = 1.0 mA to Io(nom))
Unit
ppm/°C
NCP561
180
160
3.015
VOUT = 3.0 V
VOUT, OUTPUT VOLTAGE (V)
VIN - VOUT, DROPOUT VOLTAGE (mV)
TYPICAL CHARACTERISTICS
140
150 mA Load
120
100
100 mA Load
80
60
40
50 mA Load
20
0
-50
-25
0
25
50
75
100
IOUT = 10 mA
3.010
3.005
VIN = 6.0 V
3.000
VIN = 4.0 V
2.995
2.990
2.985
2.980
2.975
-50
125
0
Figure 2. Dropout Voltage vs. Temperature
4.5
4.50
Iq, QUIESCENT CURRENT (A)
Iq, QUIESCENT CURRENT (A)
IOUT = 10 mA
VIN = 4.0 V
4.25
4.00
3.75
3.50
3.25
3.00
-50
0
3.5
3.0
2.5
2.0
1.5
100
50
VOUT = 3.0 V
IOUT = 0 mA
TA = 25°C
4.0
1
0
2
TEMPERATURE (C°)
3
4
6
5
TEMPERATURE (C°)
Figure 4. Quiescent Current vs. Temperature
Figure 5. Quiescent Current vs. Input Voltage
4.0
OUTPUT NOISE VOLTAGE (V/ǰHz)
5.0
IGND, GROUND PIN CURRENT (A)
100
Figure 3. Output Voltages vs. Temperature
4.75
VOUT = 3.0 V
IOUT = 50 mA
TA = 25°C
4.5
4.0
3.5
3.0
2.5
2.0
1.5
50
TEMPERATURE (C°)
TEMPERATURE (C°)
0
1
2
3
4
3.0
2.5
2.0
1.0 mA
1.5
1.0
150 mA
0.5
0
10
6
5
3.5
VIN, INPUT VOLTAGE (V)
100
1k
10 k
100 k
NOISE CHARACTERIZATION
Figure 7. Output Noise Voltage
Figure 6. Ground Current vs. Input Voltage
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4
1000 k
NCP561
CHANGE IN OUTPUT
VOLTAGE (mV)
60
50
40
IOUT = 10 mA
COUT = 1.0 F
400
0
-200
-400
0
0.2
0.4 0.6
0.8 1.0 1.2 1.4
TIME (s)
1.6
0
VIN = 4.0 V
VOUT = 3.0 V
CIN = 1.0 F
COUT = 10 F
Al. Elec. Surface Mount
-50
-100
-150
-200
-250
200
IOUT, OUTPUT
CURRENT (mA)
CHANGE IN OUTPUT
VOLTAGE (mV)
VIN, INPUT
VOLTAGE (mV)
TYPICAL CHARACTERISTICS
1.8 2.0
150
100
50
0
0
ENABLE
VOLTAGE (V)
0
-50
VIN = 4.0 V
VOUT = 3.0 V
CIN = 1.0 F
COUT = 10 F
Tantalum
-100
-150
-200
-250
150
100
50
0
600
TIME (s)
800
1000
1200
4
2
0
3
CIN = 1.0 F
COUT = 1.0 F
IOUT = 10 mA
2
1
0
0
200
400
600
TIME (s)
800
1000
1200
0
200
Figure 10. Load Transient Response
400
3.0
2.5
CIN = 1.0 F
COUT = 1.0 F
TA = 25°C
VENABLE = VIN
2.0
1.5
1.0
0.5
0
0
1
600 800 1000 1200 1400 1600
TIME (s)
Figure 11. Turn-On Response
3.5
VOUT, OUTPUT VOLTAGE (V)
IOUT, OUTPUT
CURRENT (mA)
400
Figure 9. Load Transient Response
VOUT, OUTPUT
VOLTAGE (V)
CHANGE IN OUTPUT
VOLTAGE (mV)
Figure 8. Line Transient Response
200
4
2
3
VIN, INPUT VOLTAGE (V)
5
Figure 12. Output Voltage vs. Input Voltage
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5
6
NCP561
DEFINITIONS
Load Regulation
Line Regulation
The change in output voltage for a change in output
current at a constant temperature.
The change in output voltage for a change in input voltage.
The measurement is made under conditions of low
dissipation or by using pulse technique such that the average
chip temperature is not significantly affected.
Dropout Voltage
The input/output differential at which the regulator output
no longer maintains regulation against further reductions in
input voltage. Measured when the output drops 3.0% below
its nominal. The junction temperature, load current, and
minimum input supply requirements affect the dropout level.
Line Transient Response
Typical over and undershoot response when input voltage
is excited with a given slope.
Thermal Protection
Internal thermal shutdown circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated at typically 160°C,
the regulator turns off. This feature is provided to prevent
failures from accidental overheating.
Maximum Power Dissipation
The maximum total dissipation for which the regulator
will operate within its specifications.
Quiescent Current
The quiescent current is the current which flows through
the ground when the LDO operates without a load on its
output: internal IC operation, bias, etc. When the LDO
becomes loaded, this term is called the Ground current. It is
actually the difference between the input current (measured
through the LDO input pin) and the output current.
Maximum Package Power Dissipation
The maximum power package dissipation is the power
dissipation level at which the junction temperature reaches
its maximum operating value, i.e. 125°C. Depending on the
ambient power dissipation and thus the maximum available
output current.
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6
NCP561
APPLICATIONS INFORMATION
Thermal
A typical application circuit for the NCP561 series is
shown in Figure 13.
As power across the NCP561 increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material and also the ambient
temperature effect the rate of temperature rise for the part.
This is stating that when the NCP561 has good thermal
conductivity through the PCB, the junction temperature will
be relatively low with high power dissipation applications.
The maximum dissipation the package can handle is
given by:
Input Decoupling (C1)
A 1.0 F capacitor either ceramic or tantalum is
recommended and should be connected close to the NCP561
package. Higher values and lower ESR will improve the
overall line transient response.
TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K
Output Decoupling (C2)
The NCP561 is a stable Regulator and does not require
any specific Equivalent Series Resistance (ESR) or a
minimum output current. Capacitors exhibiting ESRs
ranging from a few m up to 3.0 can thus safely be used.
The minimum decoupling value is 1.0 F and can be
augmented to fulfill stringent load transient requirements.
The regulator accepts ceramic chip capacitors as well as
tantalum devices. Larger values improve noise rejection and
load regulation transient response.
TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K,
or C3216X7R1C105K
T
*TA
PD + J(max)
RJA
If junction temperature is not allowed above the
maximum 125°C, then the NCP561 can dissipate up to
400 mW @ 25°C.
The power dissipated by the NCP561 can be calculated
from the following equation:
Ptot + [Vin * Ignd(Iout)] ) [Vin * Vout] * Iout
or
Enable Operation
) VOUT * IOUT
P
VINMAX + TOT
IGND ) IOUT
The enable pin will turn on the regulator when pulled high
and turn off the regulator when pulled low. These limits of
threshold are covered in the electrical specification section
of this data sheet. If the enable is not used then the pin should
be connected to VIN.
If a 150 mA output current is needed then the ground
current from the data sheet is 4.0 A. For an
NCP561SN30T1 (3.0 V), the maximum input voltage will
then be 5.6 V.
Hints
Battery or
Unregulated
Voltage
Please be sure the VIN and GND lines are sufficiently
wide. When the impedance of these lines is high, there is a
chance to pick up noise or cause the regulator to
malfunction.
Set external components, especially the output capacitor,
as close as possible to the circuit, and make leads a short as
possible.
C1
+
1
+
2
ON
3
4
OFF
Figure 13. Typical Application Circuit
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7
VOUT
5
C2
NCP561
APPLICATION CIRCUITS
Input
R1
Input
Q1
Q1
R2
R
Output
R3
5
1
1.0 F
Q2
1.0 F
2
3
Output
5
1
1.0 F
4
1.0 F
2
3
Figure 14. Current Boost Regulator
Figure 15. Current Boost Regulator
with Short Circuit Limit
The NCP561 series can be current boosted with a PNP transist‐
or. Resistor R in conjunction with VBE of the PNP determines
when the pass transistor begins conducting; this circuit is not
short circuit proof. Input/Output differential voltage minimum is
increased by VBE of the pass resistor.
Input
4
Short circuit current limit is essentially set by the VBE of Q2 and
R1. ISC = ((VBEQ2 - ib * R2) / R1) + IO(max) Regulator
Output
1
5
1.0 F
1.0 F
2
Enable
3
4
Input
1
5
1.0 F
R
1.0 F
Output
Q1
Output
1
1.0 F
5
1.0 F
2
2
3
3
R
4
5.6 V
4
C
Figure 16. Delayed Turn-on
Figure 17. Input Voltages Greater than 6.0 V
If a delayed turn-on is needed during power up of several
voltages then the above schematic can be used. Resistor R,
and capacitor C, will delay the turn-on of the bottom regulator.
A regulated output can be achieved with input voltages that
exceed the 6.0 V maximum rating of the NCP561 series with
the addition of a simple pre-regulator circuit. Care must be
taken to prevent Q1 from overheating when the regulated
output (VOUT) is shorted to GND.
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8
NCP561
ORDERING INFORMATION
Nominal
Output Voltage
Marking
Package
NCP561SN15T1
1.5
LDA
TSOP-5
NCP561SN15T1G
1.5
LDA
TSOP-5
(Pb-Free)
NCP561SN18T1
1.8
LEV
TSOP-5
NCP561SN18T1G
1.8
LEV
TSOP-5
(Pb-Free)
NCP561SN25T1
2.5
LDC
TSOP-5
NCP561SN25T1G
2.5
LDC
TSOP-5
(Pb-Free)
NCP561SN27T1
2.7
LEX
TSOP-5
NCP561SN27T1G
2.7
LEX
TSOP-5
(Pb-Free)
NCP561SN28T1
2.8
LDD
TSOP-5
NCP561SN28T1G
2.8
LDD
TSOP-5
(Pb-Free)
NCP561SN30T1
3.0
LDE
TSOP-5
NCP561SN30T1G
3.0
LDE
TSOP-5
(Pb-Free)
NCP561SN33T1
3.3
LDF
TSOP-5
NCP561SN33T1G
3.3
LDF
TSOP-5
(Pb-Free)
NCP561SN50T1
5.0
LDH
TSOP-5
NCP561SN50T1G
5.0
LDH
TSOP-5
(Pb-Free)
Device
Shipping†
3000 / 7″ Tape & Reel
NOTE: Additional voltages are available upon request by contacting your ON Semiconductor representative.
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSOP−5
CASE 483
ISSUE N
5
1
SCALE 2:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
D 5X
NOTE 5
2X
DATE 12 AUG 2020
0.20 C A B
0.10 T
M
2X
0.20 T
5
B
1
4
2
B
S
3
K
DETAIL Z
G
A
A
TOP VIEW
DIM
A
B
C
D
G
H
J
K
M
S
DETAIL Z
J
C
0.05
H
C
SIDE VIEW
SEATING
PLANE
END VIEW
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
0.95
0.037
MILLIMETERS
MIN
MAX
2.85
3.15
1.35
1.65
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
0_
10 _
2.50
3.00
1.9
0.074
5
5
XXXAYWG
G
1
1
Analog
2.4
0.094
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
1.0
0.039
XXX MG
G
Discrete/Logic
XXX = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ARB18753C
TSOP−5
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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