NCP571SN08T1G

NCP571, NCV571 Voltage Regulator - CMOS, Low Iq, Low Output 150 mA The NCP571 series of fixed output low dropout linear regulators are designed for handheld communication equipment and portable battery powered applications which require low quiescent current. The NCP571 series features an ultra−low quiescent current of 4.0 mA. Each device contains a voltage reference unit, an error amplifier, a PMOS power transistor, resistors for setting output voltage, current limit, and temperature limit protection circuits. The NCP571 has been designed to be used with low cost ceramic capacitors and requires a minimum output capacitor of 0.1 mF. The device is housed in the TSOP−5 or DFN6 surface mount package. Standard voltage versions are 0.8 V, 0.9 V, 1.0 V and 1.2 V. Features • • • • • • • 5 1 1 TSOP−5 SN SUFFIX CASE 483 XXXAYWG G XXX A Y W M G Typical Applications • Battery Powered Instruments • Hand−Held Instruments • Camcorders and Cameras DFN6 MN SUFFIX CASE 506BA 1 XX MG G = Specific Device Code = Assembly Location = Year = Work Week = Date Code = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION 1 5 Thermal Shutdown 6 MARKING DIAGRAMS Low Quiescent Current of 4.0 mA Typical Maximum Operating Voltage of 12 V Low Output Voltage Option down to 0.8 V High Accuracy Output Voltage of 3.0% Industrial Temperature Range of −40°C to +85°C (NCV571, TA = −40°C to +125°C) NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These are Pb−Free Devices Vin http://onsemi.com Vout See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. Driver w/ Current Limit + Enable ON 3 OFF GND 2 Figure 1. Representative Block Diagram © Semiconductor Components Industries, LLC, 2014 October, 2019 − Rev. 5 1 Publication Order Number: NCP571/D NCP571, NCV571 PIN CONNECTIONS TSOP−5 package Vin 1 GND 2 Enable 3 DFN6 package Vout 1 5 Vout 6 Vin NC 2 EP 4 Enable GND 3 4 NC 5 NC (Top View) (Top View) PIN FUNCTION DESCRIPTION DFN6 TSOP−5 Pin Name Description 1 5 Vout Regulated output voltage. 2 4 NC No Internal Connection. It is recommended to connect this pin to GND potential. 3 2 GND 4 3 Enable 5 − NC No Internal Connection. It is recommended to connect this pin to GND potential. 6 1 Vin Positive power supply input voltage. EP − EP No Internal Connection. It is recommended to connect this pin to GND potential. Power supply ground. This input is used to place the device into low−power standby. When this input is pulled low, the device is disabled. If this function is not used, Enable pin should be connected to Vin. MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage Vin 0 to 12 V Enable Voltage VEN −0.3 to Vin + 0.3 V Output Voltage Vout −0.3 to Vin + 0.3 V Power Dissipation PD Internally Limited W Operating Junction Temperature TJ +150 °C TA −40 to +85 −40 to +125 °C Operating Ambient Temperature NCP571 NCV571 Storage Temperature Tstg −55 to +150 °C ESD Capability, Human Body Model (Note 1) ESDHBM 2000 V ESD Capability, Machine Mode (Note 1) ESDMM 200 V ESD Capability, Charged Device Model (Note 1) ESDCDM 1000 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115) ESD Charged Device Model tested per EIA/JES D22/C101, Field Induced Charge Model (Jedec Standard) 2. Latchup capability (85°C) $100 mA DC with trigger voltage. THERMAL CHARACTERISTICS Rating Junction−to−Ambient PSIJ−Lead 2 Junction−to−Ambient PSIJ−Lead 2 NOTE: TSOP−5 TSOP−5 DFN6 DFN6 Symbol Test Conditions RqJA YJ−L2 RqJA YJ−L2 Typical Value Unit 1 oz Copper Thickness, 100 mm2 250 °C/W 1 oz Copper Thickness, 100 mm2 68 °C/W 1 oz Copper Thickness, 100 mm2 190 °C/W 1 oz Copper Thickness, 100 mm2 84 °C/W Single component mounted on an 80 x 80 x 1.5 mm FR4 PCB with stated copper head spreading area. Using the following boundary conditions as stated in EIA/JESD 51−1, 2, 3, 7, 12. http://onsemi.com 2 NCP571, NCV571 Vin 1 NC C1 0.1 mF 2 Vout Vout 5 Vin GND EN 4 3 C2 0.1 mF GND GND Enable Figure 2. Typical Application Schematic for TSOP−5 Package ELECTRICAL CHARACTERISTICS (Vin = Vout(nom) + 1.0 V, VEN = Vin, Cin = 1.0 mF, Cout = 1.0 mF, TA = 25°C, unless otherwise noted) Symbol Min Output Voltage (TA = 25°C, Iout = 10 mA) 0.8 V 0.9 V 1.0 V 1.2 V Vout − 3% 0.776 0.873 0.970 1.164 Output Voltage (TA = −40°C to +85°C for NCP571 or TA = −40°C to +125°C for NCV571, Iout = 10 mA) (Note 5) 0.8 V 0.9 V 1.0 V 1.2 V Vout − 4% Characteristic Typ Max Unit 0.8 0.9 1.0 1.2 + 3% 0.824 0.927 1.030 1.236 V + 4% V 0.768 0.864 0.960 1.152 0.8 0.9 1.0 1.2 0.832 0.936 1.040 1.248 Line Regulation (Vin = Vout + 1.0 V to 12 V, Iout = 10 mA) Regline − 10 30 mV Load Regulation (Iout = 10 mA to 150 mA, Vin = Vout + 2.0 V) Regload − 40 65 mV Output Current (Vout = (Vout at Iout = 100 mA) − 3%) 0.8 V (Vin = 3.0 V) 0.9 V (Vin = 3.0 V) 1.0 V (Vin = 3.0 V) 1.2 V (Vin = 3.0 V) Io(nom) 150 150 150 150 − − − − − − − − − − − − 730 650 550 350 850 750 650 450 − − 0.1 4.0 1.0 8.0 − 100 − 1.3 − − − − 0.3 160 160 160 160 260 260 260 260 600 600 600 600 Dropout Voltage (Iout = 10 mA, Measured at Vout − 3.0%) 0.8 V 0.9 V 1.0 V 1.2 V Vin−Vout Quiescent Current (Enable Input = 0 V) (Enable Input = Vin = 3 V, Iout = 1.0 mA to 150 mA and Vin = Enable Input = 3 V, Iout = 150 mA) IQ Output Voltage Temperature Coefficient Tc Enable Input Threshold Voltage (Voltage Increasing, Output Turns On, Logic High) (Voltage Decreasing, Output Turns Off, Logic Low) Vth(en) Output Short Circuit Current (Vout = 0 V) (Note 4) 0.8 V (Vin = 3.0 V) 0.9 V (Vin = 3.0 V) 1.0 V (Vin = 3.0 V) 1.2 V (Vin = 3.0 V) Iout(max) 3. Maximum package power dissipation limits must be observed. PD + T J(max) * T A R qJA 4. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. http://onsemi.com 3 mA mV uA ppm/°C V mA NCP571, NCV571 5. NCP571 NCV571 Tlow = −40°C Thigh = +85°C Tlow = −40°C Thigh = +125°C. 3.2 Vin = 6 V 3.0 2.8 GROUND CURRENT (mA) GROUND CURRENT (mA) 3.2 Vin = 3 V 2.6 2.4 TA = 25°C Vout = 0.8 V 2.2 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 3.0 2.8 Vin = 6 V 2.6 Vin = 3 V 2.4 2.2 0.00 0.16 TA = 25°C Vout = 1.2 V 0.02 OUTPUT CURRENT (A) 0.10 0.12 0.14 0.16 3.5 GROUND CURRENT (mA) GROUND CURRENT (mA) 0.08 Figure 4. Ground Pin Current vs. Output Current 3.5 Vin = 6 V 3.0 2.5 Vin = 3 V 2.0 Vout = 0.8 V Iout = 30 mA 1.5 −40 −20 0 20 40 60 80 3.0 Vin = 6 V 2.5 Vin = 3 V 2.0 1.5 −40 100 Vout = 1.2 V Iout = 30 mA −20 AMBIENT TEMPERATURE (°C) 3 2.5 GROUND CURRENT (mA) 3 2.5 2 1.5 1 TA = 25°C Vout = 0.8 V Iout = 30 mA 0 2 4 6 8 20 40 60 80 100 Figure 6. Ground Pin Current vs. Temperature 3.5 0.5 0 AMBIENT TEMPERATURE (°C) Figure 5. Ground Pin Current vs. Temperature GROUND CURRENT (mA) 0.06 OUTPUT CURRENT (A) Figure 3. Ground Pin Current vs. Output Current 0 0.04 10 2 1.5 1 0 12 TA = 25°C Vout = 1.2 V Iout = 30 mA 0.5 0 2 INPUT VOLTAGE (V) 4 6 8 10 INPUT VOLTAGE (V) Figure 7. Ground Pin Current vs. Input Voltage Figure 8. Ground Pin Current vs. Input Voltage http://onsemi.com 4 12 NCP571, NCV571 1.4 TA = 25°C 0.8 0.6 Iout = 70 mA Iout = 10 mA 0.4 0.2 0.0 TA = 25°C 1.2 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.0 Iout = 150 mA 0 2 4 6 8 INPUT VOLTAGE (V) 1.0 Iout = 70 mA 0.8 Iout = 10 mA 0.6 0.4 Iout = 150 mA 0.2 10 0.0 12 0 Figure 9. Output Voltage vs. Input Voltage 2 4 6 8 INPUT VOLTAGE (V) 10 Figure 10. Output Voltage vs. Input Voltage Figure 11. Line Transient Response Figure 12. Line Transient Response 3 V to 4 V Figure 13. Line Transient Response Figure 14. Line Transient Response http://onsemi.com 5 12 NCP571, NCV571 Figure 15. Load Transient Response VENA Figure 16. Load Transient Response VENA VENA: 1 V/div Figure 17. Enable Operation VENA: 1 V/div Figure 18. Enable Operation http://onsemi.com 6 NCP571, NCV571 APPLICATIONS INFORMATION A typical application circuit for the NCP571 series is shown in Figure 2. without fear of instabilities. Larger values improve noise rejection and load regulation transient response. Input Decoupling (C1) Enable Operation A 0.1 mF capacitor either ceramic or tantalum is recommended and should be connected close to the NCP571 package. Higher values and lower ESR will improve the overall line transient response. The enable pin will turn on or off the regulator. These limits of threshold are covered in the electrical specification section of this data sheet. If the enable is not used then the pin should be connected to Vin. It is not recommended to leave this pin on air. In case the voltage of Enable signal is higher then Input voltage of NCP571 device it is necessary add an resistor divider in order to keep voltage at Enable pin bellow Input voltage. A single gate device of VHC family could be used for this logic level translation. The NL17SZ06 device could be chosen for non inverting open−drain buffer as shown in Figure 19. Other possibility is using NL17SZ16 device as shown in Figure 20. More information is mentioned in Application Note AND8101/D. Output Decoupling (C2) The NCP571 is a stable Regulator and does not require any specific Equivalent Series Resistance (ESR) or a minimum output current. Capacitors exhibiting ESRs ranging from a few mW up to 3.0 W can thus safely be used. The minimum decoupling value is 0.1 mF and can be augmented to fulfill stringent load transient requirements. The regulator accepts ceramic chip capacitors as well as tantalum devices. Larger output capacitors can be used NCP571 Vout Vin Vin Vout NC GND C1 Enable 0.1 mF C2 0.1 mF GND GND 3.3 V 3.3 V 0V Enable NL17SZ06 Figure 19. http://onsemi.com 7 NCP571, NCV571 Vin NCP571 2.7 V Vout Vin Vout NC GND C1 Enable C2 0.1 mF 0.1 mF GND GND 2.7 V 3.3 V 0V 0V Enable NL17SZ16 Figure 20. Hints conductivity through the PCB, the junction temperature will be relatively low with high power dissipation applications. The maximum dissipation the package can handle is given by: Please be sure the Vin and GND lines are sufficiently wide. When the impedance of these lines is high, there is a chance to pick up noise or cause the regulator to malfunction. Set external components, especially the output capacitor, as close as possible to the circuit, and make leads as short as possible. PD + T J(max) * T A R qJA If junction temperature is not allowed above the maximum 125°C, then the NCP571 can dissipate up to 400 mW @ 25°C. The power dissipated by the NCP571 can be calculated from the following equation: Thermal As power across the NCP571 increases, it might become necessary to provide some thermal relief. The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and also the ambient temperature effect the rate of temperature rise for the part. This is stating that when the NCP571 has good thermal P tot + V in(max)ǒI GND ) I outǓ * V out * I out If a 150 mA output current is needed then the ground current from the data sheet is 4.0 mA. http://onsemi.com 8 NCP571, NCV571 ORDERING INFORMATION Nominal Output Voltage Marking Package Shipping† NCP571SN08T1G 0.8 N6A TSOP−5 (Pb−Free) 3000 / Tape & Reel NCP571SN09T1G 0.9 N6E TSOP−5 (Pb−Free) 3000 / Tape & Reel NCP571SN10T1G 1.0 N6C TSOP−5 (Pb−Free) 3000 / Tape & Reel NCP571SN12T1G 1.2 N6D TSOP−5 (Pb−Free) 3000 / Tape & Reel NCV571SN08T1G* 0.8 N6F TSOP−5 (Pb−Free) 3000 / Tape & Reel NCV571SN09T1G* 0.9 N6G TSOP−5 (Pb−Free) 3000 / Tape & Reel NCV571SN10T1G* 1.0 N6H TSOP−5 (Pb−Free) 3000 / Tape & Reel NCV571SN12T1G* 1.2 N6J TSOP−5 (Pb−Free) 3000 / Tape & Reel NCP571MN08TBG 0.8 AC DFN6 (Pb−Free) 3000 / Tape & Reel NCP571MN09TBG 0.9 AD DFN6 (Pb−Free) 3000 / Tape & Reel NCP571MN10TBG 1.0 AE DFN6 (Pb−Free) 3000 / Tape & Reel NCP571MN12TBG 1.2 AA DFN6 (Pb−Free) 3000 / Tape & Reel NCV571MN08TBG* 0.8 AF DFN6 (Pb−Free) 3000 / Tape & Reel NCV571MN09TBG* 0.9 AG DFN6 (Pb−Free) 3000 / Tape & Reel NCV571MN10TBG* 1.0 AH DFN6 (Pb−Free) 3000 / Tape & Reel NCV571MN12TBG* 1.2 AJ DFN6 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 9 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−5 CASE 483 ISSUE N 5 1 SCALE 2:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSION A. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. D 5X NOTE 5 2X DATE 12 AUG 2020 0.20 C A B 0.10 T M 2X 0.20 T 5 B 1 4 2 B S 3 K DETAIL Z G A A TOP VIEW DIM A B C D G H J K M S DETAIL Z J C 0.05 H C SIDE VIEW SEATING PLANE END VIEW GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 0.95 0.037 MILLIMETERS MIN MAX 2.85 3.15 1.35 1.65 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 0_ 10 _ 2.50 3.00 1.9 0.074 5 5 XXXAYWG G 1 1 Analog 2.4 0.094 XXX = Specific Device Code A = Assembly Location Y = Year W = Work Week G = Pb−Free Package 1.0 0.039 XXX MG G Discrete/Logic XXX = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) 0.7 0.028 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ARB18753C TSOP−5 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN6, 2x2.2, 0.65P CASE 506BA−01 ISSUE A 6 DATE 07 JUL 2008 1 SCALE 4:1 A B D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L L1 ÉÉÉ ÉÉÉ PIN ONE REFERENCE 2X 0.10 C DETAIL A E ALTERNATE TERMINAL CONSTRUCTIONS TOP VIEW ÉÉ ÉÉ ÉÉ EXPOSED Cu 2X 0.10 C A 0.10 C DIM A A1 b D D2 E E2 e K L L1 A3 MOLD CMPD A1 ÇÇ ÉÉ DETAIL B DETAIL B ALTERNATE CONSTRUCTIONS 7X 0.08 C SIDE VIEW C A1 L SEATING PLANE e 6X 3 1 1 L1 6 4 6X BOTTOM VIEW XX MG G XX = Specific Device Code M = Date Code G = Pb−Free Device E2 K GENERIC MARKING DIAGRAM* D2 DETAIL A 6X MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 0.30 2.00 BSC 1.10 1.30 2.20 BSC 0.70 0.90 0.65 BSC 0.20 −−− 0.25 0.35 0.00 0.10 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. b 0.10 C A B 0.05 C SOLDERING FOOTPRINT* NOTE 3 1.36 PACKAGE OUTLINE 6X 0.58 2.50 0.96 1 6X 0.35 0.65 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON23023D 6 PIN DFN, 2.0X2.2, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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