NCP6915AFCCLT1G

ON Semiconductor Is Now To learn more about onsemi™, please visit our website at www.onsemi.com onsemi and       and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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It is optimized to supply battery powered portable application sub−systems such as camera function, microprocessors ... etc. This device integrates one high efficiency 600 mA Step−down DCDC converter with DVS (Dynamic Voltage Scaling) and 5 low dropout (LDO) voltage regulators in WLCSP16 package. www.onsemi.com WLCSP16 CASE 567GF Features • One DCDC Converter: MARKING DIAGRAM* Peak Efficiency 96% ♦ Programmable Output Voltage from 0.8 V to 2.3 V by 50 mV Steps ♦ 600 mA Output Current Capability Five Low Noise − Low Dropout Regulators ♦ Programmable Output Voltage from 1.7 V to 3.3 V for LDOs 1, 2, 3 ♦ Programmable Output Voltage from 1.2 V to 2.85 V for LDO 4 & 5 ♦ 200 mA Output Current Capability: LDO’s 1, 2, 3 & 4 ♦ 300 mA Output Current Capability: LDO 5 ♦ 45 mVrms Low Output Noise Control ♦ 400 kHz / 3.4 MHz I2C Control Interface ♦ Hardware Enable Pin ♦ Customizable Power up Sequencer Extended Input Voltage Range 2.5 V to 5.5 V ♦ Support of Newest Battery Technologies Optimized Power Efficiency ♦ 82 mA Very Low Quiescent Current at no Load ♦ Dynamic Voltage Scaling on DCDC Converter ♦ Regulators can be Supplied from DCDC Converter Output Small footprint ♦ Package WLCSP16 1.56 x 1.56 mm2 ♦ DCDC Converter runs at 3.0 MHz using a 1 mH Inductor and 10 mF Capacitor or 2.2 mH Inductor and 4.7 mF Capacitor This is a Pb−Free Device ♦ • • • • • • 6915x ALYWW G 6915x A L Y WW G = Specific Device Code (x = A or B) = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *Pb−Free indicator, “G” or microdot “ G”, may or may not be present. PIN ASSIGNMENT 1 2 3 4 A VOUT2 VOUT1 FB PVIN B VIN1 SCL HWEN SW C AGND VBG SDA PGND D VOUT3 VOUT4 VIN2 VOUT5 Typical Applications • • • • Cellular Phones Digital Cameras Personal Digital Assistant and Portable Media Player GPS (Top View) This document contains information on some products that are still under development. ON Semiconductor reserves the right to change or discontinue these products without notice. © Semiconductor Components Industries, LLC, 2014 June, 2017 − Rev. 5 1 ORDERING INFORMATION See detailed ordering and shipping information on page 23 of this data sheet. Publication Order Number: NCP6915/D NCP6915 NCP6915 PVIN VBG 100 nF AGND DCDC1 600 mA Core 2 .2uF System Supply DCDC1 Out SW 1 uH FB 10 uF PGND 1uF System Supply System Supply Or DCDC Out VIN1 VIN2 1uF Thermal Protection Enabling HWEN Power Up/ Down Sequencer SDA Processor I2C I2C SCL LDO1 200 mA VOUT1 LDO2 200 mA VOUT2 LDO3 200 mA VOUT3 LDO4 200 mA VOUT4 LDO5 300 mA VOUT5 Figure 1. Functional Block Diagram www.onsemi.com 2 1.0 uF 1.0 uF 1.0 uF 1.0 uF 1.0 uF NCP6915 Table 1. PIN OUT DESCRIPTION Pin Name Type Description VIN1 Power Input Analog Supply. This pin is the device analog, digital and LDO 1, 2 & 3 supply. A 1.0 mF ceramic capacitor or larger must bypass this input to ground. This capacitor should be placed as close a possible to this pin. C2 VBG Analog Input Reference Voltage. A 0.1 mF ceramic capacitor must bypass this pin to the ground C1 AGND Analog Ground POWER B1 Analog Ground. Analog and digital modules ground. Must be connected to the system ground. CONTROL AND SERIAL INTERFACE B3 HWEN Digital Input Hardware Enable. Active high will enable the part; there is internal pull down resistor on this pin. B2 SCL Digital Input I2C interface Clock C3 SDA Digital Input/Output I2C interface Data DCDC Power Supply. This pin must be decoupled to ground by a 2.2 mF ceramic capacitor. This capacitor should be placed as close a possible to this pin. DCDC CONVERTER A4 PVIN Power Input B4 SW Power Output DCDC Switch Power pin connects power transistors to one end of the inductor. Typical application uses 1.0 mH inductor; refer to application section for more information. A3 FB Analog Input DCDC Feedback Voltage. Must be connected to the output capacitor. This is the input to the error amplifier. C4 PGND Power Ground DCDC Power Ground. This pin is the power ground and carries the high switching current. High quality ground must be provided to prevent noise spikes. To avoid high−density current flow in a limited PCB track, a local ground plane is recommended. LDO REGULATORS B1 VIN1 Power Input LDO 1,2 & 3 Power and Core supply (see Power table) D3 VIN2 Power Input LDO 4&5 Power Supply This pin requires a 1 mF decoupling capacitor. A2 VOUT1 Power Output LDO 1 Output Power. This pin requires a 1 mF decoupling capacitor. A1 VOUT2 Power Output LDO 2 Output Power. This pin requires a 1 mF decoupling capacitor. D1 VOUT3 Power Output LDO 3 Output Power. This pin requires a 1 mF decoupling capacitor. D2 VOUT4 Power Output LDO 4 Output Power. This pin requires a 1 mF decoupling capacitor. D4 VOUT5 Power Output LDO 5 Output Power. This pin requires a 1 mF decoupling capacitor. Table 2. MAXIMUM RATINGS Symbol Rating Analog and power pins: AVIN, PVIN, SW, VIN1, VIN2, VOUT1, VOUT2, VOUT3, VOUT4, VOUT5, FB, VBG Pins Value Unit VA −0.3 to +6.0 V VDG IDG −0.3 to VA +0.3 ≤ 6.0 10 V mA Storage Temperature Range TSTG −65 to + 150 °C Maximum Junction Temperature TJMAX −40 to +150 °C MSL Level 1 Digital pins: SCL, SDA, HWEN Pin: Input Voltage Input Current Moisture Sensitivity (Note 1) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A. www.onsemi.com 3 NCP6915 Table 3. RECOMMENDED OPERATING CONDITIONS Symbol Parameter VIN1 PVIN Core Power Supply, DCDC power supply and LDOs 1, 2&3 Conditions VIN2 Min Typ 2.5 Max Unit 5.5 V LDOs 4 & 5 Input Voltage range 1.7 5.5 V TA Ambient Temperature Range −40 25 +85 °C TJ Junction Temperature Range (Note 3) −40 25 +125 °C RqJA Thermal Resistance Junction to Case − 80 − °C/W TA = 25°C − 1250 − mW TA = 85°C − 500 − mW 2.2 mH PD L Power Dissipation Rating (Note 5) Inductor for DCDC converter (Note 2) Co 1 Output Capacitor for DCDC Converter (Note 2) 10 mF 1 mF Output Capacitors for VBG 100 nF Cpvin Input Capacitor for DCDC Converter (Note 2) 2.2 mF Cvin1 Input Capacitor for Vin1 (Note 2) 1 mF Cvin2 Input Capacitor for Vin2 (Note 2) 1 mF Output Capacitors for LDO (Note 2) CBG 0.65 Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 2. Refer to the Application Information section of this data sheet for more details. 3. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation. 4. The RqCA is dependent of the PCB heat dissipation. Board used to drive this data was a 2” x 2” NCPXXXEVB board. It is a multilayer board with 1−once internal power and ground planes and 2−once copper traces on top and bottom of the board. 5. The maximum power dissipation (PD) is dependent by input voltage, maximum output current and external components selected. R qCA + 125 * T A PD * R qJC with ǒR qJA + R qJC ) R qCAǓ Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TJ up to +125°C unless otherwise specified. PVIN = VIN1 = VIN2 = 3.6 V (Unless otherwise noted). DCDC Output Voltage = 1.2 V, LDO1, 2 & 4= 2.8 V, LDO 3 & 5 = 1.8 V, Typical values are referenced to TJ = + 25°C and default configuration (Note 7). Symbol Parameter Conditions Min Typ Max − 32 − Unit SUPPLY CURRENT: PINS VIN1, VIN2, PVIN DCDC on – no load – no switching LDOs off TA = up to +85°C IQ ISLEEP Operating quiescent current Product sleep mode current mA DCDC on – no load – no switching LDOs on – no load TA = up to +85°C − 82 − DCDC Off LDOs on – no load TA = up to +85°C − 65 − HWEN on All DCDC and LDOs off VIN = 2.5 V to 5.5 V TA = up to +85°C − 7 − mA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Devices that use non−standard supply voltages which do not conform to the intent I2C bus system levels must relate their input levels to the VDD voltage to which the pull−up resistors RP are connected. 7. Refer to the Application Information section of this data sheet for more details. 8. Guaranteed by design and characterized. www.onsemi.com 4 NCP6915 Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TJ up to +125°C unless otherwise specified. PVIN = VIN1 = VIN2 = 3.6 V (Unless otherwise noted). DCDC Output Voltage = 1.2 V, LDO1, 2 & 4= 2.8 V, LDO 3 & 5 = 1.8 V, Typical values are referenced to TJ = + 25°C and default configuration (Note 7). Symbol Parameter Conditions Min Typ Max Unit − 0.3 − mA 2.5 − 5.5 V SUPPLY CURRENT: PINS VIN1, VIN2, PVIN IOFF Product off current HWEN off I2C interface disabled VIN = 2.5 V to 5.5 V TA = up to +85°C DCDC CONVERTER PVIN Input Voltage Range IOUTMAX Maximum Output Current (Note 8) 0.6 − − A DVOUT Output Voltage DC Error Io = 300 mA, PWM mode −1.5 0 1.5 % DCOUT DCDC Output voltage Programmable 50 mV steps (Note 8) 0.8 2.3 V FSW Switching Frequency IPK Peak Inductor Current Open loop 2.5 V ≤ PVIN ≤ 5.5 V Load Regulation Line Regulation D tSTART RDISDCDC 2.7 3 3.3 MHz 1.0 1.3 1.6 A IOUT from 300 mA to IOUTMAX − −0.5 − %/A IOUT = 300 mA 2.5 V ≤ VIN ≤ 5.5 V − 0 − %/V − 100 − % − 128 − 8 − W LDO1, LDO2, LDO3 input voltage Range 2.5 − 5.5 V Maximum Output Current 200 − − mA − 500 mA 130 mA Maximum Duty Cycle Soft−Start Time I2C Time from command ACK to 90% of Output Voltage, Vout = 1.2 V. DCDC Active Output Discharge ms LDO1, LDO2, LDO3 VIN1 IOUTMAX1,2, 3 ISC1,2, 3 Short Circuit Protection Foldback Current Vout1, 2, 3 tSTART1 DVOUT1,2, 3 VDROP Output voltage Programmable, see table. (Note 8) 1.7 Soft−Start Time Time from I2C command ACK to 90% of Output Voltage. − 128 IOUT1,2, 3 = 150 mA −2 VNOM +2 % Load Regulation IOUT1,2, 3 = 0 mA to 200 mA − 0.4 − % Line Regulation VIN1 = (Vout + Drop) to 5.5 V VOUT1,2 = 2.8 V, VOUT3 = 1.8 V IOUT1,2,3 = 200 mA − 0.3 − Output Voltage Accuracy DC Dropout Voltage IOUT1,2,3 = 200 mA, VOUT = 3.3 V − 2% IOUT1,23 = 200 mA, VOUT = 2.8 V − 2% 3.3 V ms % 160 mV − 185 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Devices that use non−standard supply voltages which do not conform to the intent I2C bus system levels must relate their input levels to the VDD voltage to which the pull−up resistors RP are connected. 7. Refer to the Application Information section of this data sheet for more details. 8. Guaranteed by design and characterized. www.onsemi.com 5 NCP6915 Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TJ up to +125°C unless otherwise specified. PVIN = VIN1 = VIN2 = 3.6 V (Unless otherwise noted). DCDC Output Voltage = 1.2 V, LDO1, 2 & 4= 2.8 V, LDO 3 & 5 = 1.8 V, Typical values are referenced to TJ = + 25°C and default configuration (Note 7). Symbol Parameter Conditions Min Typ Max Unit F = 1 kHz, 100 mV peak to peak VOUT1,2 = 2.8 V, VOUT3 = 1.8 V IOUT1,2,3 = 5 mA − −70 − F = 10 kHz, 100 mV peak to peak VOUT1,2 = 2.8 V, VOUT3 = 1.8 V IOUT1,2,3 = 5 mA − −60 − 10 Hz ³ 100 kHz, 5 mA VOUT1,2,3 = 2.8 V − 45 − mV − 25 − W LDO4 and LDO5 Input Voltage 1.7 − 5.5 V IOUTMAX4 Maximum Output Current 200 − − mA IOUTMAX5 Maximum Output Current 300 − − mA LDO1, LDO2, LDO3 PSRR Ripple Rejection Noise RDISLDO1,2, 3 LDO Active Output Discharge dB LDO4 and LDO5 VIN2 ISC4 Short Circuit Protection − 500 − mA ISC5 Short Circuit Protection − 600 − mA ISC4 Foldback Protection 130 − mA ISC5 Foldback Protection 190 − mA 2.85 V Vout4,5 LDO 4&5 Output voltage tSTART2 Soft−Start Time DVOUT4 DVOUT5 VDROP Programmable, see table. (Note 8) 1.2 − Time from I2C command ACK to 90% of Output Voltage. − 128 Output Voltage Accuracy IOUT4 = 200 mA −2 VNOM +2 % Output Voltage Accuracy IOUT5 = 300 mA −2 VNOM +2 % Load Regulation IOUT4 = 0 mA to 200 mA IOUT5 = 0 mA to 300 mA − 0.4 − % Line Regulation VIN2 = (Vout + Drop) to 5.5 V VOUT4 = 2.8 V, VOUT5 = 1.8 V IOUT4 = 200 mA, IOUT5 = 300 mA − 0.3 − % Dropout Voltage IOUT4,5 = 200 mA VOUT4,5 = 2.8 V − 2% − 165 mV IOUT5 = 300 mA VOUT5 = 1.8 V − 2% PSRR Ripple Rejection Noise RDISLDO4,5 ms 290 F = 1 kHz, 100 mV peak to peak IOUT4= 5 mA, IOUT5 = 5 mA − −70 − F = 10 kHz, 100 mV peak to peak IOUT4,5 = 5 mA − −60 − 10 Hz ³ 100 kHz, 5 mA VOUT4,5 = 2.8 V − 45 − mV − 25 − W LDO 4&5 Active Output Discharge dB HWEN VIH High level input Voltage Threshold 1.1 − − V VIL Low level Voltage Threshold − − 0.4 V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Devices that use non−standard supply voltages which do not conform to the intent I2C bus system levels must relate their input levels to the VDD voltage to which the pull−up resistors RP are connected. 7. Refer to the Application Information section of this data sheet for more details. 8. Guaranteed by design and characterized. www.onsemi.com 6 NCP6915 Table 4. ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TJ up to +125°C unless otherwise specified. PVIN = VIN1 = VIN2 = 3.6 V (Unless otherwise noted). DCDC Output Voltage = 1.2 V, LDO1, 2 & 4= 2.8 V, LDO 3 & 5 = 1.8 V, Typical values are referenced to TJ = + 25°C and default configuration (Note 7). Symbol Parameter Conditions Min Typ Max Unit 0.1 1 mA 1.7 − 5.0 V HWEN IEN I2C VI2C Voltage at SCL and SDA line VI2CIL SCL, SDA low input voltage SCL, SDA pin (Note 6) − − 0.5 V VI2CIH SCL, SDA high input voltage SCL, SDA pin (Note 6) 0.8 x VI2CC − − V VI2COL SCL, SDA low output voltage ISINK = 3 mA (Note 8) − − 0.4 V FSCL I2C clock frequency (Note 8) − − 3.4 MHz VUVLO Under Voltage Lockout VIN falling − − 2.3 V VUVLOH Under Voltage Lockout Hysteresis VIN rising 60 − 200 mV TSD Thermal Shut Down Protection − 150 − °C TWARNING Warning Rising Edge − 135 − °C TSDR Thermal Shut Down Rearming − 110 − °C TOTAL DEVICE Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. Devices that use non−standard supply voltages which do not conform to the intent I2C bus system levels must relate their input levels to the VDD voltage to which the pull−up resistors RP are connected. 7. Refer to the Application Information section of this data sheet for more details. 8. Guaranteed by design and characterized. www.onsemi.com 7 NCP6915 DETAILED DESCRIPTION capabilities of the device can be exceeded. A thermal protection circuit is therefore implemented to prevent the part from damage. This protection circuit is only activated when the core is in active mode (at least one output channel is enabled). During thermal shutdown, all outputs of NCP6915 are off. When NCP6915 returns from thermal shutdown, it can re−start in two different configurations depending on REARM[7:6] bits ($09 register). If REARM[7:6] = 00 then NCP6915 re−starts with default register values, otherwise it re−starts with register values set prior to thermal shutdown. In addition, a thermal warning is implemented which can inform the processor through an interrupt that NCP6915 is close to its thermal shutdown so that preventive action can be taken by software. The NCP6915 is optimized to supply the different sub systems of battery powered portable applications. The IC can be supplied directly from the latest technology single cell batteries such as Lithium−Polymer as well as from triple alkaline cells. Alternatively, the IC can be supplied from a pre−regulated supply rail in case of multi−cell or mains powered applications. The output voltage range, current capabilities and performance of the switched mode DCDC converter are well suited to supply the different peripherals in the system as well as to supply processor cores. To reduce overall power consumption of the application, Dynamic Voltage Scaling (DVS) is supported on the DCDC converter. For PWM operation, the converter runs on a local 3 MHz clock. A low power PFM mode is provided that ensures that even at low loads high efficiency can be obtained. All the switching components are integrated including the compensation networks and synchronous rectifier. Small sized 1 uH inductor and 10 uF bypass capacitor are required for typical applications. The general purpose low dropout regulators can be used to supply the lower power rails in the application. To improve on overall application standby current, the bias current of these regulators are made very low. The regulators have two separated input supply pin to be able to connect them independently to either the system supply voltage or to the output of the DCDC converter in the application. The regulators are bypassed with a small size 1.0 uF capacitor. The IC is controlled through the I2C interface that allows to program amongst others the output voltages of the different supply rails as well as to configure its behavior. In addition to this bus, a digital hardware enable control pin (HWEN) is provided. Active Output Discharge By default, to prevent any disturbances on power−up sequence, output discharge is activated as soon as the input voltage is valid (upper than UVLO+ hyst). After power up sequence and during ON state, output discharge can be independently enabled / disabled by appropriate settings in the DIS register (refer to the register definition section). If a power down sequence, UVLO or thermal shutdown events occur, the output discharge paths are activated until the next PUS and ON state. When the IC is turned off when VIN1 drops down below UVLO threshold, no shut down sequence is expected, all supplies are disabled and outputs turn to high impedance. Enabling The HWEN pin controls the device start up. If HWEN is raised, this starts the power up sequencer (PUS). If HWEN is made low, device enters in shutdown mode and all regulators will be turned off with inverted PUS of power up. A built−in pull−down resistor disables the device if this pin is left unconnected. When HWEN is high, the different power rails can be independently enabled / disabled by writing the appropriate bit in the ENABLE register. Under Voltage Lockout The core does not operate for voltages below the under voltage lockout (UVLO) threshold and all internal circuitry, both analog and digital, is held in reset. NCP6915 functionality is guaranteed down to VUVLO when the battery is falling. A hysteresis is implemented to avoid erratic on / off behavior of the IC. Due to its 200 mV hysteresis, when the battery is rising, re−start is guaranteed at 2.5 V. Power Up Sequence and HWEN When enabling part with HWEN pin, the part will be set with the default configuration factory programmed in the registers, if no I2C programming has been done as described in the below table. Thermal Shutdown Given the output power capabilities of the on chip step down converters and low drop out regulators the thermal www.onsemi.com 8 NCP6915 Table 5. DEFAULT POWER UP SEQUENCER Device Delay (in ms) from Tstart Sequence Default Assignment Default Vprog Default Mode and ON/OFF NCP6915AFCCLT1G 128 To: 000 DCDC 1.2 V Auto PFM/PWM OFF 256 T1: 001 LDO1 2.8 V OFF 512 T2: 011 LDO2 2.8 V OFF 640 T3: 100 LDO3 1.8 V OFF 768 T4: 101 LDO4 2.8 V OFF 896 T5: 110 LDO5 1.8 V OFF 128 To: 000 DCDC 2.1 V Auto PFM/PWM ON 384 T1: 001 LDO1 3.0 V ON 512 T2: 011 LDO2 2.8 V OFF 640 T3: 100 LDO3 2.8 V OFF 640 T4: 101 LDO4 1.8 V ON 256 T5: 110 LDO5 1.8 V ON NCP6915BFCCLT1G NOTE: Additional power sequence are available. Please contact your ON Semiconductor representative for further information. VIN1, VIN2 UVLO POR HWEN VOUT DCDC O F F 600 us typ (DCDC_T[2:0] + 1) x 128 ms * M O DVS ramp Time VOUT LDOx D E (LDOx_T[2:0] + 1) x 128 ms * Bias Time 128 us Soft start 90% I@C Figure 3. IPUS Figure 2. IPUS In order to power up the circuit, the input voltage VIN1 has to rise above the VUVLO threshold. This triggers the internal core circuitry power up including: • Internal references • Core circuitry “Wake Up Time” • DCDC “Bias Time” The initial power up sequence (IPUS) is described in Figure 2. Remark 1: T2 – T1 = 2x 128 ms in the default configuration. Can be reprogrammed at 128 ms by I2C. Remark 2: LDOs must be turned on sequentially to avoid inrush current on Vin source. So it’s strongly recommended to turn them one by one, even if the default PUS sequence is changed by I2C. These delays are internals and cannot be bypassed. www.onsemi.com 9 NCP6915 As the default configuration factory is programmed with disable state for the DCDC and LDOs, an I2C access must be done at the end of the bias time to enable the supplies. In addition a user programmable delay will also take place between end of Core circuitry turn on (Bias time) and Start up time: The PowerSupplies_T[2..0] bits of TIME register will set this user programmable delay with a 128 ms resolution (note: please contact your ON Semiconductor representative for additional resolution options). The output discharge of the DCDC and LDOs are done during this time slot. NOTE: During the Bias time, the I2C interface is not active during the first 50 ms. Any I2C request to the IC during this time period will result in a NACK reply. However, I2C registers can be read and written while HWEN pin is still low (except blanking time of 50 ms typical). By programming the appropriate registers (see registers description section), the power up sequence default can be modified and set upon requirements (please contact your ON representative for additional PUS options) VIN1, VIN2 UVLO POR HWEN VOUT DCDC Bias time 32ms VOUT LDOx Soft start 90% 128 us I@C LDOx, DCDC OFF/ ON Figure 5. ON Mode PUS (OPUS) Shutdown by HWEN VIN1, VIN2 When HWEN is tied low, all supplies are disabled with reverted turn on sequence detailed in default Power Up Sequencer table. If different turn off sequence is required, a different programming can be done by I2C. UVLO POR HWEN (DCDC _T[2:0] + 1) x 128 ms* S L E E P VOUT DCDC O F F VOUT LDOx M O D E M O D E 70 us typ 600ms Bias min Time I@C DVS ramp Time Ì Ì DCDC Converter The converter can operate in two modes: PWM mode and PFM mode. In PWM mode the converter operates at a fixed frequency and adapts its duty cycle to regulate to the desired output voltage. The advantage of this mode is that the EMI noise is predictable. However, at lower loadings the efficiency is degraded. In PFM mode some switching pulses are skipped to control the output voltage. This allows maintaining high efficiency even at low loadings. In addition, no high frequency clock is required which provides additional current savings. The switchover point between both modes is chosen depending on the supply conditions such that highest efficiency is obtained over the entire load range. The switch over between PWM/PFM modes can occur automatically but the switcher can be set in auto switching mode PFM / PWM by I2C programming. A soft start is provided to limit inrush currents when enabling the converters. The soft start consists of ramping gradually the reference to the switcher. Additional current limitation is provided by a peak current limiter that monitors and limits the current through the inductor. DCDC converter output voltage can be set by I2C MODEDCDC bit is used to program switcher mode control DVS ramp Time (LDOx_T[2:0] + 1) x 128 ms* 128 us Soft start 90% Figure 4. Sleep Mode PUS (SMPUS) A third turn on sequence is also available by I2C. Indeed each power supply can be turn off/on through I2C register. In this case no biasing time is required except for DCDC bias time (32 ms typical). www.onsemi.com 10 NCP6915 DCDC Step Down Converter and LDOs End of Turn on Sequence Table 6. MODEDCDC BIT DESCRIPTION MODEDCDC DCDC Mode Control 0 Mode is auto switching PFM / PWM (default) 1 Mode is PWM only To indicate the end of the power up sequence, a power good sense bit is available at the $0A address. (SEN_PG). Sense bit is set to 0 during power up sequence and 16 x digital clock (128 ms by default). The Power good sense bit is released to 1 after this sequence and trig ACK_PG interrupt. The interrupt is reset by a read or HWEN. Dynamic Voltage Scaling (DVS) Step down converters support dynamic voltage scaling (DVS). This means the output voltage can be reprogrammed based upon I2C commands to provide the different voltages required by the processor. The change between set points is managed in a smooth manner without disturbing the operation of the processor. When programming a higher voltage, the reference of the switcher and therefore the output is raised in 50 mV/ 2.67 ms (default) steps such that the dV/dt is controlled. When programming a lower voltage the output voltage will decrease based on the output capacitor value and the load. The DVS system makes sure that the voltage ramp down will not exceed the steps settings. V2 Internal Reference Output Voltage Figure 7. Power good behavior DV Interrupt Dt The interrupt controller continuously monitors internal interrupt sources, generating an interrupt signal when a system status change is detected (dual edge monitoring). The interrupt sources include: Figure 6. Dynamic Voltage Scaling Effect Timing Programmability DCDC converter has two different output voltages programmed by default in the DCDC_V1 and V2 bank. The DCDC output voltage can be changed from V1 to V2 with the DCDC_V2/V1 bit in $08 register. Table 9. INTERRUPT SOURCES Register UVLO PUS Table 7. DCDC_V2/1 BIT DESCRIPTION DCDC_V2/1 WNRG TSD Bit Description 0 Output voltage is set to DCDC_V2 1 Output voltage is set to DCDC_V1(Default) 1 10.67 ms per step Thermal shutdown The I2C registers are reset when the part is in Off Mode: • Vin