NCP718BMT330TBG

Low Dropout Regulator, Wide Input Voltage, Low Iq, 300 mA NCP718 The NCP718 is 300 mA LDO Linear Voltage Regulator. It is a very stable and accurate device with ultra−low quiescent current consumption (typ. 4 mA over the full temperature range) and a wide input voltage range (up to 24 V). The regulator incorporates several protection features such as Thermal Shutdown and Current Limiting. www.onsemi.com MARKING DIAGRAMS Features • • • • • • • • • • • • • • WDFN6 MT SUFFIX CASE 511BR Operating Input Voltage Range: 2.5 V to 24 V Fixed Voltage Options Available: 1.2 V to 5 V (upon request) Adjustable Voltage Option from 1.2 V to 5 V Ultra−Low Quiescent Current: typ. 4 mA over Temperature ±2% Accuracy Over Full Load, Line and Temperature Variations PSRR: 60 dB at 1 kHz Noise: typ. 36 mVRMS from 100 Hz to 100 kHz Stable with Small 1 mF Ceramic Capacitor Soft−start to Reduce Inrush Current and Overshoots Thermal Shutdown and Current Limit Protection SOA Limiting for High Vin / High Iout – Static / Dynamic Active Discharge Option Available (upon request) Available in TSOT−23−5 and WDFN6 2x2 mm Packages These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant 1 XX M 1 XX = Specific Device Code M = Date Code TSOT−23−5 SN SUFFIX CASE 419AE 1 XX MG G 1 XX = Specific Device Code M = Date Code* G = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. PIN CONNECTIONS Typical Applications • Wireless Chargers • Portable Equipment • Communication Systems 1 NC/ADJ 2 GND 3 V OUT V IN IN C IN OUT EN GND NC C OUT ON IN 5 NC 4 EN WDFN6 2x2 mm (Top View) OUT NCP718 1 mF Ceramic GND 6 1 mF Ceramic OUT IN OFF GND Figure 1. Typical Application Schematic NC/ADJ EN TSOT−23−5 (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2017 September, 2019 − Rev. 9 1 Publication Order Number: NCP718/D NCP718 IN IN ENABLE LOGIC EN BANDGAP REFERENCE THERMAL SHUTDOWN BANDGAP REFERENCE MOSFET DRIVER WITH CURRENT LIMIT INTEGRATED SOFT−START ENABLE LOGIC EN THERMAL SHUTDOWN MOSFET DRIVER WITH CURRENT LIMIT INTEGRATED SOFT−START OUT OUT ADJ * ACTIVE DISCHARGE Version A only * ACTIVE DISCHARGE Version A only EN EN GND GND Fixed Version Adjustable Version Figure 2. Simplified Block Diagram Table 1. PIN FUNCTION DESCRIPTION Pin No. (WDFN6) Pin No. (TSOT−23−5) Pin Name 6 1 IN 3, EXP 2 GND 4 3 EN Enable pin. Driving this pin high turns on the regulator. Driving EN pin low puts the regulator into shutdown mode. 2 4 NC / ADJ Fixed Version: No connection. This pin can be tied to ground to improve thermal dissipation or left disconnected. Adjustable Version: Feedback pin for set−up output voltage. Use resistor divider for voltage selection. 1 5 OUT Regulated output voltage pin. A small 1 mF ceramic capacitor is needed from this pin to ground to assure stability. 5 − N/C No connection. This pin can be tied to ground to improve thermal dissipation or left disconnected. Description Input pin. A small capacitor is needed from this pin to ground to assure stability. Power supply ground. Table 2. ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Input Voltage (Note 1) Rating VIN −0.3 to 24 V Enable Voltage VEN −0.3 to VIN+0.3 V Output Voltage VOUT −0.3 to VIN+0.3 (max. 6) V tSC Indefinite s TJ(MAX) 150 °C Output Short Circuit Duration Maximum Junction Temperature TSTG −55 to 150 °C ESD Capability, Human Body Model (Note 2) ESDHBM 2000 V ESD Capability, Charged Device Model (Note 2) ESDCDM 1000 V Storage Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114) ESD Charged Device Model tested per EIA/JESD22−C101, Field Induced Charge Model. Latch up Current Maximum Rating tested per JEDEC standard: JESD78. Latch−up is not guaranteed on ENABLE pin. Table 3. THERMAL CHARACTERISTICS Rating Symbol Value Unit Thermal Characteristics, WDFN6, 2 mm x 2 mm Thermal Resistance, Junction−to−Air RqJA 65 °C/W Thermal Characteristics, TSOT−23−5 Thermal Resistance, Junction−to−Air RqJA 235 °C/W www.onsemi.com 2 NCP718 Table 4. ELECTRICAL CHARACTERISTICS -40°C ≤ TJ ≤ 125°C; VIN = 2.5 V or (VOUT + 1.0 V), whatever is greater; IOUT = 1 mA, CIN = COUT = 1 mF, unless otherwise noted. Typical values are at TJ = +25°C. (Note 3) Parameter Test Conditions Symbol Min Max Unit VIN 2.5 24 V −40°C ≤ TJ ≤ 125°C, VOUT < 1.8 V VOUT + 1 V < VIN < 16 V, 0.1 mA < IOUT < 300 mA (Note 5) VOUT ≥ 1.8 V VOUT −3% +3% V −2% +2% Reference Voltage −40°C ≤ TJ ≤ 125°C, VOUT + 1 V < VIN < 16 V VADJ Reference Voltage Accuracy −40°C ≤ TJ ≤ 125°C, VOUT + 1 V < VIN < 16 V VOUT Line Regulation VOUT + 1 V ≤ VIN ≤ 16 V, Iout = 1 mA RegLINE 10 mV Load Regulation IOUT = 0.1 mA to 300 mA RegLOAD 10 mV VDO 480 Operating Input Voltage Output Voltage Accuracy (fixed versions) Dropout Voltage (Package TSOT−23−5) Dropout Voltage (Package WDFN6) Maximum Output Current Disable Current Quiescent Current Ground current VDO = VIN – (VOUT(NOM) – 3%), IOUT = 300 mA (Note 4) VDO = VIN – (VOUT(NOM) – 3%), IOUT = 300 mA (Note 4) 2.1 V – 2.4 V 1.2 −2% Output Noise Voltage Enable Input Threshold Voltage +2% 490 2.8 V − 3.2 V 295 465 3.3 V – 4.9 V 275 440 5V 250 380 2.1 V – 2.4 V VDO mV 490 2.5 V − 2.7 V 335 505 2.8 V − 3.2 V 305 475 3.3 V – 4.9 V 285 450 5V 260 395 ILIM VEN = 0 V, VIN = 5 V IDIS IOUT = 0 mA, −40°C ≤ TJ ≤ 125°C IOUT = 10 mA 300 V mV 320 VIN = VOUT + 1 V (Note 5) VIN = 3.5 V + 100 mVpp VOUT = 2.5 V IOUT = 1 mA, Cout = 1 mF V 2.5 V − 2.7 V 800 mA 0.1 1.0 mA IQ 4.0 8.0 mA IGND 50 IOUT = 300 mA Power Supply Rejection Ratio Typ mA 300 f = 1 kHz PSRR 60 dB VOUT = 1.2 V, IOUT = 10 mA f = 100 Hz to 100 kHz VN 36 mVrms Voltage increasing VEN_HI 1.2 − − − V Voltage decreasing VEN_LO − 0.4 ADJ Pin Current VIN = VOUT + 1 V IADJ 0.1 1.0 EN Pin Current VEN = 5.5 V IEN 100 nA VIN = 5.5 V, VEN = 0 V Rdis 100 W Temperature increasing from TJ = +25°C TSD 165 °C Temperature falling from TSD TSDH Active Output Discharge Resistance Thermal Shutdown Temperature (Note 6) Thermal Shutdown Hysteresis (Note 6) − 25 − mA °C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Performance guaranteed over the indicated operating temperature range by design and/or characterization production tested at TJ = TA = 25°C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible. 4. Voltage dropout for voltage variants below 2.1 V is given by minimum input voltage 2.5 V. 5. Respect SOA 6. Guaranteed by design and characterization. www.onsemi.com 3 NCP718 TYPICAL CHARACTERISTICS 1.212 1.208 4.0 VIN = 2.5 V VOUT = 1.2 V CIN = 1 mF COUT = 1 mF 1.204 IQ, QUIESCENT CURRENT (mA) VOUT, OUTPUT VOLTAGE (V) 1.220 1.216 IOUT = 1 mA 1.200 1.196 1.192 1.188 1.184 1.180 −40 0 20 40 60 80 VOUT = 1.2 V CIN = 1 mF COUT = 1 mF 2.2 2.0 4 8 6 10 12 16 14 18 20 22 24 0.10 0.09 VIN = 24 V 0.4 0.3 VIN = 2.5 V 0.2 0.1 0 −40 −20 0 20 40 60 80 100 0.08 0.07 0.06 VEN = VIN VOUT = 1.2 V IOUT = 10 mA CIN = 1 mF COUT = 1 mF 0.05 120 VIN = 24 V 0.04 0.03 VIN = 2.5 V 0.02 0.01 0 −40 −20 0 20 40 60 80 100 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 5. Disable Current vs. Temperature Figure 6. Current to Enable Pin vs. Temperature ISC, SHORT CIRCUIT CURRENT (mA) 30 IGND, GROUND CURRENT (mA) 2.6 2.4 Figure 4. Quiescent Current vs. Input Voltage 0.5 VIN = 2.5 V VOUT = 1.2 V CIN = 1 mF COUT = 1 mF 18 15 12 9 6 3 0 0 2.8 Figure 3. Output Voltage vs. Temperature − VOUT = 1.2 V 0.6 21 −40°C 3.0 VIN, INPUT VOLTAGE (V) 0.7 24 25°C 3.2 TJ, JUNCTION TEMPERATURE (°C) 0.8 27 3.4 2 CIN = 1 mF COUT = 1 mF 0.9 125°C 3.6 120 100 IEN, ENABLE CURRENT (mA) IDIS, DISABLE CURRENT (mA) 1.0 −20 3.8 1 2 3 4 5 6 7 8 9 10 640 VIN = 2.5 V VOUT = 1.2 V CIN = 1 mF COUT = 1 mF 620 600 580 560 540 520 500 480 460 440 −40 −20 0 20 40 60 80 100 IOUT, OUTPUT CURRENT (mA) TJ, JUNCTION TEMPERATURE (°C) Figure 7. Ground Current vs. Output Current − VOUT = 1.2 V Figure 8. Short Circuit Current vs. Temperature www.onsemi.com 4 120 120 NCP718 0.40 0.36 480 420 360 300 240 f = 50 Hz Duty = 20% CIN = 1 mF COUT = 1 mF 180 120 60 0 0 RR, RIPPLE REJECTION (dB) VDROP, DROPOUT VOLTAGE (V) 600 540 2 4 6 8 10 12 14 16 18 22 20 0.16 0.12 0.08 0.04 0 VDIF, DIFFERENTIAL VOLTAGE VIN − VOUT (V) IOUT, OUTPUT CURRENT (A) Figure 9. SOA Current Limit vs. Differential Voltage Figure 10. Dropout Voltage vs. Output Current − VOUT = 2.5 V 80 80 1 mA 70 60 10 mA 50 40 10 VIN = 3.5 V VOUT = 2.5 V CIN = 1 mF COUT = 1 mF MLCC, X7R, 0805 100 mA 1 mA 10 mA 70 60 50 40 100 mA VIN = 12 V VOUT = 2.5 V CIN = 1 mF COUT = 1 mF MLCC, X7R, 0805 30 20 10 0 10 100 1K 10K 100K 1M 10M 10 100 1K 10K 100K 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 11. Power Supply Rejection Ratio vs. Current, VIN = 3.5 V, COUT = 1 mF Figure 12. Power Supply Rejection Ratio vs. Current, VIN = 12 V, COUT = 1 mF 100K OUTPUT VOLTAGE NOISE (nV/√Hz) 100K 10K 1K 100 −40°C 0 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36 0.40 0 OUTPUT VOLTAGE NOISE (nV/√Hz) 0.24 0.20 90 20 125°C 25°C 0.28 90 30 VOUT = 2.5 V CIN = 1 mF COUT = 1 mF 0.32 24 RR, RIPPLE REJECTION (dB) SOA CURRENT LIMITATION (mA) TYPICAL CHARACTERISTICS VIN = 2.5 V VOUT = 1.2 V IOUT = 10 mA CIN = 1 mF COUT = 1 mF MLCC, X7R, 0805 10 10K 1K VIN = 2.8 V VOUT = 1.8 V IOUT = 10 mA CIN = 1 mF COUT = 1 mF MLCC, X7R, 0805 100 10 10 100 1K 10K 100K 1M 10 100 1K 10K 100K FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Output Voltage Noise Spectral Density for VOUT = 1.2 V, IOUT = 10 mA, COUT = 1 mF Figure 14. Output Voltage Noise Spectral Density for VOUT = 1.8 V, IOUT = 10 mA, COUT = 1 mF www.onsemi.com 5 1M NCP718 APPLICATIONS INFORMATION The maximum power dissipation the NCP718 can handle is given by: The NCP718 is the member of new family of Wide Input Voltage Range Low Dropout Regulators which delivers Ultra Low Ground Current consumption, Good Noise and Power Supply Rejection Ratio Performance. The NCP718 incorporates EN pin and soft−start feature for simple controlling by microprocessor or logic. P D(MAX) + (eq. 1) R qJA The power dissipated by the NCP718 for given application conditions can be calculated from the following equations: Input Decoupling (CIN) It is recommended to connect at least 1 mF ceramic X5R or X7R capacitor between IN and GND pin of the device. This capacitor will provide a low impedance path for any unwanted AC signals or noise superimposed onto constant input voltage. The good input capacitor will limit the influence of input trace inductances and source resistance during sudden load current changes. Higher capacitance and lower ESR capacitors will improve the overall line transient response. P D [ V INǒI GND(I OUT)Ǔ ) I OUTǒV IN * V OUTǓ (eq. 2) or V IN(MAX) [ P D(MAX) ) ǒV OUT I OUTǓ (eq. 3) I OUT ) I GND Hints VIN and GND printed circuit board traces should be as wide as possible. When the impedance of these traces is high, there is a chance to pick up noise or cause the regulator to malfunction. Place external components, especially the output capacitor, as close as possible to the NCP718, and make traces as short as possible. Output Decoupling (COUT) The NCP718 does not require a minimum Equivalent Series Resistance (ESR) for the output capacitor. The device is designed to be stable with standard ceramics capacitors with values of 1 mF or greater. The X5R and X7R types have the lowest capacitance variations over temperature thus they are recommended. ADJUSTABLE VERSION The output voltage can be set by using a resistor divider as shown in Figure 15 with a range of 1.2 V to 5 V. The appropriate resistor divider can be found by solving the equation below, while VREF = 1.2 V Power Dissipation and Heat Sinking The maximum power dissipation supported by the device is dependent upon board design and layout. Mounting pad configuration on the PCB, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. For reliable operation junction temperature should be limited to +125°C. V OUT + V REF @ ǒ Ǔ (R1 ) R2) + V REF @ 1 ) R2 R1 R1 (eq. 4) Value of R1 and R2 is recommended to keep below 100 kW for R1 and below 1 MW for R2 to avoid influence of current IADJ variation over temperature range. V OUT V IN C IN ƪTJ(MAX) * TAƫ IN OUT NCP 718 ADJ version ADJ EN GND 1 μF Ceramic R2 R1 ON OFF C OUT 1 μF Ceramic Figure 15. Adjustable Version Connection Schematic 30 μVRMS * VOUT. Do not operate the device at output voltage about 5.2 V, as device can be damaged. Please note that output noise is amplified by VOUT / VADJ ratio. For simplified calculation, output noise is equal to www.onsemi.com 6 NCP718 ORDERING INFORMATION Device Part No. Voltage Option Marking NCP718AMTADJTBG Adj. GA NCP718AMT120TBG 1.2 V GN NCP718AMT180TBG 1.8 V GP NCP718AMT250TBG 2.5 V GD NCP718AMT300TBG 3.0 V GQ NCP718AMT330TBG 3.3 V GR NCP718AMT500TBG 5.0 V GM NCP718BMTADJTBG Adj. GC NCP718BMT180TBG 1.8 V GU NCP718BMT300TBG 3.0 V GV NCP718BMT330TBG 3.3 V GW NCP718BMT500TBG 5.0 V GE NCP718ASNADJT1G Adj. GAA NCP718ASN120T1G 1.2 V GAE NCP718ASN150T1G 1.5 V GAF NCP718ASN180T1G 1.8 V GAD NCP718ASN250T1G 2.5 V GAG NCP718ASN300T1G 3.0 V GAH NCP718ASN330T1G 3.3 V GAJ NCP718ASN500T1G 5.0 V GAK NCP718BSNADJT1G Adj. GAC NCP718BSN120T1G 1.2 V GCA NCP718BSN150T1G 1.5 V GCC NCP718BSN180T1G 1.8 V GCD NCP718BSN250T1G 2.5 V GCF NCP718BSN300T1G 3.0 V GCG NCP718BSN330T1G 3.3 V GCH NCP718BSN500T1G 5.0 V GCE Option Package Shipping† WDFN6 (Pb−Free) 3000 / Tape & Reel TSOT−23−5 (Pb−Free) 3000 / Tape & Reel With Active Output Discharge Without Active Output Discharge With Active Output Discharge Without Active Output Discharge †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOT−23, 5 LEAD CASE 419AE−01 ISSUE O DATE 19 DEC 2008 SYMBOL D MIN NOM A e E1 MAX 1.00 A1 0.01 0.05 0.10 A2 0.80 0.87 0.90 b 0.30 c 0.12 E 0.45 0.15 D 2.90 BSC E 2.80 BSC E1 1.60 BSC e 0.95 TYP L 0.30 L1 0.40 0.20 0.50 0.60 REF L2 0.25 BSC 0º θ 8º TOP VIEW A2 A b q L A1 c L2 L1 SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-193. DOCUMENT NUMBER: DESCRIPTION: 98AON34392E TSOT−23, 5 LEAD Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WDFN6 2x2, 0.65P CASE 511BR ISSUE B ÉÉ ÉÉ ÇÇ SCALE 4:1 D A B A1 0.10 C 0.10 C ALTERNATE B−1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25 mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. FOR DEVICES CONTAINING WETTABLE FLANK OPTION, DETAIL A ALTERNATE CONSTRUCTION A-2 AND DETAIL B ALTERNATE CONSTRUCTION B-2 ARE NOT APPLICABLE. MOLD CMPD ALTERNATE B−2 ALTERNATE CONSTRUCTIONS E L L DIM A A1 A3 b D D2 E E2 e L L1 L1 TOP VIEW ALTERNATE A−1 ALTERNATE A−2 DETAIL A A3 DETAIL B 0.05 C ÉÉ ÉÉ ÇÇ EXPOSED Cu DETAIL B ÍÍÍ ÍÍÍ ÍÍÍ PIN ONE REFERENCE A3 DATE 19 JAN 2016 ALTERNATE CONSTRUCTIONS A 6X 0.05 C A1 NOTE 4 C SIDE VIEW D2 DETAIL A 1 3 SEATING PLANE GENERIC MARKING DIAGRAM* 1 L XX M XX = Specific Device Code M = Date Code E2 6 4 6X *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. b e BOTTOM VIEW MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.25 0.35 2.00 BSC 1.50 1.70 2.00 BSC 0.90 1.10 0.65 BSC 0.20 0.40 --0.15 0.10 M C A 0.05 M C B RECOMMENDED MOUNTING FOOTPRINT NOTE 3 1.72 6X 0.45 1.12 PACKAGE OUTLINE 6X 0.40 2.30 1 0.65 PITCH DIMENSIONS: MILLIMETERS DOCUMENT NUMBER: DESCRIPTION: 98AON55829E WDFN6 2X2, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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