NCP81031MNTWG

NCP81031 Product Preview Low Voltage Synchronous Buck Controller with Power Saving and Transient Enhancement Features http://onsemi.com MARKING DIAGRAMS 1 XXXXX A L Y W G Features • • • • (Note: Microdot may be in either location) VCC ROSC/EN CSP PIN CONNECTIONS 16 15 14 13 VCCP 1 12 CSN/VO LG 2 11 FBG LX 3 10 VSEN BOOT 4 9 FB 7 8 COMP 6 SYNC 5 PGOOD High Performance Operational Error Amplifier Internal Soft−Start/Stop ±0.5% internal Voltage Accuracy, 0.8 V voltage reference OCP accuracy, Four Re−entry Times Before Latch “Lossless” Differential Inductor Current Sensing Internal high precision current sensing amplifier Oscillator Frequency Range of 100 kHz − 1000 kHz 20 ns Adaptive FET Non−overlap Time of internal Gate Driver 5.0 V to 12 V Operation Support 1.5 V to 19 V Vin Vout from 0.8 V to 3.3 V (5 V with 12 VCC) Chip enable through OSC pin Latched Over Voltage Protection (OVP) Internally fixed OCP Threshold Guaranteed Startup Into Pre−Charged Loads Thermally Compensated Current Monitoring Thermal Shutdown Protection Integrated MOSFET Drivers Integrated BOOST diode with internal Rbst = 2.2 W Automatic Power Saving Mode to Maximize Efficiency During Light Load Operation Sync Function Remote Ground Sensing Enhanced Transient Protection This is a Pb−Free Device = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package GND • • • • • • • • • • • • • • • • • • • • XXXXX XXXXX ALYWG G QFN16 CASE 485G UG The NCP81031 is a simple single phase solution with differential phase current sensing, low current power saving mode of operation, and on board gate drivers to provide accurately regulated power. It can be set up to synchronize to an external clock or PWM signal within certain frequency range. The adaptive non overlap gate drive and power saving operation circuit provide a low switching loss and high efficiency solution for server, notebook, and desktop systems. A high performance operational error amplifier is provided to simplify compensation of the system. The NCP81031 features include soft−start sequence, accurate overvoltage and over current protection, UVLO for VCC and VCCP, and thermal shutdown. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. Applications • Desktop and Server Systems This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. © Semiconductor Components Industries, LLC, 2011 March, 2011 − Rev. P0 1 Publication Order Number: NCP81031/D VCC PGOOD NCP81031 15 6 2.2 W Over Current Detector CSP 13 4 BOOT 5 UG 3 LX 1 VCCP 2 LG CDIFF + − Current Sense Amplifier CSN/VO 12 − COMP 8 FBG 11 VREF*75% UVP Control Logic, Protection, RAMP Generator and PWM Logic + + 0.8V − Error Amplifier FB 9 + VREF*125% 1.24V SYNC 7 Programmable VREF*50% UVLO Control OVP − − VSEN 10 ROSC/EN 14 OSC OVP, UNLATCHED + OSC 16 GND Figure 1. NCP81031 BLOCK DIAGRAM PIN DESCRIPTIONS Pin No. Symbol Description 1 VCCP 2 LG Bottom gate MOSFET driver pin. 3 LX Switch node 4 BOOT Power supply for MOSFET drivers Supply rail for the floating top gate drier. 5 UG 6 PGOOD Power Good. It is an open−drain output set free after SS (with 3x clock delay) as long as the output voltage monitored through VSEN is within specifications. 7 SYNC Synchronization Pin. The controller synchronizes on the falling edge of a square wave provided to this pin. Short to GND if not used. 8 COMP Output of the error amplifier. The device cannot be disabled by grounding this pin 9 FB 10 VSEN Output Voltage Sensing 11 FBG Remote Ground Sense 12 CSN/VO 13 CSP 14 ROSC/EN 15 VCC Supply rail for the controller internal circuitry. GND Ground reference 16 THERMAL PAD Top gate MOSFET driver pin. Inverting input to the error amplifier Inductor differential sense inverting input Inductor differential sense non−inverting input Programs the switching frequency; EN: Pull−low to disable the device Connects with the Silicon substrate for good thermal contact with the PCB. Connect to GND plane http://onsemi.com 2 NCP81031 13 LX VSEN CH1 10 CF1 ROSC/EN COMP LG 2 LOUT1 5 3 Q4 2 1 ENABLE JP3 2 R2 VOUT + COUT1 2 FB 8 RVFB1 CBOOT1 UG FBG 9 RF1 1 4 ROSC1 11 RFB3 Q3 1 CSP NCP5230 CSN/VO 12 CFB2 BOOT GND RS4 SYNC VCCP 3 7 CSEN1 16 RSEN1 PGOOD VCC 6 RS3 RISO1 RFB2 VIN 15 RNTC1 14 SYNC VCCP 3 VCC PGOOD 1 ETCH R1 Figure 2. Typical Application Circuit ABSOLUTE MAXIMUM RATINGS Rating Symbol VMAX VMIN Unit VCC, VCCP 15 −0.3 V BOOT 35V wrt/GND 40 V 7.5 V −0.3 − 5.5 V ROSC open −10 − 10 % 10 − kHz / mA − 0.75 V CURRENT SENSE AMPLIFIERS Common Mode Input Voltage Range (Note 1, GNG, output within 10 mV) OSCILLATOR (with no ROSC Resistor Defaults to 200 kHz) Switching Frequency Accuracy OSC Gain (Note 1) Disable threshold ROSC/EN pin, Vdis_th − MODULATORS (PWM Comparators) Minimum Pulse Width Fsw = 200 kHz, OSC open Minimum Turn Off Time (LG on) Fsw = 200 kHz, OSC open Magnitude of the PWM Ramp 250 VIN = 5 V or 12 V Maximum Duty Cycle Minimum Skip mode frequency 80 300 ns 400 1.50 ns V OSC/EN = OPEN 80 − 95 % In light load, maximum time for LG to turn on after HG turns off 30 − − kHz SOFT−START Soft Start Time @ 200 kHz 1024 clock cycles, OSC/EN open 5.12 ms Rdis 200 W SOFT−OFF Soft OFF bleeding resistor OVER CURRENT PROTECTION First Over Current Threshold Second Over Current Threshold CSP−CSN, 4xMasking 17 CSP−CSN, Immediate action 20 23 30 mV mV SYNC PIN Synchronization Input VIL, square wave Synchronization Input VIH, square wave 1.0 2.5 V V PROTECTION AND PGOOD Output Voltage Logic Low, Sinking 4 mA OVP Threshold VSEN rising above 1.25 * Vref 120 VSEN falling below 0.75 * Vref Vth_disoff with respect to 0.5 Vref UVP Threshold Unlatched Overvoltage Threshold 0.4 V 125 130 % 70 75 80 % 40 50 60 % ZERO CURRENT DETECTION (LX Pin) Blanking Time before Zero Current Detection (Note 1) Blanking Time after LG is < 1.0 V 40 ns Capture Time for LX Voltage (Note 1) Time to capture LX voltage once LG is < 1.0 V (must be within dead time limits) 20 ns Negative LX detection voltage Vbdls 200 300 400 mV Positive LX detection voltage Vbdhs 0.2 0.5 1 V 300 kHz 3 − 3.7 ms LX−GND, Includes ± 2 mV Offset Range −6.0 −4.0 −2.0 mV −16 0 15 mV Time for Vth adjustment and settling time (Note 1) Initial Negative Current Detection Threshold Voltage Set Point (Note 1) Vth adjustable Range (Note 1) 1. Guaranteed by design. 2. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. Reference Gate Timing Diagram. http://onsemi.com 5 NCP81031 ELECTRICAL CHARACTERISTICS Unless otherwise stated: 0°C < TA < 85°C; 4.5 V < VCC < 13.2 V; CVCC = 0.1 mF Parameter Test Conditions Min Typ Max Unit VBOOT − VLX = 12 V, Cload = 3 nF 2.5 5 W VBOOT − VLX = 12V 2 2.5 W ns HIGH SIDE DRIVER UG RH_TG Output Resistance, Sourcing RH_TG Output Resistance, Sinking TrDRVH Transition Time CLOAD = 3 nF − 16 − TfDRVH Transition Time CLOAD = 3 nF − 11 − Driving High, CLOAD = 3 nF, VCC = 12 V, VCCP =12 V 10 20 30 TpdhDRVH Propagation Delay (Notes 1, 2) UG Internal Resistor to LX ns Unbiased, BOOT − LX = 0 45 VLX = GND, Cload = 3 nF 2 3 W VLX = VCC 1 1.5 W ns kW LOW SIDE DRIVER LG RH_BG Output Resistance, Sourcing RL_BG Output Resistance, Sinking TrDRVL Transition Time CLOAD = 3 nF − 16 − TfDRVL Transition Time CLOAD = 3 nF − 11 − Driving High, CLOAD = 3 nF, VCCP = 12 V, VCCP = 12 V TBD 18 TBD TpdhDRVL Propagation Delay (Notes 1, 2) LX Internal Resistor to GND 45 ns kW THERMAL SHUTDOWN Tsd Thermal Shutdown (Note 1) Tsdhys Thermal Shutdown Hysteresis (Note 1) 150 180 50 − °C °C 1. Guaranteed by design. 2. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. Reference Gate Timing Diagram. http://onsemi.com 6 NCP81031 1V 1V Figure 3. Gate Timing Diagram Switching Frequency Synchronization Function Connecting a resistor from ROSC/EN to external voltage source Vpu will configure the frequency. Normal range would be 100 kHz to 1 MHz. With no resistor connected to the pin, the oscillator frequency is 200 kHz. The switching frequency will follow the relationship: Synchronize through the SYNCH pin. Synchronization function allows different converters to share the same input filter reducing the resulting Irms and reducing the need for total caps to sustain the load. Synchronized systems also exhibits higher noise immunity and better regulation. The device synchronizes the high−side MOSFET turn−on with the falling edge of the SYNCH pin input signal. In order for internal switching to track the external signal, the external signal has to fall within 0−40% frequency window above the internal frequency set by the OSC pin. SYNCH pin can be connected to other regulators’ PWM, phase node, gate signals according to the desired phase−shift with proper voltage scaling. F SW + 200 kHz * V pu * 1.240 R OSC @ 10 kHz mA (eq. 1) When Rosc = infinity (no resistor connected), Fsw = 200 kHz; when Vpu = ground, the frequency programmed will be higher than 200 kHz. Soft−Start Soft−Start will begin if VCC, VCCP are both above their UVLO threshold and EN pin is set free. IC initially waits a fixed delay time and then ramping−up the reference in 1024 clock cycles in closed−loop regulation. After digital soft start, PGOOD signal will be released with three clock cycles delay. Protection active during soft−start: • Overvoltage Protection always enabled; • Undervoltage Protection is enabled after reference voltage ramps up to 80% of the final value. In soft−start, a UVP fault will directly restart a complete soft−start. Protection Scheme • • • • • PGOOD Overvoltage Protection (OV) Undervoltage Protection (UV) PreOVP Protection, monitor CSN/VO when IC is disabled. Vin detection: If UV is triggered during SS, it will restart SS after a fixed delay. http://onsemi.com 7 NCP81031 Vin POR_VCC UVLO_VCC VCC 1.24V OSC/EN 0.75V LG (Stays Low until first PWM pulse except in case of a Fault) UG OVP (125%Vref) Vref = 0.8 V 80% Vrer OCP/ Normal shutdown Vout. FB Vth_disoff (50%Vref) v v Softstop UV monitor SoftStart Normal 1024cycle ~5ms@200kHzz Pre-OVP valid Figure 4. Start Up and Shutdown Timing Diagram http://onsemi.com 8 NCP81031 PWR ON EN>Vdis_th No VCC> POR & VCCDR > UVLO _VCCDR (16− pin ) Yes PreOVP detection BG on VSEN >OV Vth VCC > POR & VCCDR > UVLO _ VCCDR BOOT >UVLO_BOOT No Yes Fosc detection Soft Start , Normal Operation OCP, OVP, UVP detection UV (after Vout reaches UV threshold in softstart ) OC OV UVP OVP TG OFF, BG OFF PGOOD=0 TG OFF, BG ON PGOOD =0 OCP 4 times reentry After 4 times reentry for 1st threshod or immediately over 2nd threshold No Vout < Vth_disoff TG OFF, BG OFF Yes Vo discharge mode Yes OVP Vcc