NCP81071BDR2G

Dual 5 A High Speed Low-Side MOSFET Drivers with Enable NCP81071 NCP81071 is a high speed dual low−side MOSFETs driver. It is capable of providing large peak currents into capacitive loads. This driver can deliver 5 A peak current at the Miller plateau region to help reduce the Miller effect during MOSFETs switching transition. This driver also provides enable functions to give users better control capability in different applications. ENA and ENB are implemented on pin 1 and pin 8 which were previously unused in the industry standard pin−out. They are internally pulled up to driver’s input voltage for active high logic and can be left open for standard operations. This part is available in MSOP8−EP package, SOIC8 package and WDFN8 3 mm x 3 mm package. Features • • • • • • • • • • High Current Drive Capability ±5 A TTL/CMOS Compatible Inputs Independent of Supply Voltage Industry Standard Pin−out High Reverse Current Capability (6 A) Peak Enable Functions for Each Driver 8 ns Typical Rise and 8 ns Typical Fall Times with 1.8 nF Load Typical Propagation Delay Times of 20 ns with Input Falling and 20ns with Input Rising Input Voltage from 4.5 V to 20 V Dual Outputs can be Paralleled for Higher Drive Current These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Applications • • • • • • • • www.onsemi.com MARKING DIAGRAMS 8 SOIC−8 D SUFFIX CASE 751 XXXX ALYW G 1 XXXX AYW G MSOP−8 Z SUFFIX CASE 846AM 1 1 XX MG G WDFN8 MN SUFFIX CASE 511CD XX A L Y W M G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb−Free Package (Note: Microdot may be in either location) Server Power Telecommunication, Datacenter Power Synchronous Rectifier Switch Mode Power Supply DC/DC Converter Power Factor Correction Motor Drive Renewable Energy, Solar Inverter PIN CONNECTIONS 1 8 ENA ENB INA OUTA GND VDD OUTB INB (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. © Semiconductor Components Industries, LLC, 2016 March, 2021 − Rev. 4 1 Publication Order Number: NCP81071/D NCP81071 VDD VDD ENA ENA VDD Ref VDD INA Logic A Channel VDD OUTA INA VDD INB OUTA UVLO VDD ENB OUTB Ref Logic B Channel VDD VDD Ref VDD UVLO OUTB VDD Logic A Channel VDD ENB Ref VDD Ref VDD Ref VDD VDD GND Logic B Channel INB Ref GND Ref NCP81071A NCP81071B VDD VDD ENA VDD Ref VDD INA Logic A Channel VDD OUTA VDD Ref VDD VDD UVLO ENB OUTB Ref INB Logic B Channel GND Ref NCP81071C Figure 1. NCP81071 Block Diagram Table 1. PIN DESCRIPTION Pin No. Symbol Description 1 ENA Enable input for the driver channel A with logic compatible threshold and hysteresis. This pin is used to enable and disable the driver output. It is internally pulled up to VDD with a 200 kW resistor for active high operation. The output of the pin when the device is disabled will be always low. 2 INA Input of driver channel A which has logic compatible threshold and hysteresis. If not used, this pin should be connected to either VDD or GND. It should not be left unconnected. 3 GND Common ground. This ground should be connected very closely to the source of the power MOSFET. 4 INB Input of driver channel B which has logic compatible threshold and hysteresis. If not used, this pin should be connected to either VDD or GND. It should not be left unconnected. 5 OUTB Output of driver channel B. The driver is able to provide 5 A drive current to the gate of the power MOSFET. 6 VDD Supply voltage. Use this pin to connect the input power for the driver device. 7 OUTA Output of driver channel A. The driver is able to provide 5 A drive current to the gate of the power MOSFET. 8 ENB Enable input for the driver channel B with logic compatible threshold and hysteresis. This pin is used to enable and disable the driver output. It is internally pulled up to VDD with a 200 kW resistor for active high operation. The output of the pin when the device is disabled will be always low. www.onsemi.com 2 NCP81071 TYPICAL APPLICATION CIRCUIT NCP81071 ENA INA 1 8 2 7 ENB OUTA VDD GND 3 6 4 5 OUTB INB Table 2. ABSOLUTE MAXIMUM RATINGS Value Supply Voltage VDD Output Current (DC) Iout_dc Min Max Unit −0.3 24 V 0.3 A 6.0 Reverse Current (Pulse< 1 ms) A Output Current (Pulse < 0.5 ms) Iout_pulse 6.0 Input Voltage INA, INB −6.0 VDD+0.3 Enable Voltage ENA, ENB −0.3 VDD+0.3 Output Voltage OUTA, OUTB −0.3 VDD+0.3 Output Voltage (Pulse < 0.5 ms) OUTA, OUTB −3.0 VDD+3.0 V Junction Operation Temperature TJ −40 150 °C Storage Temperature Tstg −65 160 Electrostatic Discharge Human body model, HBM 4000 Charge device model, CDM 1000 OUTA OUTB Latch−up Protection A V V V 500 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Table 3. RECOMMENDED OPERATING CONDITIONS Parameter VDD supply Voltage INA, INB input voltage ENA, ENB input voltage Junction Temperature Range Rating Unit 4.5 to 20 V −5.0 to VDD V 0 to VDD V −40 to +140 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Table 4. THERMAL INFORMATION Package qJA (5C/W) qJC (5C/W) SOIC−8 115 50 MSOP−8 EP 39 4.7 WDFN8 3x3 39 4.7 1. YJT: approximate thermal impedance, junction−to−case top. www.onsemi.com 3 YJT (5C/W) (Note 1) 11 NCP81071 Table 5. INPUT/OUTPUT TABLE NCP81071A NCP81071B NCP81071C ENA ENB INA INB OUTA OUTB OUTA OUTB OUTA OUTB H H L L H H L L H L H H L H H L L H H H H H H L L H H L L L H H H H L L H H L H L L Any Any L L L L L L Any Any x (Note 2) x (Note 2) L L L L L L x (Note 2) x (Note 2) L L H H L L H L x (Note 2) x (Note 2) L H H L L H H H x (Note 2) x (Note 2) H L L H H L L L x (Note 2) x (Note 2) H H L L H H L H 2. Floating condition, internal resistive pull up or pull down configures output condition PRODUCT MATRIX NCP81071A NCP81071B www.onsemi.com 4 NCP81071C NCP81071 Table 6. ELECTRICAL CHARACTERISTICS (Typical values: VDD =12 V, 1 mF from VDD to GND, TA = TJ = −40°C to 140°C, typical at TAMB = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Units 3.5 4.0 4.5 V SUPPLY VOLTAGE VDD Under Voltage Lockout (rising) VCCR VDD Under Voltage Lockout (hysteresis) VCCH Operating Current (no switching) IDD VDD Under Voltage Lockout to Output Delay (Note 3) VDD rising 400 INA = 0, INB = 5 V, ENA = ENB = 0 INA = 5 V, INB = 0, ENA = ENB = 0 INA = 0, INB = 5 V, ENA = ENB = 5 V INA = 5 V, INB = 0, ENA = ENB = 5 V 1.4 VDD rising 10 mV 3 mA ms INPUTS High Threshold VthH Input rising from logic low 1.8 2.0 2.2 V Low Threshold VthL Input falling from logic high 0.8 1.0 1.2 V INA, INB Pull−Up Resistance OUTA = OUTB = Inverter Configuration 200 kW INA, INB Pull−Down Resistance OUTA = OUTB = Buffer Configuration 200 kW OUTPUTS Output Resistance High ROH IOUT = −10 mA 0.8 2 W Output Resistance Low ROL IOUT = +10 mA 0.8 2 W Peak Source Current (Note 4) ISource OUTA/OUTB = GND 200 ns Pulse 5 A Miller Plateau Source Current (Note 4) ISource OUTA/OUTB = 5.0 V 200 ns Pulse 4.5 A Peak Sink Current (Note 4) ISink OUTA/OUTB = VDD 200 ns Pulse 5 A Miller Plateau Sink Current (Note 4) ISink OUTA/OUTB = 5.0 V 200 ns Pulse 3.5 A ENABLE High−Level Input Voltage VIN_H Low to High Transition 1.8 2.0 2.2 V Low−Level Input Voltage VIN_L High to Low Transition 0.8 1.0 1.2 V ENA, ENB pull−up resistance 200 kW Propagation Delay Time (EN to OUT) (Notes 3, 5) td3 CLoad = 1.8 nF 16 20 29 ns Propagation Delay Time (EN to OUT) (Notes 3, 5) td4 CLoad = 1.8 nF 16 20 29 ns Propagation Delay Time Low to High, IN Rising (IN to OUT) (Notes 3, 5) td1 CLoad = 1.8 nF 16 20 29 ns Propagation Delay Time High to Low, IN Falling (IN to OUT) (Notes 3, 5) td2 CLoad = 1.8 nF 16 20 29 ns Rise Time (Note 5) tr CLoad = 1.8 nF 8 15 ns Fall Time (Note 5) tf CLoad = 1.8 nF 8 15 ns Delay Matching between 2 Channels (Note 6) tm INA = INB, OUTA and OUTB at 50% Transition Point 1 4 ns SWITCHING CHARACTERISTICS Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Guaranteed by design. 4. Not production tested, guaranteed by design and statistical analysis. 5. See timing diagrams in Figure 2, Figure 3, Figure 4 and Figure 5. 6. Guaranteed by characterization. www.onsemi.com 5 NCP81071 2V 2V Input Input 1V 1V 2V 2V Enable Enable 1V 1V 90% 90% Output Output 10% 10% t d3 t d4 t d3 Figure 2. Enable Function for Non−inverting Input Driver Operation t d4 Figure 3. Enable Function for Inverting Input Driver Operation 2V 2V Input Input 1V 1V 2V 2V Enable Enable 1V 1V 90% 90% Output Output 10% 10% t d1 t r t d2 t f t d1 Figure 4. Non−inverting Input Driver Operation t d2 Figure 5. Inverting Input Driver Operation www.onsemi.com 6 NCP81071 TYPICAL CHARACTERISTICS 100 180 10 nF 80 VDD = 4.5 V 70 60 4.7 nF 50 40 30 2.2 nF 20 1 nF 10 0 200 400 600 800 1000 1200 1400 1600 1800 2000 60 2.2 nF 40 1 nF 470 pF 0 250 500 750 1000 1250 1500 1750 2000 Figure 6. Supply Current vs. Switching Frequency (VDD = 4.5 V) Figure 7. Supply Current vs. Switching Frequency (VDD = 8 V) 270 10 nF 240 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 4.7 nF 80 FREQUENCY (kHz) VDD = 12 V 210 180 150 4.7 nF 120 90 2.2 nF 60 1 nF 30 0 250 500 750 1000 1250 VDD = 15 V 210 180 4.7 nF 10 nF 150 120 90 2.2 nF 60 1 nF 30 470 pF 0 1500 1750 2000 470 pF 0 250 500 750 1000 1250 1500 1750 2000 FREQUENCY (kHz) FREQUENCY (kHz) Figure 8. Supply Current vs. Switching Frequency (VDD = 12 V) Figure 9. Supply Current vs. Switching Frequency (VDD = 15 V) 120 270 240 VDD = 18 V SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 100 FREQUENCY (kHz) 240 210 180 10 nF 150 120 4.7 nF 90 2.2 nF 60 1 nF 30 470 pF 0 120 0 270 0 VDD = 8.0 V 140 20 470 pF 0 10 nF 160 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 90 0 250 500 750 1000 1250 1500 1750 2000 100 CLOAD = 2.2 nF 2 MHz 80 60 1 MHz 100 kHz 50 kHz 40 500 kHz 20 0 200 kHz 4 6 8 10 12 14 16 18 FREQUENCY (kHz) SUPPLY VOLTAGE (V) Figure 10. Supply Current vs. Switching Frequency (VDD = 18 V) Figure 11. Supply Current vs. Supply Voltage (CLOAD = 2.2 nF) www.onsemi.com 7 20 NCP81071 TYPICAL CHARACTERISTICS 160 CLOAD = 4.7 nF 1.8 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 140 2.0 2 MHz 120 100 1 MHz 80 500 kHz 100 kHz 60 50 kHz 40 200 kHz 20 0 4 6 8 10 12 14 16 18 0.6 0.4 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (V) Figure 12. Supply Current vs. Supply Voltage (CLOAD = 4.7 nF) Figure 13. Supply Current vs. Supply Voltage (NCP81071A) 20 2.0 1.8 Input = GND 1.6 1.4 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 0.8 0 20 Input = VDD 1.2 1.0 0.8 0.6 0.4 0.2 Input = GND 1.6 1.4 Input = VDD 1.2 1.0 0.8 0.6 0.4 0.2 4 6 8 10 12 14 16 18 0 20 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 14. Supply Current vs. Supply Voltage (NCP81071B) Figure 15. Supply Current vs. Supply Voltage (NCP81071C) 12 20 12 10 10 VDD = 15 V tf, FALL TIME (ns) tr, RISE TIME (ns) 1.2 1.0 SUPPLY VOLTAGE (V) 1.8 8 VDD = 20 V 6 4 Input = VDD 1.4 0.2 2.0 0 Input = GND 1.6 VDD = 10 V VDD = 5 V 2 VDD = 15 V 8 VDD = 20 V 6 4 VDD = 10 V 2 0 −40 −20 0 20 40 60 80 100 120 0 −40 −20 140 0 VDD = 5 V 20 40 60 80 100 120 140 TEMPERATURE (°C) TEMPERATURE (°C) Figure 16. Rise Time vs. Temperature Figure 17. Fall Time vs. Temperature www.onsemi.com 8 NCP81071 30 30 25 25 20 15 10 nF 4.7 nF 2.2 nF 1.0 nF 470 pF 10 5 0 4 6 8 10 12 14 16 18 20 15 0 20 6 8 10 12 14 16 18 VDD, SUPPLY VOLTAGE (V) Figure 18. Propagation Delay td1 vs. Supply Voltage Figure 19. Propagation Delay td2 vs. Supply Voltage 35 25 30 10 nF 20 4.7 nF 15 10 1.0 nF 2.2 nF 5 6 8 10 12 14 10 nF 25 20 4.7 nF 15 1.0 nF 10 2.2 nF 16 18 0 20 470 pF 4 6 8 10 12 14 16 18 VDD, SUPPLY VOLTAGE (V) VDD, SUPPLY VOLTAGE (V) Figure 20. Fall Time tf vs. Supply Voltage Figure 21. Rise Time tr vs. Supply Voltage VDD 20 5 470 pF 4 4 VDD, SUPPLY VOLTAGE (V) 30 0 10 nF 4.7 nF 2.2 nF 1.0 nF 470 pF 10 5 tr, RISE TIME (ns) tf, FALL TIME (ns) td2, DELAY TIME (ns) td1, DELAY TIME (ns) TYPICAL CHARACTERISTICS 20 VDD Output Output Figure 22. Output Behavior vs. Supply Voltage NCP81071A (Inverting) 10 nF between Output and GND, INA = GND, ENA = VDD Figure 23. Output Behavior vs. Supply Voltage NCP81071A (Inverting) 10 nF between Output and GND, INA = GND, ENA = VDD www.onsemi.com 9 NCP81071 TYPICAL CHARACTERISTICS VDD VDD Output Output Figure 25. Output Behavior vs. Supply Voltage NCP81071A (Inverting) 10 nF between Output and GND, INA = VDD, ENA = VDD Figure 24. Output Behavior vs. Supply Voltage NCP81071A (Inverting) 10 nF between Output and GND, INA = VDD, ENA = VDD VDD VDD Output Output Figure 26. Output Behavior vs. Supply Voltage NCP81071B (Non−Inverting) 10 nF between Output and GND, INA = VDD, ENA = VDD Figure 27. Output Behavior vs. Supply Voltage NCP81071B (Non−Inverting) 10 nF between Output and GND, INA = VDD, ENA = VDD VDD VDD Output Output Figure 29. Output Behavior vs. Supply Voltage NCP81071B (Non−Inverting) 10 nF between Output and GND, INA = GND, ENA = VDD Figure 28. Output Behavior vs. Supply Voltage NCP81071B (Non−Inverting) 10 nF between Output and GND, INA = GND, ENA = VDD www.onsemi.com 10 NCP81071 LAYOUT GUIDELINES Keep low level signal lines away from high level power lines with a lot of switching noise. Place a ground plane for better noise shielding. Beside noise shielding, ground plane is also useful for heat dissipation. NCP81071 DFN and MSOP package have thermal pad for: 1) quiet GND for all the driver circuits; 2) heat sink for the driver. This pad must be connected to a ground plane and no switching currents from the driven MOSFET should pass through the ground plane under the driver. To maximize the heatsinking capability, it is recommended several ground layers are added to connect to the ground plane and thermal pad. A via array within the area of package can conduct the heat from the package to the ground layers and the whole PCB board. The number of vias and the size of ground plane are determined by the power dissipation of NCP81071 (VDD voltage, switching frequency and load condition), the air flow condition and its maximum junction temperature. The switching performance of NCP81071 highly depends on the design of PCB board. The following layout design guidelines are recommended when designing boards using these high speed drivers. Place the driver as close as possible to the driven MOSFET. Place the bypass capacitor between VDD and GND as close as possible to the driver to improve the noise filtering. It is preferred to use low inductance components such as chip capacitor and chip resistor. If vias are used, connect several paralleled vias to reduce the inductance of the vias. Minimize the turn-on/sourcing current and turn-off/sinking current paths in order to minimize stray inductance. Otherwise high di/dt established in these loops with stray inductance can induce significant voltage spikes on the output of the driver and MOSFET Gate terminal. Keep power loops as short as possible by paralleling the source and return traces (flux cancellation). ORDERING INFORMATION Part Number Output Configuration NCP81071ADR2G dual inverting NCP81071BDR2G dual non inverting NCP81071CDR2G One inverting one non inverting NCP81071AZR2G dual inverting NCP81071BZR2G dual non inverting NCP81071CZR2G One inverting one non inverting NCP81071AMNTXG dual inverting NCP81071BMNTXG dual non inverting NCP81071CMNTXG One inverting one non inverting Temperature Range (5C) −40 to +140 Package Type Shipping† SOIC−8 (Pb−Free) 2500 / Tape & Reel MSOP8 EP (Pb−Free) 3000 / Tape & Reel WDFN8 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WDFN8 3x3, 0.65P CASE 511CD ISSUE O 1 SCALE 2:1 B A D DATE 29 APR 2014 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L L1 ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ PIN ONE REFERENCE 2X DETAIL A E ALTERNATE CONSTRUCTIONS 0.10 C 2X 0.10 C ÇÇÇ ÉÉÉ EXPOSED Cu TOP VIEW A DETAIL B 0.05 C DIM A A1 A3 b D D2 E E2 e K L L1 ÉÉÉ ÇÇÇ ÇÇÇ A3 MOLD CMPD A1 DETAIL B ALTERNATE CONSTRUCTIONS 0.05 C A3 NOTE 4 SIDE VIEW DETAIL A 1 A1 D2 C 8X 4 SEATING PLANE GENERIC MARKING DIAGRAM* L XXXXX XXXXX ALYWG G E2 K 5 8 e/2 e 8X A L Y W G b 0.10 C A B BOTTOM VIEW 0.05 C = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) NOTE 3 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. RECOMMENDED SOLDERING FOOTPRINT* 8X 2.31 PACKAGE OUTLINE MILLIMETERS MIN MAX 0.70 0.80 0.00 0.05 0.20 REF 0.25 0.35 3.00 BSC 2.05 2.25 3.00 BSC 1.10 1.30 0.65 BSC 0.20 −−− 0.30 0.50 0.00 0.15 0.63 3.30 1.36 1 0.65 PITCH 8X 0.40 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON84944F WDFN8, 3X3, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS MSOP8 EP, 3x3 CASE 846AM ISSUE B DATE 07 JAN 2022 GENERIC MARKING DIAGRAM* 8 XXXX AYWG G 1 XXXX A Y W G = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON82708F MSOP8 EP, 3X3 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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