Dual MOSFET Gate Driver,
High Performance
NCP81075
Introduction
The NCP81075 is a high performance dual MOSFET gate driver
optimized to drive the gates of both high and low side power
MOSFETs in a synchronous buck converter. The NCP81075 uses an
on−chip bootstrap diode to eliminate the external discrete diode. A
high floating top driver design can accommodate HB voltage as high
as 180 V. The low−side and high−side are independently controlled
and match to 4 ns between the turn−on and turn−off of each other.
Independent Under−Voltage lockout is provided for the high side and
low side driver forcing the output low when the drive voltage is below
a specific threshold.
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1
Configuration
Floating Top Driver Accommodates Boost Voltage up to 180 V
Switching Frequency up to 1 MHz
20 ns Propagation Delay Times
4 A Sink, 4 A Source Output Currents
8 ns Rise / 7 ns Fall Times with 1000 pF Load
UVLO Protection
Specified from −40°C to 140°C
Offered in SOIC−8 (D), DFN8 (MN), WDFN10 (MT)
Packages
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
•
•
•
•
DFN8
CASE 506CY
8
WDFN10
CASE 511CE
NCP
81075
ALYWG
G
NCP81075
ALYWG
G
1
NCP81075 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PINOUT DIAGRAMS
VDD 1
8 LO
VDD 1
Telecom and Datacom
Isolated Non−Isolated Power Supply Architectures
Class D Audio Amplifiers
Two Switch and Active Clamp Forward Converters
HB 2
7 VSS
HO 3
6 LI
HS 4
5 HI
10 LO
HB 2
9 VSS
HO 3
8 LI
HS 4
NC 5
7 HI
6 NC
WDFN10
SOIC/DFN8
Simplified Application Diagram
NCP81075
(top views)
VDD
VDD
HB
ORDERING INFORMATION
VIN
HO
HI
PWM
CONTROLLER
1
MARKING DIAGRAMS
• Drives Two N-Channel MOSFETs in High-Side and Low-Side
•
1
SOIC−8 NB
CASE 751−07
Features
•
•
•
•
•
•
•
•
ÇÇÇ
ÇÇÇ
8
NCP81075
VOUT
HS
LI
Package
Shipping†
NCP81075DR2G
SOIC8
(Pb−Free)
2500 /
Tape & Reel
NCP81075MNTXG
DFN8
(Pb−Free)
4000 /
Tape & Reel
NCP81075MTTXG
WDFN10
(Pb−Free)
4000 /
Tape & Reel
Device
LO
VSS
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
March, 2021 − Rev. 3
1
Publication Order Number:
NCP81075/D
NCP81075
Table 1. PIN DESCRIPTION
Pin No.
SOIC/DFN8
Pin No.
WDFN10
Symbol
Description
1
1
VDD
2
2
HB
High Side Bootstrap Supply
3
3
HO
High Side Output
4
4
HS
High−Side Source
5
7
HI
High−Side Input
6
8
LI
Low−Side Input
7
9
VSS
8
10
LO
Low−Side Output
−
5,6
NC
No Connect
Positive Supply to the Lower Gate Driver
Negative Supply Return
Table 2. MAXIMUM RATINGS
Parameter
Value
Units
VDD
−0.3 to 24
V
VHB
−0.3 to 200
V
DC
VHS – 0.3 to VHB + 0.3
V
Repetitive Pulse < 100 ns
VHS − 2 to VHB + 0.3, (VHB − VHS < 24)
VHS
DC
−20 to 200 − VDD
V
VLO
DC
−0.3 to VDD + 0.3
V
Repetitive pulse < 100 ns
−2 to VDD + 0.3
VHO
VHI, VLI
−10 to 24
V
VHB − HS
−0.3 to 24
V
Operating Junction Temperature Range, TJ
−40 to 170
°C
Storage Temperature, TSTG
−65 to 150
°C
Lead Temperature (Soldering, 10 sec)
+300
°C
HBM
1000
V
CDM
2000
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. VHB – VHS should be in the range of −0.3 V to +20 V.
Table 3. RECOMMENDED OPERATING CONDITIONS
Parameter
Min
Nom
Max
Units
12
20
V
VDD
Supply Voltage Range
8.5
VHS
Voltage on HS (DC)
−10
180 − VDD
VHB
Voltage on HB
VHS + 8,
VDD − 1
VHS + 20,
180
50
V / ns
−40
+140
°C
VHO
VHS − 0.3
VHB + 0.3
V
VLO
−0.3
VDD + 0.3
V
Voltage Slew Rate on HS
TJ
Operating Junction Temperature Range
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
NCP81075
ABSOLUTE MAXIMUM RATINGS
Table 4. ELECTRICAL/THERMAL INFORMATION (All signals referenced to GND unless noted otherwise, Note 2)
SOIC
DFN8
DFN10
Unit
qJA Junction to Ambient thermal resistance
116
36
35
°C/W
qJC(top) Junction to case (Top) thermal resistance
98
42
32
qJB Junction to Board thermal resistance
52
19.1
12
qJC(Bottom) Junction to case (Bottom) thermal resistance
40
4
1.3
yJT Junction to top characterization parameter
14
0.6
0.2
yJB Junction to board characterization parameter
39
19.3
12.2
Thermal Characteristic
Moisture Sensitivity Level (MSL)
QFN Package
1
2. This data was taken using the JEDEC proposed High−K Test PCB.
Table 5. ELECTRICAL CHARACTERISTICS
Unless otherwise stated: TA = TJ = −40°C to 140°C; VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO
Parameter
Test Condition
Min
Typ
Max
Units
mA
SUPPLY CURRENTS
IDD
VDD quiescent current
VLI = VHI = 0
0.85
1.8
IDDO
VDD operating current
f = 500 kHz, CLOAD = 0
7.3
15
f = 300 kHz, CLOAD = 0
4.9
11
IHB
Boot voltage quiescent current
VLI = VHI = 0 V
0.92
1.8
IHBO
Boot voltage operating current
f = 500 kHz, CLOAD = 0
6.55
12
f = 300 kHz, CLOAD = 0
4.5
7.0
25
IHBS
HB to VSS quiescent current
VHS = VHB = 110 V
5.0
IHBSO
HB to VSS operating current
f = 500 kHz, CLOAD = 0
0.1
mA
mA
INPUT
VHIH, VLIH
Input rising threshold
VHIL, VLIL
Input falling threshold
RIN
V
2.7
0.8
Input Pulldown Resistance
100
170
350
kW
6.2
7.1
8.0
V
UNDERVOLTAGE PROTECTION (UVLO)
VDD rising threshold
VDD threshold hysteresis
0.58
VHB rising threshold
5.5
VHB threshold hysteresis
6.5
7.5
0.5
BOOTSTRAP DIODE
V
VF
Low−current forward voltage
I VDD − HB = 100 mA
0.59
0.95
VFI
High−current forward voltage
I VDD − HB = 100 mA
0.85
1.1
RD
Dynamic resistance, DVF/DI
I VDD − HB = 100 mA and 80 mA
0.94
2.0
W
V
LO GATE DRIVER
VLOL
Low level output voltage
ILO = 100 mA
0.1
0.40
VLOH
High level output voltage
ILO = −100 mA, VLOH = VDD − VLO
0.15
0.40
Peak pull−up current
VLO = 0 V
4
Peak pull−down current
VLO = 12 V
4
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3
A
NCP81075
Table 5. ELECTRICAL CHARACTERISTICS
Unless otherwise stated: TA = TJ = −40°C to 140°C; VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO
Parameter
Test Condition
Min
Typ
Max
Units
V
HO GATE DRIVER
VHOL
Low level output voltage
IHO = 100 mA
0.1
0.40
VHOH
High level output voltage
IHO = −100 mA, VHOH = VHB – VHO
0.15
0.40
Peak pull−up current
VLO = 0 V
4
Peak pull−down current
VLO = 12 V
4
CLOAD = 0 (−40 to 125°C)
20
45
CLOAD = 0 (−40 to 140°C)
20
50
CLOAD = 0 (−40 to 125°C)
20
45
CLOAD = 0 (−40 to 140°C)
20
50
CLOAD = 0 (−40 to 125°C)
20
45
CLOAD = 0 (−40 to 140°C)
20
50
CLOAD = 0 (−40 to 125°C)
20
45
CLOAD = 0 (−40 to 140°C)
20
50
A
PROPAGATION DELAYS
tDLFF
VLI falling to VLO falling
tDHFF
VHI falling to VHO falling
tDLRR
tDHRR
VLI rising to VLO rising
VHI rising to VHO rising
ns
DELAY MATCHING
tMON
LI ON, HI OFF
3.5
14
tMOFF
LI OFF, HI ON
3.5
14
ns
OUTPUT RISE AND FALL TIME
ns
tR
LO, HO
CLOAD = 1000 pF
8
tF
LO, HO
CLOAD = 1000 pF
7
tR
LO, HO (3 V to 9 V)
CLOAD = 0.1 mF
0.2
0.55
tF
LO, HO (3 V to 9 V)
CLOAD = 0.1 mF
0.25
0.45
ms
MISCELLANEOUS
t1
Minimum input pulse width that
changes the output
t2
Bootstrap diode turn−off time
30
IF = 100 mA, IREV = −100 mA
(Notes 3 and 4)
ns
50
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Typical values for TA = 25°C
4. IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode.
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4
NCP81075
Internal Block Diagram
Figure 1. Internal Block Diagram
Timing Diagrams
VDD / VHB-VHS
UVLO
Thresholds
LI
Delay ~ 40us
LO
HI
Delay ~ 40us
HO
Note: If HI is set and the High−Side driver (VHB−VHS) crosses its UVLO threshold
100ns after the VDD UVLO then a rising edge on HI is required to pull HO High.
Figure 2. UVLO
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5
NCP81075
LI
HI
LO
TMOFF
TON
HO
Figure 3. TMON and TMOFF
90%
10%
HI, LI
TDLRR
TDHRR
90%
TDLFF
TDHFF
10%
HO, LO
Figure 4. Propagation Delays
LOGIC TABLE
HI
LI
HO
LO
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
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6
NCP81075
PINOUT DIAGRAMS
DFN8
VDD
1
8
LO
HB
2
7
VSS
GND
Pad
HO
3
6
LI
HS
4
5
HI
10
LO
9
VSS
8
LI
WDFN10
VDD
1
HB
2
GND
Pad
HO
3
HS
4
7
HI
NC
5
6
NC
SOIC 8
VDD
1
8
LO
HB
2
7
VSS
HO
3
6
LI
HS
4
5
HI
Note: The VSS Pin and the GND Pad are internally connected.
Figure 5. NCP81075 Top View
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7
NCP81075
TYPICAL CHARACTERISTICS
4.0
DELAY MATCHING (ns)
3
2
QUIESCENT CURRENT (mA)
4
TmOFF
1
0
−1
−2
−3
TmON
−4
−5
−50
−25
0
25
50
75
100
125
2.5
2.0
HI ; LI = High
I(HB)
1.5
Input Current
1.0
0.5
8
10
12
14
16
18
20
22
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 6. Delay Matching vs. Temperature
Figure 7. Quiescent Current vs. Supply
Voltage High
24
3.0
1.4
Rising
2.5
1.2
2.0
1.0
0.8
HI ; LI = GND
I(HB)
0.6
HI, LI (V)
QUIESCENT CURRENT (mA)
3.0
0
150
1.6
Falling
1.5
1.0
I(VDD)
0.4
0.5
0.2
0
8
10
12
14
16
18
20
0
24
22
−25
0
25
50
75
100
125
150
TEMPERATURE (°C)
Figure 8. Quiescent Current vs. Supply
Voltage Low
Figure 9. Input Threshold vs. Temperature
4.0
1.98
3.5
OUTPUT CURRENT (A)
Rising
1.97
1.96
1.95
1.94
Falling
1.93
1.92
T = 25°C
1.91
1.90
1.89
−50
SUPPLY VOLTAGE (V)
1.99
INPUT THRESHOLD (V)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
8
10
12
14
16
18
20
22
0
24
Sink Current
0
2
Source Current
4
6
8
10
12
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 10. Input Threshold vs. Supply Voltage
Figure 11. Output Current vs. Output Voltage
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8
NCP81075
TYPICAL CHARACTERISTICS
25
PROPAGATION DELAY (ns)
Falling
22.0
21.5
21.0
Rising
20.5
20.0
19.5
8
10
12
14
16
18
22
Rising Edge
10
5
−50
−25
0
25
50
75
100
125
150
TEMPERATURE (°C)
Figure 12. Propagation Delay vs. Supply
Voltage
Figure 13. Propagation Delay vs. Temperature
1000
I(VDD)
9
100
8
I(HB)
7
6
5
4
3
2
1
0
15
0
24
Falling Edge
20
SUPPLY VOLTAGE (V)
10
OPERATING CURRENT (mA)
20
DIODE CURRENT (A)
PROPAGATION DELAY (ns)
22.5
10
1
0.1
0.01
10 110 210 310 410 510 610 710 810 910 1010
0.001
0.50
0.60
0.70
0.80
0.90
FREQUENCY (kHz)
DIODE VOLTAGE (V)
Figure 14. Operating Current vs. Frequency
Figure 15. Diode Current vs. Diode Voltage
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9
NCP81075
APPLICATION INFORMATION
taken by the system designer to pre−charge the bootstrap
capacitor (CBST) to ensure sufficient voltage levels for
proper operation. If the capacitor is discharged, the
high−side power MOSFET relies on the driver’s internal
20 kW pull down resistor to prevent charge from building up
across its VGS during the initial low side FET turn on events.
High dV/dt on HS, when turning on the low−side MOSFET,
creates a capacitive divider across the high side FET gate,
possibly resulting in cross−conduction. With proper biasing
across CBST (VHB−VHS), the internal low−impedance pull
down at HO ensures the high−side FET remains off.
The external BST resistor, which connects HB pin and
BST cap, should avoid excessive resistance. NCP81075
has high−side UVLO protection based on the voltage across
HB and HS pins. High resistance on HB pin may falsely
trigger UVLO protection at the moment when high−side
MOSFET is turning on.
The NCP81075 is a high performance dual MOSFET gate
driver optimized for driving the gates of both high side and
low side power MOSFETs in a synchronous buck converter
topology. A high and a Low input signals are all that is
required to properly drive the high side and low side
MOSFETs.
Low−Side Driver
The low side driver is designed to drive low RDSON
N−channel MOSFETs. The typical output resistances for the
driver are 1.5 ohms for sourcing and 1 ohm for sinking gate
current. Due to the parasitic inductances of the packages,
drive circuits and the nonlinearity of the MOSFETs output
resistances the recorded peak current is close to 4 A.
The low output resistances allow the driver to have 8 ns
rise and 7 ns fall times into a 1 nF load. When the driver is
enabled, the driver’s output is in phase with LI. When the
NCP81075 is disabled, the low side gate is held low.
UVLO (Under Voltage Lockout)
High−Side Driver
The bias supplies of the high−side and low−side drivers
have UVLO protection. The VDD UVLO disables both
drivers when the VDD voltage crosses the specified
threshold. The typical rising threshold is 7.1 V with 0.58 V
hysteresis. The VHB UVLO disables only the high−side
driver when the VHB to VHS is below the specified
threshold. The typical VHB UVLO rising threshold is 6.5 V
with 0.5 V hysteresis. The designer must take into account
a 40 ms delay before the output channels can react to a logic
input. (Refer to the UVLO Timing Diagram).
The high side driver is designed to drive a floating low
RDSON N−channel MOSFET. The output resistances for the
driver are 1.5 ohms for sourcing and 1 ohm for sinking gate
current. The bias voltage for the high side driver is realized
by an external bootstrap supply circuit which is connected
between the HB and HS Pins.
The bootstrap circuit is comprised of only the bootstrap
capacitor since the bootstrap diode is internal. When the
NCP81075 is starting up, the HS Pin is at ground, the
bootstrap capacitor will charge up to VDD through the
internal diode. When the HI goes high, the high side driver
will begin to turn the high side MOSFET On by pulling
charge out of the bootstrap capacitor. As the external
MOSFET turns ON, the HS Pin will rise up to VIN, forcing
the HB Pin to VIN + VBstCap which is enough gate to source
voltage to hold the switch On. To complete the cycle, the
MOSFET is switched OFF by pulling the gate down to the
voltage at the HS Pin. When the low side MOSFET turns On,
the HS Pin is pulled to ground. This allows the bootstrap
capacitor to charge up to VDD again. The high−side driver’s
output is in phase with the HI input. When the driver is
disabled, the high side gate is held low.
Unlike a Buck regulator at power−up, Boost regulators
typically require starting when the HS pin is at the VIN level,
instead of GND or the prevailing VOUT. Care should be
Input Stages
The input stage of the NCP81075 is TTL compatible. The
logic rising threshold level is 2.4 V and the logic falling
threshold is 1.6 V.
Layout Guidelines
Gate drivers experience high di/dt during the switching
transitions. So, the inductance at the gate drive traces must
be minimized to avoid excessive ringing on the switch node.
Gate drive traces should be kept as short and wide (> 20 mil)
as practical. The input capacitor must be placed as close as
possible to the IC. Connect the VSS pin of the NCP81075 as
close as possible to the source of the lower MOSFET. The
use of vias is highly desirable to maximize thermal
conduction away from driver.
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ÇÇ
ÇÇÇÇ
Ç
Ç
DFN8, 4x4, 0.8P
CASE 506CY
ISSUE O
1
SCALE 2:1
PIN ONE
REFERENCE
2X
0.15 C
2X
0.15 C
ÉÉ
ÉÉ
ÉÉ
L1
OPTIONAL
CONSTRUCTIONS
TOP VIEW
(A3)
NOTE 4
SIDE VIEW
ÇÇÇ
ÉÉÉ
EXPOSED Cu
A
C
8X
8
L
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.25
0.35
4.00 BSC
3.28
3.48
4.00 BSC
2.35
2.55
0.80 BSC
0.375 REF
0.30
0.50
−−−
0.15
XXXXXX
XXXXXX
ALYWG
G
4
E2
ÇÇÇÇ
K
ALTERNATE
CONSTRUCTION
SEATING
PLANE
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
GENERIC
MARKING DIAGRAM*
ÇÇÇÇ
1
MOLD CMPD
DETAIL B
A1
D2
DETAIL A
DETAIL A
E
ÇÇÇÇ
0.08 C
L
L
DETAIL B
0.10 C
8X
A
B
D
DATE 31 JUL 2014
5
8X
e
e/2
b
0.10
M
C A B
0.05
M
C
XXXX = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
NOTE 3
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
8X
3.58
0.63
4.30 2.65
PACKAGE
OUTLINE
8X
0.80
PITCH
0.40
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON89300F
DFN8, 4X4, 0.8P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN10 4x4, 0.8P
CASE 511CE
ISSUE O
1
DATE 17 SEP 2014
SCALE 2:1
B
A
D
L
L
PIN ONE
REFERENCE
2X
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
L1
E
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.25 AND 0.30 MM FROM THE
TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS
WELL AS THE TERMINALS.
5. DETAILS A AND B SHOW OPTIONAL VIEWS FOR END
OF TERMINAL LEAD AT EDGE OF PACKAGE.
6. FOR DEVICE OPN CONTAINING W OPTION, DETAIL B
ALTERNATE CONSTRUCTION IS NOT APPLICABLE.
0.10 C
0.10 C
2X
TOP VIEW
DETAIL B
0.10 C
ÉÉ
ÇÇ
ÇÇ
EXPOSED Cu
A
10X
A1
DETAIL B
0.08 C
NOTE 4
SIDE VIEW
DETAIL A
1
A3
A1
C
D2
10X
SEATING
PLANE
L
ALTERNATE
CONSTRUCTIONS
10
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.25
0.35
4.00 BSC
2.90
3.10
4.00 BSC
2.50
2.70
0.80 BSC
0.30 REF
0.30
0.50
0.00
0.15
GENERIC
MARKING DIAGRAM*
5
XXXXXX
XXXXXX
ALYWG
G
E2
K
A3
ÇÇÇ
ÉÉÉ
MOLD CMPD
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
6
10X
e
b
0.10 C A B
0.05 C
BOTTOM VIEW
RECOMMENDED
MOUNTING FOOTPRINT
NOTE 3
XXXXX
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer
to device data sheet for actual part
marking. Pb−Free indicator, “G”, may
or not be present.
10X
3.20
0.60
2.76 4.30
PACKAGE
OUTLINE
1
0.80
PITCH
DOCUMENT NUMBER:
DESCRIPTION:
10X
0.42
DIMENSIONS: MILLIMETERS
98AON90341F
WDFN10 4X4, 0.8P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
8
1
SCALE 1:1
−X−
DATE 16 FEB 2011
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
8
8
1
1
IC
4.0
0.155
XXXXX
A
L
Y
W
G
IC
(Pb−Free)
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXXXX
AYWW
1
1
Discrete
XXXXXX
AYWW
G
Discrete
(Pb−Free)
XXXXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
1.270
0.050
SCALE 6:1
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
8
8
XXXXX
ALYWX
G
XXXXX
ALYWX
1.52
0.060
0.6
0.024
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
7.0
0.275
DIM
A
B
C
D
G
H
J
K
M
N
S
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1:
PIN 1. EMITTER
2. COLLECTOR
3. COLLECTOR
4. EMITTER
5. EMITTER
6. BASE
7. BASE
8. EMITTER
STYLE 2:
PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. BASE, #2
6. EMITTER, #2
7. BASE, #1
8. EMITTER, #1
STYLE 3:
PIN 1. DRAIN, DIE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. GATE, #2
6. SOURCE, #2
7. GATE, #1
8. SOURCE, #1
STYLE 4:
PIN 1. ANODE
2. ANODE
3. ANODE
4. ANODE
5. ANODE
6. ANODE
7. ANODE
8. COMMON CATHODE
STYLE 5:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. DRAIN
5. GATE
6. GATE
7. SOURCE
8. SOURCE
STYLE 6:
PIN 1. SOURCE
2. DRAIN
3. DRAIN
4. SOURCE
5. SOURCE
6. GATE
7. GATE
8. SOURCE
STYLE 7:
PIN 1. INPUT
2. EXTERNAL BYPASS
3. THIRD STAGE SOURCE
4. GROUND
5. DRAIN
6. GATE 3
7. SECOND STAGE Vd
8. FIRST STAGE Vd
STYLE 8:
PIN 1. COLLECTOR, DIE #1
2. BASE, #1
3. BASE, #2
4. COLLECTOR, #2
5. COLLECTOR, #2
6. EMITTER, #2
7. EMITTER, #1
8. COLLECTOR, #1
STYLE 9:
PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #1
3. COLLECTOR, DIE #2
4. EMITTER, COMMON
5. EMITTER, COMMON
6. BASE, DIE #2
7. BASE, DIE #1
8. EMITTER, COMMON
STYLE 10:
PIN 1. GROUND
2. BIAS 1
3. OUTPUT
4. GROUND
5. GROUND
6. BIAS 2
7. INPUT
8. GROUND
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 12:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 13:
PIN 1. N.C.
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 14:
PIN 1. N−SOURCE
2. N−GATE
3. P−SOURCE
4. P−GATE
5. P−DRAIN
6. P−DRAIN
7. N−DRAIN
8. N−DRAIN
STYLE 15:
PIN 1. ANODE 1
2. ANODE 1
3. ANODE 1
4. ANODE 1
5. CATHODE, COMMON
6. CATHODE, COMMON
7. CATHODE, COMMON
8. CATHODE, COMMON
STYLE 16:
PIN 1. EMITTER, DIE #1
2. BASE, DIE #1
3. EMITTER, DIE #2
4. BASE, DIE #2
5. COLLECTOR, DIE #2
6. COLLECTOR, DIE #2
7. COLLECTOR, DIE #1
8. COLLECTOR, DIE #1
STYLE 17:
PIN 1. VCC
2. V2OUT
3. V1OUT
4. TXE
5. RXE
6. VEE
7. GND
8. ACC
STYLE 18:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 19:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. MIRROR 2
7. DRAIN 1
8. MIRROR 1
STYLE 20:
PIN 1. SOURCE (N)
2. GATE (N)
3. SOURCE (P)
4. GATE (P)
5. DRAIN
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 21:
PIN 1. CATHODE 1
2. CATHODE 2
3. CATHODE 3
4. CATHODE 4
5. CATHODE 5
6. COMMON ANODE
7. COMMON ANODE
8. CATHODE 6
STYLE 22:
PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC
3. COMMON CATHODE/VCC
4. I/O LINE 3
5. COMMON ANODE/GND
6. I/O LINE 4
7. I/O LINE 5
8. COMMON ANODE/GND
STYLE 23:
PIN 1. LINE 1 IN
2. COMMON ANODE/GND
3. COMMON ANODE/GND
4. LINE 2 IN
5. LINE 2 OUT
6. COMMON ANODE/GND
7. COMMON ANODE/GND
8. LINE 1 OUT
STYLE 24:
PIN 1. BASE
2. EMITTER
3. COLLECTOR/ANODE
4. COLLECTOR/ANODE
5. CATHODE
6. CATHODE
7. COLLECTOR/ANODE
8. COLLECTOR/ANODE
STYLE 25:
PIN 1. VIN
2. N/C
3. REXT
4. GND
5. IOUT
6. IOUT
7. IOUT
8. IOUT
STYLE 26:
PIN 1. GND
2. dv/dt
3. ENABLE
4. ILIMIT
5. SOURCE
6. SOURCE
7. SOURCE
8. VCC
STYLE 29:
PIN 1. BASE, DIE #1
2. EMITTER, #1
3. BASE, #2
4. EMITTER, #2
5. COLLECTOR, #2
6. COLLECTOR, #2
7. COLLECTOR, #1
8. COLLECTOR, #1
STYLE 30:
PIN 1. DRAIN 1
2. DRAIN 1
3. GATE 2
4. SOURCE 2
5. SOURCE 1/DRAIN 2
6. SOURCE 1/DRAIN 2
7. SOURCE 1/DRAIN 2
8. GATE 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42564B
SOIC−8 NB
STYLE 27:
PIN 1. ILIMIT
2. OVLO
3. UVLO
4. INPUT+
5. SOURCE
6. SOURCE
7. SOURCE
8. DRAIN
STYLE 28:
PIN 1. SW_TO_GND
2. DASIC_OFF
3. DASIC_SW_DET
4. GND
5. V_MON
6. VBULK
7. VBULK
8. VIN
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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