NCP81119
Multiple-Phase Controller
with SVID Interface for
Desktop and Notebook CPU
Applications
The NCP81119 Multi−Phase buck solution is optimized for
Intel® VR12.5 compatible CPUs with user configurations of 4/3/2/1
phases. The controller combines true differential voltage sensing,
differential inductor DCR current sensing, input voltage
feed−forward, and adaptive voltage positioning to provide accurately
regulated power for both Desktop and Notebook applications. The
control system is based on Dual−Edge pulse−width modulation
(PWM) combined with DCR current sensing providing the fastest
initial response to dynamic load events at reduced system cost. It has
the capability to shed to single phase during light load operation and
can auto frequency scale in light load conditions while maintaining
excellent transient performance.
High performance operational error amplifiers are provided to
simplify compensation of the system. Patented Dynamic Reference
Injection further simplifies loop compensation by eliminating the need
to compromise between closed−loop transient response and Dynamic
VID performance. Patented Total Current Summing provides highly
accurate digital current monitoring.
Features
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MARKING
DIAGRAM
NCP
81119
ALYWG
G
1
QFN32
CASE 510AT
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 26 of this data sheet.
• Meets Intel VR12.5 Specifications
• Current Mode Dual Edge Modulation for Fastest Initial Response to
•
•
•
•
•
•
•
•
•
•
•
•
Transient Loading
High Performance Operational Error Amplifier
Digital Soft Start Ramp
Dynamic Reference Injection
Accurate Total Summing Current Amplifier
Dual High Impedance Differential Voltage and Total
Current Sense Amplifiers
Phase−to−Phase Dynamic Current Balancing
“Lossless” DCR Current Sensing for Current Balancing
True Differential Current Balancing Sense Amplifiers
for Each Phase
Adaptive Voltage Positioning (AVP)
Switching Frequency Range of 280 kHz – 600 kHz
Startup into Pre−Charged Loads While Avoiding False
OVP
Power Saving Phase Shedding
© Semiconductor Components Industries, LLC, 2013
August, 2013 − Rev. 1
• Vin Feed Forward Ramp Slope
• Pin Programming for Internal SVID parameters
• Over Voltage Protection (OVP) & Under Voltage
Protection (UVP)
• Over Current Protection (OCP)
• VR−RDY Output with Internal Delays
• These are Pb−Free Devices
Applications
• Desktop and Notebook Processors
1
Publication Order Number:
NCP81119/D
VSN
VSP
+
DAC
DIFFAMP
GND
Error
Amp
CSCOMP
CS
Amp
Current
Measurement
& Limit
−
CSREF
CSSUM
IOUT
ILIM
COMP
FB
DIFFOUT
NCP81119
CSREF
VSP
TSENSE
Thermal
Monitor
VSN
OVP
OVP
VRHOT
SDIO
ALERT
SVID Interface
Data
Registers
ADC
MUX
SCLK
VSP−VSN
TSENSE
VBOOT
IOUT
IMAX
ADDR
CSN4
DAC
DAC
CSP4
CSN2
CSP2
Enable
VR Ready
Comparator
VSP
VSN
DAC
IPH3
CSN3
Current
Balance
IPH2
CSP3
IPH1
CSN1
RAMP1
RAMP2
RAMP3
RAMP4
CSP1
PWM
Generators
OVP
COMP
Enable
Enable
GND
Ramp
Generators
UVLO & EN
VCC
ENABLE
Power State
Stage
DRON
PWM1/ADD
PWM2/IMAX
PWM4/ROSC
NCP81102
PWM3/VBOOT
Enable
VRMP
VRDY
IPH4
Figure 1. Block Diagram for NCP81119
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2
VSP
VSN
DIFFOUT
FB
COMP
VRMP
IOUT
ILIM
NCP81119
32
31
30
29
28
27
26
25
ENABLE
1
24 CSCOMP
VCC
2
23 CSSUM
VR_HOT#
3
22 CSREF
NCP81119
19 CSN2
VR_RDY
7
18 CSP2
TSENSE
8
17 CSN3
9
10
11
12
13
14
15
16
CSP3
6
CSN1
SCLK
CSP1
20 CSP4
DRON
5
PWM1/ADD
ALERT#
PWM3/IMAX
21 CSN4
PWM2/VBOOT
4
PWM4/ROSC
SDIO
Figure 2. NCP81119 Pin Configurations
NCP81119 PIN DESCRIPTIONS
Pin No.
Symbol
1
ENABLE
Description
Logic input. Logic high enables the output and logic low disables the output.
2
VCC
3
VR_HOT#
Power for the internal control circuits. A decoupling capacitor is connected from this pin to ground
4
SDIO
5
ALERT#
6
SCLK
7
VR_RDY
Open drain output. High indicates that the output is regulating
8
TSENSE
Temp Sense input for the multiphase converter
9
PWM4/ROSC
10
PWM2/VBOOT
Phase 2 PWM output. Also as VBOOT input pin to adjust the boot−up voltage. During start up it is
used to program VBOOT with a resistor to ground
11
PWM3/IMAX
Phase 3 PWM output. Also as ICC_MAX Input Pin. During start up it is used to program ICC_MAX
with a resistor to ground
12
PWM1/ADD
Phase 1 PWM output. Also as Address program pin. A resistor to ground on this pin programs the
SVID address of the device
13
DRON
Bidirectional gate drive enable output
14
CSP1
Non−inverting input to current balance sense amplifier for phase 1
15
CSN1
Inverting input to current balance sense amplifier for phase 1
16
CSP3
Non−inverting input to current balance sense amplifier for phase 3
Thermal logic output for over temperature
Serial VID data interface
Serial VID ALERT#.
Serial VID clock
Phase 4 PWM output. A resistance from this pin to ground programs the oscillator frequency
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NCP81119
NCP81119 PIN DESCRIPTIONS
Pin No.
Symbol
Description
17
CSN3
Inverting input to current balance sense amplifier for phase 3. Pull this Pin to VCC, configure as
1−phase operation
18
CSP2
Non−inverting input to current balance sense amplifier for phase 2
19
CSN2
Inverting input to current balance sense amplifier for phase 2. Pull this Pin to VCC, configure as
2−phase operation
20
CSP4
Non−inverting input to current balance sense amplifier for phase 4
21
CSN4
Inverting input to current balance sense amplifier. Pull this Pin to VCC, configure as 3−phase operation
22
CSREF
Total output current sense amplifier reference voltage input, a capacitor on this pin is used to ensure CSREF voltage signal integrity
23
CSSUM
Inverting input of total current sense amplifier
24
CSCOMP
Output of total current sense amplifier
25
ILIM
Over current shutdown threshold setting. Resistor to CSCOMP to set threshold
26
IOUT
Total output current monitor.
27
VRMP
Feed−forward input of Vin for the ramp slope compensation. The current fed into this pin is used
to control the ramp of PWM slope
28
COMP
Output of the error amplifier and the inverting inputs of the PWM comparators
29
FB
30
DIFFOUT
31
VSN
Inverting input to differential remote sense amplifier
32
VSP
Non−inverting input to the differential remote sense amplifier
33
FLAG / GND
Error amplifier voltage feedback
Output of the differential remote sense amplifier
Power supply return (QFN Flag)
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NCP81119
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL INFORMATION
Pin Symbol
VMAX
VMIN
COMP
VCC + 0.3 V
−0.3 V
CSCOMP
VCC + 0.3 V
−0.3 V
VSN
GND + 300 mV
GND – 300 mV
DIFFOUT
VCC + 0.3 V
−0.3 V
VR_RDY
VCC + 0.3 V
−0.3 V
VCC
6.5 V
−0.3 V
IOUT
2.0 V
−0.3 V
VRMP
+25 V
−0.3 V
All Other Pins
VCC + 0.3 V
−0.3 V
*All signals referenced to GND unless noted otherwise.
THERMAL INFORMATION
Description
Thermal Characteristic
QFN Package (Note 1)
Operating Junction Temperature Range (Note 2)
Symbol
Typ
Unit
RqJA
68
_C/W
TJ
−10 to 125
_C
−10 to 100
_C
TSTG
−40 to +150
_C
Pd
110 to 131
mW
MSL
1
Operating Ambient Temperature Range
Maximum Storage Temperature Range
Max Power Dissipation
Moisture Sensitivity Level
QFN Package
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
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NCP81119
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −10°C < TA < 100°C; VCC = 5 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
@ 1.3 V
−25
Typ
Max
Unit
25
mA
ERROR AMPLIFIER
Input Bias Current
Open Loop DC Gain
CL = 20 pF to GND,
RL = 10 kW to GND
80
dB
Open Loop Unity Gain Bandwidth
CL = 20 pF to GND,
RL = 10 kW to GND
20
MHz
DVin = 100 mV, G = −10 V/V,
DVout = 1.5 V – 2.5 V,
CL = 20 pF to GND,
DC Load = 10k to GND
20
V/ms
Slew Rate
Maximum Output Voltage
ISOURCE = 2.0 mA
Minimum Output Voltage
ISINK = 2.0 mA
3.5
V
1
V
−15
15
uA
VSP Input Voltage Range
−0.3
3.0
V
VSN Input Voltage Range
−0.3
0.3
V
DIFFERENTIAL SUMMING AMPLIFIER
Input Bias Current
−3dB Bandwidth
Closed Loop DC gain
VSP, VSN = 1.3 V
CL = 20 pF to GND,
RL = 10 kW to GND
VS+ to VS− = 0.5 to 1.3 V
10
MHz
1.0
V/V
CURRENT SUMMING AMPLIFIER
Offset Voltage (Vos)
Input Bias Current
CSSUM = CSREF= 1 V
−300
300
mV
−10
10
mA
Open Loop Gain
Current Sense Unity Gain Bandwidth
CL = 20 pF to GND,
RL = 10 kW to GND
80
dB
10
MHz
CURRENT BALANCE AMPLIFIER
Maximum CSCOMP Output Voltage
Isource = 2 mA
Minimum CSCOMP Output Voltage
Isink = 500 mA
Input Bias Current
3.5
V
0.1
CSP1−4 = CSN1−4 = 1.2
V
nA
−50
50
Common Mode Input Voltage Range
CSPx = CSNx
0
2.3
V
Differential Mode Input Voltage Range
CSNx = 1.2 V
−100
100
mV
Input Offset Voltage Matching
CSPx = CSNx = 1.2 V,
Measured from the average
−1.5
1.5
mV
Current Sense Amplifier Gain
0 V < CSPx − CSNx < 0.1 V,
5.7
6.3
V/V
Multiphase Current Sense Gain Matching
CSP−CSN = 10 mV to 30 mV
−3
3
%
−3dB Bandwidth
6.0
8
MHz
INPUT SUPPLY
4.75
Supply Voltage Range
VCC Quiescent Current
5.25
V
EN = high, PS0,1,2 Mode
25
mA
EN = high, PS3 Mode
15
mA
EN = low
30
mA
3. Guaranteed by design or characterization data, not in production test.
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NCP81119
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −10°C < TA < 100°C; VCC = 5 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Typ
Max
Unit
4.5
V
INPUT SUPPLY
UVLO Threshold
VCC rising
VCC falling
4
VCC UVLO Hysteresis
V
160
UVLO Threshold
VRMP rising
VRMP failing
mV
4.2
3
V
V
DAC SLEW RATE
Soft Start Slew Rate
5
mv/ms
Slew Rate Slow
5
mv/ms
Slew Rate Fast
20
mv/ms
ENABLE INPUT
Enable High Input Leakage Current
External 1k pull−up to 3.3 V
Upper Threshold
VUPPER
Lower Threshold
VLOWER
Total Hysteresis
VUPPER – VLOWER
Enable Delay Time
1.0
0.8
mA
V
0.3
90
Measure time from Enable
transitioning HI to when DRON goes
high
V
mV
5
ms
DRON
Output High Voltage
Sourcing 500 mA
Output Low Voltage
Rise Time
3.0
V
0.1
Sinking 500 mA
CL (PCB) = 20 pF,
DVo = 10% to 90%
Fall Time
Internal Pull Down Resistance
EN = Low
V
156
ns
55
ns
70
kW
IOUT OUTPUT
Ilimit to CSREF
Input Referred Offset Voltage
Output Source Current
Current Gain
−1.75
Ilimit sink current = 80 mA
(IOUTCURRENT) / (ILIMITCURRENT),
RILIM = 20k, RIOUT = 5.0k , DAC =
0.8 V, 1.25 V, 1.52 V
9.5
10
1.75
mV
850
mA
10.5
OSCILLATOR
280
Switching Frequency Range
4 Phase Operation
600
KHz
600
kHz
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
CSREF
2.8
2.9
3
V
VSP rising
350
400
425
mV
Absolute Over Voltage Threshold During Soft Start
Over Voltage Threshold Above DAC
Over Voltage Delay
VSP rising to PWMx low
50
ns
Under Voltage
Ckt in development
300
mV
Under−voltage Delay
Ckt in development
5
ms
3. Guaranteed by design or characterization data, not in production test.
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NCP81119
ELECTRICAL CHARACTERISTICS
Unless otherwise stated: −10°C < TA < 100°C; VCC = 5 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min
Typ
Max
Unit
(−10°C − + 85°C)
1.5 V ≤ DAC < 2.3 V
1.0 V< DAC < 1.49 V
0.5 V threshold
Low
Low
Disabled
Low
Start up Delay &
Calibration
EN > threshold
UVLO > threshold
Low
Low
Disabled
Low
DRON Fault
EN > threshold
UVLO > threshold
DRON < threshold
Low
Low
Disabled
Resistive pull up
Soft Start
EN > threshold
UVLO > threshold
DRON > High
Low
Operational
Active /
No latch
High
Normal Operation
EN > threshold
UVLO >threshold
DRON > High
High
Operational
Active /
Latching
High
Over Voltage
Low
N/A
DAC + 150 mV
High
Over Current
Low
Operational
Last DAC Code
Low
VID Code = 00h
Low: if Reg34h:bit0 = 0;
High:if Reg34h:bit0 = 1
Clamped at
0.9 V
Disabled
High, PWM outputs
in low state
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Method of
Reset
Driver must
release DRON
to high
N/A
NCP81119
(VCCANDVRMP) > UVLO
Controller
POR
Disable
EN = 1
VCC < UVLO OR
VRMP < UVLO
Calibrate
Cal Done
Phase Detection and
Power On Configuration
POC done
Set DRVON High
VCCP > UVLO and DRVON High
EN = 0
Check VBoot
VBoot > 0V
DRVON Latch off
Turn off Drive
VBoot = 0 V
DRVON
Pulled Low
Wait for SVID
command
DRVON
Pulled Low
DRVON Pulled Low
EN = 0
First VID code programmed
EN = 0
Boost Cap Refresh
Boost cap done
OVP Latch off.
VR_RDY = Low
Ramp output to 0V
then force LS ON
CSREF OVP
occurs
Soft Start Ramp
Current Limit
Occurs
Soft start done
Turn off Drive
VR_RDY = Low.
Maintain DAC voltage
and monitor for OVP
Current Limit
Occurs
(DAC + 400mV) OVP or
CSREF OVP occurs
Normal Operation,
VR_RDY = High
DAC = VID/offset programmed.
Power state = PS programmed
UVP Occurs
VR_RDY = Low
DAC = VID/offset programmed.
Power state = PS programmed
Figure 5.
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(DAC + 400mV) OVP
or CSREF OVP occurs
DRVON Pulled
Low
EN = 0
NCP81119
General
The NCP81119 is a four phase dual edge modulated multiphase PWM controller, designed to meet the Intel VR12.5
specifications with a serial SVID control interface. The NCP81119 implements PS0, PS1, PS2 and PS3 power saving states.
It is designed to work in notebook, desktop, and server applications.
Power Status
PWM Output Operating Mode
PS0
Multi−phase PWM interleaving output
PS1
Single−phase RPM CCM mode (PWM1 or PWM3, PWM2~4 stay in Mid)
PS2
Single−phase RPM DCM mode (PWM1 only, PWM2~4 stay in Mid)
PS3
Single−phase RPM DCM mode (PWM1 only, PWM2~4 stay in Mid)
Serial VID interface (SVID)
The Serial VID Interface (SVID Interface) is a 3 wire digital interface used to transfer power management information
between the CPU (Master) and the NCP81119 (Slave). The 3 wires are clock (SCLK), data (SDIO) and ALERT#. The SCLK
is unidirectional and generated by the master. The SDIO is bi−directional, used for transferring data from the CPU to the
NCP81119 and from the NCP81119 to the CPU. The ALERT# is an open drain output from the NCP81119 to signal to the
master that the Status Register should be read.
SCLK, SDIO and ALERT# should be pulled high to CPU I/O voltage VTT (which is typically 1.0 to 1.1 V) using 55 W
Resistors. The SVID bus will operate at a max frequency of 43 MHz.
VID code change is supported by SVID interface with three options as below:
SVID Command
Code
Option
Register Address
(Indicating the slew rate of VID code change)
Feature
SetVID_Fast
01h
>10 mV/ms VID code change slew
rate
24h
SetVID_Slow
02h
=1/4 of SetVID_Fast VID code
change slew rate
25h
SetVID_Decay
03h
No control, VID code down
N/A
Serial VID
The NCP81119 supports the Intel serial VID interface. It communicates with the microprocessor through three wires (SCLK,
SDIO, ALERT#). The table of supported registers is shown below.
Index
Name
Description
Access
Default
00h
Vendor ID
Uniquely identifies the VR vendor. The vendor ID assigned by Intel to
ON Semiconductor is 0x1Ah
R
0x1Ah
01h
Product ID
Uniquely identifies the VR product. The VR vendor assigns this
number.
R
0x12
02h
Product Revision
Uniquely identifies the revision or stepping of the VR control IC. The
VR vendor assigns this data.
R
0x04
03h
Product date code
ID
R
00
05h
Protocol ID
Identifies the SVID Protocol the controller supports
R
0x02
06h
Capability
Informs the Master of the controller’s Capabilities, 1 = supported, 0 =
not supported
Bit 7 = Iout_format. Bit 7 = 0 when 1A = 1LSB of Reg 15h. Bit 7 = 1
when Reg 15 FFh = Icc_Max. Default = 1
Bit 6 = ADC Measurement of Temp Supported = 1
Bit 5 = ADC Measurement of Pin Supported = 0
Bit 4 = ADC Measurement of Vin Supported = 1
Bit 3 = ADC Measurement of Iin Supported = 0
Bit 2 = ADC Measurement of Pout Supported = 1
Bit 1 = ADC Measurement of Vout Supported = 1
Bit 0 = ADC Measurement of Iout Supported = 1
R
0xD7
10h
Status_1
Data register read after the ALERT# signal is asserted. Conveying
the status of the VR.
R
00h
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NCP81119
Index
Name
11h
Status_2
12h
Description
Access
Default
Data register showing optional status_2 data.
R
00h
Temp zone
Data register showing temperature zones the system is operating in
R
00h
15h
I_out
8 bit binary word ADC of current. This register reads 0xFF when the
output current is at Icc_Max
R
01h
16h
V_out
8 bit binary word ADC of output voltage, measured between VSP and
VSN. LSB size is 15.5 mV
R
01h
17h
VR_Temp
8 bit binary word ADC of voltage. Binary format in deg C, IE 100C =
64h. A value of 00h indicates this function is not supported
R
01h
18h
P_out
8 bit binary word representative of output power. The output voltage
is multiplied by the output current value and the result is stored in this
register. A value of 00h indicates this function is not supported
R
01h
1Ah
V_in
1Ch
Status 2 Last read
When the status 2 register is read its contents are copied into this
register. The format is the same as the Status 2 Register.
R
00h
21h
Icc_Max
Data register containing the Icc_Max the platform supports. The
value is measured on the ICCMAX pin on power up and placed in
this register. From that point on the register is read only.
R
00h
22h
Temp_Max
R/W
64h
24h
SR_fast
Slew Rate for SetVID_fast commands. Binary format in mV/us.
R
0Ah
25h
SR_slow
Slew Rate for SetVID_slow commands. It is 4 times slower than the
SR_fast rate. Binary format in mV/us
R
02h
26h
Vboot
The Vboot is programmed using resistors on the Vboot pin which is
sensed on power up. The controller will ramp to Vboot and hold at
Vboot until it receives a new SVID SetVID command to move to a
different voltage.
R
00h
30h
Vout_Max
Programmed by master and sets the maximum VID the VR will
support. If a higher VID code is received, the VR should respond with
“not supported” acknowledge. VR 12.5 VID format.
RW
B5h
31h
VID setting
Data register containing currently programmed VID voltage. VID data
format.
RW
00h
32h
Pwr State
Register containing the current programmed power state.
RW
00h
33h
Offset
Sets offset in VID steps added to the VID setting for voltage
margining. Bit 7 is sign bit, 0=positive margin, 1= negative margin.
Remaining 7 BITS are # VID steps for margin 2s complement.
00h = no margin
01h = +1 VID step
02h = +2 VID steps
FFh = −1 VID step
FEh = −2 VID steps.
RW
00h
34h
MultiVR Config
8 bit binary word ADC of input voltage. LSB size = 110 mV.
Data register containing the max temperature the platform supports
and the level VR_hot asserts. This value defaults to 100°C and
programmable over the SVID Interface
BOOT VOLTAGE PROGRAMMING
The NCP81119 has a Vboot voltage register that can be externally programmed. The Boot voltage for the NCP81119 is set
using VBOOT pin on power up. A 10uA current is sourced from the VBoot pin and the resulting voltage is measured. This
is compared with the thresholds in Table below and the corresponding value is placed in the VBoot registers (0x26). This value
is set on power up and cannot be changed after the initial power up sequence is complete.
BOOT VOLTAGE TABLE
R
VBoot
Phase Number in PS1
30.1k
0V
1
49.9k
1.65 V
1
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NCP81119
BOOT VOLTAGE TABLE
R
VBoot
Phase Number in PS1
69.8k
1.70 V
1
90.9k
1.75 V
1
130k
0V
2
150k
1.65 V
2
169k
1.70 V
2
Open
1.75 V
2
Remote Sense Amplifier
A high performance high input impedance true differential amplifier is provided to accurately sense the output voltage of
the regulator. The VSP and VSN inputs should be connected to the regulator’s output voltage sense points. The remote sense
amplifier takes the difference of the output voltage with the DAC voltage and adds the droop voltage to
V DIFOUT + ǒV VSP * V VSNǓ ) ǒ1.3 V * V DACǓ ) ǒV DROOP * V CSREFǓ
This signal then goes through a standard error compensation network and into the inverting input of the error amplifier. The
non−inverting input of the error amplifier is connected to the same 1.3 V reference used for the differential sense amplifier
output bias.
Addressing Programming
The NCP81119 supports 9 possible SVID device addresses. Pin 12 (PWM1/ADDR) is used to set the SVID address. On
power up a 10uA current is sourced from this pin through a resistor connected to this pin and the resulting voltage is measured.
Table below provides the resistor values for each corresponding SVID address. The address value is latched at startup.
SVID Address Table
Missing SVID Table
Resistor Value
SVID Address
10 k
0000
22 k
0001
36 k
0010
51 k
0011
68 k
0100
91 k
0101
120 k
0110
160 k
0111
220 k
1000
Differential Current Feedback Amplifiers
CSNx
RCSN
CSPx
Each phase has a low offset differential amplifier to sense that phase current for current balance. The inputs to the CSNx and
CSPx pins are high impedance inputs. It is recommended that any external filter resistor RCSN does not exceed 10 kW to avoid
offset issues with leakage current. It is also recommended that the voltage sense element be no less than 0.5 mW for accurate
current balance. Fine tuning of this time constant is generally not required. The individual phase current is summed into the
PWM comparator feedback this way current is balanced via a current mode control approach.
CCSN
R CSN +
SWNx
VOUT
DCR
1
LPHASE
2
Figure 6.
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L PHASE
C CSN * DCR
NCP81119
Total Current Sense Amplifier
The NCP81119 uses a patented approach to sum the phase currents into a single temperature compensated total current signal.
This signal is then used to generate the output voltage droop, total current limit, and the output current monitoring functions.
The total current signal is floating with respect to CSREF. The current signal is the difference between CSCOMP and CSREF.
The Ref(n) resistors sum the signals from the output side of the inductors to create a low impedance virtual ground, the capacitor
is used to ensure that the CSREF voltage signal integrity. The amplifier actively filters and gains up the voltage applied across
the inductors to recover the voltage drop across the inductor series resistance (DCR). Rth is placed near an inductor to sense
the temperature of the inductor. This allows the filter time constant and gain to be a function of the Rth NTC resistor and
compensate for the change in the DCR with temperature.
Rref1 10
CSN1
CSN2
CSN3
CSN4
Rref2
10
Rfer3
10
Rref4
10
Cref
1nF
0
U1A
CSREF
+
CSSUM
CSCOMP
−
Ccs1
Rph1
SWN1
Ccs2
Rph2
SWN2
R10
Rph3
R9
SWN3
R
Rph4
R
SWN4
t
RT1
100k
Figure 7.
The DC gain equation for the current sensing:
Rcs1*Rth
V CSCOMP−CSREF +
Rcs2 ) Rcs1)Rth
Rph
* ǒIout Total * DCRǓ
Set the gain by adjusting the value of the Rph resistors. The DC gain should be set to the output voltage droop. If the voltage
from CSCOMP to CSREF is less than 100 mV at ICCMAX then it is recommend increasing the gain of the CSCOMP amp.
This is required to provide a good current signal to offset voltage ratio for the ILIMIT pin. When no droop is needed, the gain
of the amplifier should be set to provide ~100mV across the current limit programming resistor at full load. The values of Rcs1
and Rcs2 are set based on the 100k NTC and the temperature effect of the inductor and should not need to be changed. The
NTC should be placed near the closest inductor. The output voltage droop should be set with the droop filter divider.
The pole frequency in the CSCOMP filter should be set equal to the zero from the output inductor. This allows the circuit
to recover the inductor DCR voltage drop current signal. Ccs1 and Ccs2 are in parallel to allow for fine tuning of the time
constant using commonly available values. It is best to fine tune this filter during transient testing.
Fz +
DCR@25° C
2 * PI * L Phase
Programming the Current Limit
The current limit thresholds are programmed with a resistor between the ILIMIT and CSCOMP pins. The ILIMIT pin mirrors
the voltage at the CSREF pin and mirrors the sink current internally to IOUT (reduced by the IOUT Current Gain) and the
current limit comparators. The 100% current limit trips if the ILIMIT sink current exceeds 10 mA for 50 ms. The 150% current
limit trips with minimal delay if the ILIMIT sink current exceeds 15 mA. Set the value of the current limit resistor based on
the CSCOMP−CSREF voltage as shown below.
Rcs1*Rth
Rcs2)Rcs1)Rth
R LIMIT +
Rph
* ǒIout LIMIT * DCRǓ
10m
or R LIMIT +
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lV CSCOMP−CSREF@ILIMIT
10m
NCP81119
Programming IOUT
The IOUT pin sources a current in proportion to the ILIMIT sink current. The voltage on the IOUT pin is monitored by the
internal A/D converter and should be scaled with an external resistor to ground such that a load equal to ICCMAX generates
a 2 V signal on IOUT. A pull−up resistor from 5 V VCC can be used to offset the IOUT signal positive if needed.
2.0 V * R LIMIT
R IOUT +
10 *
Rcs1*Rth
Rcs2)
Rcs1)Rth
Rph
* ǒIout ICC_MAX * DCRǓ
Programming ICC_MAX
The SVID interface provides the platform ICC_MAX value at register 21h for. A resistor to ground on the IMAX pin
programs these registers at the time the part is enabled. 10 mA is sourced from these pins to generate a voltage on the program
resistor. The value of the register is 1 A per LSB and is set by the equation below. The resistor value should be no less than 10k.
ICC_MAX 21h +
R * 10 mA * 256 A
2V
Programming TSENSE
A temperature sense inputs are provided. A precision current is sourced out the output of the TSENSE pin to generate a
voltage on the temperature sense network. The voltage on the temperature sense input is sampled by the internal A/D converter.
A 100k NTC similar to the VISHAY ERT−J1VS104JA should be used. Rcomp1 is mainly used for noise. See the specification
table for the thermal sensing voltage thresholds and source current.
TSENSE
Rcomp1
0.0
Cfilter
0.1uF
Rcomp2
8.2K
AGND
RNTC
100K
AGND
Figure 8.
Precision Oscillator
A programmable precision oscillator is provided. The clock oscillator serves as the master clock to the ramp generator circuit.
This oscillator is programmed by a resistor to ground on the ROSC pin. The oscillator frequency range is between 280 kHz
to 650 kHz on the NCP81119 The graph below lists the resistor options and associated frequency setting.
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NCP81119
NCP81119 Operating Frequency vs. Rosc
Figure 9. NCP81119 Rosc vs. Frequency
The oscillator generates triangle ramps that are 0.5~2.5 V in amplitude depending on the VRMP pin voltage to provide input
voltage feed forward compensation. The ramps are equally spaced out of phase with respect to each other.
Programming the Ramp Feed−Forward Circuit
The ramp generator circuit provides the ramp used by the PWM comparators. The ramp generator provides voltage
feed−forward control by varying the ramp magnitude with respect to the VRMP pin voltage. The VRMP pin also has a 4 V
UVLO function. The VRMP UVLO is only active after the controller is enabled. The VRMP pin is high impedance input when
the controller is disabled.
The PWM ramp time is changed according to the following,
V RAMPpkäpkPP + 0.1 * V VRMP
Vin
Vramp_pp
Comp−IL
Duty
PWM Comparators
The noninverting input of the comparator for each phase is connected to the summed output of the error amplifier (COMP)
and each phase current (IL*DCR*Phase Balance Gain Factor). The inverting input is connected to the oscillator ramp voltage
with a 1.3 V offset. The operating input voltage range of the comparators is from 0 V to 3.0 V and the output of the comparator
generates the PWM output.
During steady state operation, the duty cycle is centered on the valley of the sawtooth ramp waveform. The steady state duty
cycle is still calculated by approximately Vout/Vin. During a transient event, the controller will operate in a hysteretic mode
with the duty cycles pull in for all phases as the error amp signal increases with respect to all the ramps.
PHASE DETECTION SEQUENCE
During start−up, the number of operational phases and their phase relationship is determined by the internal circuitry
monitoring the CSN Pins. Normally, NCP81119 operates as a 4−phase Vcore PWM controller. Connecting CSN4 pin to VCC
programs 3−phase operation, connecting CSN2 and CSN4 pin to VCC programs 2−phase operation, connecting CSN2, CSN3
and CSN4 pin to VCC programs 1−phase operation. Prior to soft start, while ENABLE is high, CSN4 to CSN2 pins sink
approximately 50 mA. An internal comparator checks the voltage of each pin versus a threshold of 4.5 V. If the pin is tied to
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NCP81119
VCC, its voltage is above the threshold. Otherwise, an internal current sink pulls the pin to GND, which is below the threshold.
PWM1 is low during the phase detection interval, which takes 30 ms. After this time, if the remaining CSN outputs are not
pulled to VCC, the 50 mA current sink is removed, and NCP81119 functions as normal 4 phase controller. If the CSNs are pulled
to VCC, the 50 mA current source is removed, and the outputs are driven into a high impedance state.
The PWM outputs are logic−level devices intended for driving fast response external gate drivers such as the NCP5901 and
NCP5911 .Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition,
more than one PWM output can be on at the same time to allow overlapping phases.
PROTECTION FEATURES
Under voltage Lockouts
There are several under voltage monitors in the system. Hysteresis is incorporated within the comparators. NCP81119
monitors the VCC Shunt supply. The gate driver monitors both the gate driver VCC and the BST voltage. When the voltage
on the gate driver is insufficient it will pull DRON low and prevents the controller from being enabled. The gate driver will
hold DRON low for a minimum period of time to allow the controller to hold off it’s startup sequence. In this case the PWM
is set to the MID state to begin soft start.
Gate Driver UVLO Restart
Figure 10.
Soft Start
Soft start is implemented internally. A digital counter steps the DAC up from zero to the target voltage based on the
predetermined rate in the spec table. The PWM signals will start out open with a test current to collect data on phase count and
for setting internal registers. After the configuration data is collected, if the controller is enabled the PWMs will be set to 2.0 V
MID state to indicate that the drivers should be in diode mode. DRON will then be asserted. As the DAC ramps the PWM
outputs will begin to fire. Each phase will move out of the MID state when the first PWM pulse is produced. When the controller
is disabled the PWM signal will return to the MID state.
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NCP81119
Figure 11.
Over Current Latch− Off Protection
The NCP81119 compares a programmable current−limit set point to the voltage from the output of the current−summing
amplifier. The level of current limit is set with the resistor from the ILIM pin to CSCOMP. The current through the external
resistor connected between ILIM and CSCOMP is then compared to the internal current limit current ICL. If the current
generated through this resistor into the ILIM pin (Ilim) exceeds the internal current−limit threshold current (ICL), an internal
latch−off counter starts, and the controller shuts down if the fault is not removed after 50 ms (shut down immediately for 150%
load current) after which the outputs will remain disabled until the VCC voltage or EN is toggled.
On startup a clim1/clim2 current limit protection is enabled once the output voltage has exceeded 250 mV or if the internal
DAC voltage has increased above 300 mV, this allow for protection again a Vout short to ground. This is necessary because
the voltage swing of CSCOMP cannot go below ground. This limits the voltage drop across the DCR through the current
balance circuitry.
The over−current limit is programmed by a resistor on the ILIM pin. The resistor value can be calculated by the following
equation:
R ILIM +
I LIM * DCR * R CSńR PH
I CL
Where ICL = 10 mA
CSSUM
RCS
RPH
RPH
RPH
RPH
CSCOMP
RLIM
ILIM
CSREF
Figure 12.
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NCP81119
Under Voltage Monitor
The output voltage is monitored at the output of the differential amplifier for UVLO. If the output falls more than 300mV
below the DAC−DROOP voltage the UVLO comparator will trip sending the VR_RDY signal low.
Over Voltage Protection
The output voltage is also monitored at the output of the differential amplifier for OVP. During normal operation, if the output
voltage exceeds the DAC voltage by 400 mV, the VR_RDY flag goes low, and the DAC will be ramped down to 0 V. At the
same time, the high side gate drivers are all turned off and the low side gate drivers are all turned on until the voltage falls to
new DAC voltage 0.2 V. The part will stay in this mode until the VCC voltage or EN is toggled.
OVP Threshold Behavior
VCC
UVLO RISING
OVP Threshold
DAC + ~400 mV
2.9 V
DAC
DRON
Figure 13. OVP Threshold Behavior
OVP Behavior at Startup
OVP Threshold
2.9 V
Vout
DAC
DRON
PWM
Figure 14. OVP Behavior at Startup
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NCP81119
OVP Threshold
DAC
VSP_VSN
OVP
Triggered
Latch Off
PWM
Figure 15. OVP During Normal Operation Mode
During start up, the OVP threshold is set to 2.9 V. This allows the controller to start up without false triggering the OVP.
ORDERING INFORMATION
Device
NCP81119MNTXG
Package
Shipping†
QFN32
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NCP81119
PACKAGE DIMENSIONS
WQFN32 4x4, 0.4P
CASE 510AT
ISSUE O
PIN ONE
REFERENCE
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
B
A
D
L
L1
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
EXPOSED Cu
TOP VIEW
A
0.05 C
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
L3
ÉÉÉ
ÉÉÉ
0.10 C
0.10 C
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
MOLD CMPD
DETAIL B
ALTERNATE
CONSTRUCTION
A3
0.05 C
DETAIL B
NOTE 4
A1
SIDE VIEW
RECOMMENDED
MOUNTING FOOTPRINT*
SEATING
PLANE
C
0.10 C A B
DETAIL A
D2
9
L3
1
2.80
DETAIL C
8X
1
0.10 C A B
25
32X
BOTTOM VIEW
4.30
CORNER LEAD
CONSTRUCTION
E2
e
32X
0.58
L3
L
DETAIL C
4.30
2.80
PACKAGE
OUTLINE
K
17
32X
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.15
0.25
4.00 BSC
2.60
2.80
4.00 BSC
2.60
2.80
0.40 BSC
0.30 REF
0.25
0.45
−−−
0.15
0.17 REF
b
0.07
M
C A B
0.05
M
C
C0.08
0.40
PITCH
32X
0.25
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
NOTE 3
Intel is a registered trademark of Intel Corporation in the U.S. and/or other countries.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP81119/D
